1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Machine check exception handling CPU-side for power7 and power8
4 *
5 * Copyright 2013 IBM Corporation
6 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
7 */
8
9 #undef DEBUG
10 #define pr_fmt(fmt) "mce_power: " fmt
11
12 #include <linux/types.h>
13 #include <linux/ptrace.h>
14 #include <linux/extable.h>
15 #include <linux/pgtable.h>
16 #include <asm/mmu.h>
17 #include <asm/mce.h>
18 #include <asm/machdep.h>
19 #include <asm/pte-walk.h>
20 #include <asm/sstep.h>
21 #include <asm/exception-64s.h>
22 #include <asm/extable.h>
23 #include <asm/inst.h>
24
25 /*
26 * Convert an address related to an mm to a PFN. NOTE: we are in real
27 * mode, we could potentially race with page table updates.
28 */
addr_to_pfn(struct pt_regs * regs,unsigned long addr)29 unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
30 {
31 pte_t *ptep, pte;
32 unsigned int shift;
33 unsigned long pfn, flags;
34 struct mm_struct *mm;
35
36 if (user_mode(regs))
37 mm = current->mm;
38 else
39 mm = &init_mm;
40
41 local_irq_save(flags);
42 ptep = __find_linux_pte(mm->pgd, addr, NULL, &shift);
43 if (!ptep) {
44 pfn = ULONG_MAX;
45 goto out;
46 }
47 pte = READ_ONCE(*ptep);
48
49 if (!pte_present(pte) || pte_special(pte)) {
50 pfn = ULONG_MAX;
51 goto out;
52 }
53
54 if (shift <= PAGE_SHIFT)
55 pfn = pte_pfn(pte);
56 else {
57 unsigned long rpnmask = (1ul << shift) - PAGE_SIZE;
58 pfn = pte_pfn(__pte(pte_val(pte) | (addr & rpnmask)));
59 }
60 out:
61 local_irq_restore(flags);
62 return pfn;
63 }
64
65 /* flush SLBs and reload */
66 #ifdef CONFIG_PPC_BOOK3S_64
flush_and_reload_slb(void)67 void flush_and_reload_slb(void)
68 {
69 /* Invalidate all SLBs */
70 slb_flush_all_realmode();
71
72 #ifdef CONFIG_KVM_BOOK3S_HANDLER
73 /*
74 * If machine check is hit when in guest or in transition, we will
75 * only flush the SLBs and continue.
76 */
77 if (get_paca()->kvm_hstate.in_guest)
78 return;
79 #endif
80 if (early_radix_enabled())
81 return;
82
83 /*
84 * This probably shouldn't happen, but it may be possible it's
85 * called in early boot before SLB shadows are allocated.
86 */
87 if (!get_slb_shadow())
88 return;
89
90 slb_restore_bolted_realmode();
91 }
92 #endif
93
flush_erat(void)94 static void flush_erat(void)
95 {
96 #ifdef CONFIG_PPC_BOOK3S_64
97 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
98 flush_and_reload_slb();
99 return;
100 }
101 #endif
102 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory");
103 }
104
105 #define MCE_FLUSH_SLB 1
106 #define MCE_FLUSH_TLB 2
107 #define MCE_FLUSH_ERAT 3
108
mce_flush(int what)109 static int mce_flush(int what)
110 {
111 #ifdef CONFIG_PPC_BOOK3S_64
112 if (what == MCE_FLUSH_SLB) {
113 flush_and_reload_slb();
114 return 1;
115 }
116 #endif
117 if (what == MCE_FLUSH_ERAT) {
118 flush_erat();
119 return 1;
120 }
121 if (what == MCE_FLUSH_TLB) {
122 tlbiel_all();
123 return 1;
124 }
125
126 return 0;
127 }
128
129 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
130
131 struct mce_ierror_table {
132 unsigned long srr1_mask;
133 unsigned long srr1_value;
134 bool nip_valid; /* nip is a valid indicator of faulting address */
135 unsigned int error_type;
136 unsigned int error_subtype;
137 unsigned int error_class;
138 unsigned int initiator;
139 unsigned int severity;
140 bool sync_error;
141 };
142
143 static const struct mce_ierror_table mce_p7_ierror_table[] = {
144 { 0x00000000001c0000, 0x0000000000040000, true,
145 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
146 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
147 { 0x00000000001c0000, 0x0000000000080000, true,
148 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
149 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
150 { 0x00000000001c0000, 0x00000000000c0000, true,
151 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
152 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
153 { 0x00000000001c0000, 0x0000000000100000, true,
154 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
155 MCE_ECLASS_SOFT_INDETERMINATE,
156 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
157 { 0x00000000001c0000, 0x0000000000140000, true,
158 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
159 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
160 { 0x00000000001c0000, 0x0000000000180000, true,
161 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
162 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
163 { 0x00000000001c0000, 0x00000000001c0000, true,
164 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
165 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
166 { 0, 0, 0, 0, 0, 0, 0 } };
167
168 static const struct mce_ierror_table mce_p8_ierror_table[] = {
169 { 0x00000000081c0000, 0x0000000000040000, true,
170 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
171 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
172 { 0x00000000081c0000, 0x0000000000080000, true,
173 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
174 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
175 { 0x00000000081c0000, 0x00000000000c0000, true,
176 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
177 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
178 { 0x00000000081c0000, 0x0000000000100000, true,
179 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
180 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
181 { 0x00000000081c0000, 0x0000000000140000, true,
182 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
183 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
184 { 0x00000000081c0000, 0x0000000000180000, true,
185 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
186 MCE_ECLASS_HARDWARE,
187 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
188 { 0x00000000081c0000, 0x00000000001c0000, true,
189 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
190 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
191 { 0x00000000081c0000, 0x0000000008000000, true,
192 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
193 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
194 { 0x00000000081c0000, 0x0000000008040000, true,
195 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
196 MCE_ECLASS_HARDWARE,
197 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
198 { 0, 0, 0, 0, 0, 0, 0 } };
199
200 static const struct mce_ierror_table mce_p9_ierror_table[] = {
201 { 0x00000000081c0000, 0x0000000000040000, true,
202 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
203 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
204 { 0x00000000081c0000, 0x0000000000080000, true,
205 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
206 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
207 { 0x00000000081c0000, 0x00000000000c0000, true,
208 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
209 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
210 { 0x00000000081c0000, 0x0000000000100000, true,
211 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
212 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
213 { 0x00000000081c0000, 0x0000000000140000, true,
214 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
215 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
216 { 0x00000000081c0000, 0x0000000000180000, true,
217 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
218 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
219 { 0x00000000081c0000, 0x00000000001c0000, true,
220 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
221 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
222 { 0x00000000081c0000, 0x0000000008000000, true,
223 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
224 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
225 { 0x00000000081c0000, 0x0000000008040000, true,
226 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
227 MCE_ECLASS_HARDWARE,
228 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
229 { 0x00000000081c0000, 0x00000000080c0000, true,
230 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
231 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
232 { 0x00000000081c0000, 0x0000000008100000, true,
233 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
234 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
235 { 0x00000000081c0000, 0x0000000008140000, false,
236 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
237 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
238 { 0x00000000081c0000, 0x0000000008180000, false,
239 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
240 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
241 { 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
242 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
243 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
244 { 0, 0, 0, 0, 0, 0, 0 } };
245
246 static const struct mce_ierror_table mce_p10_ierror_table[] = {
247 { 0x00000000081c0000, 0x0000000000040000, true,
248 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
249 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
250 { 0x00000000081c0000, 0x0000000000080000, true,
251 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
252 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
253 { 0x00000000081c0000, 0x00000000000c0000, true,
254 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
255 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
256 { 0x00000000081c0000, 0x0000000000100000, true,
257 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
258 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
259 { 0x00000000081c0000, 0x0000000000140000, true,
260 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
261 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
262 { 0x00000000081c0000, 0x0000000000180000, true,
263 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
264 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
265 { 0x00000000081c0000, 0x00000000001c0000, true,
266 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
267 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
268 { 0x00000000081c0000, 0x0000000008080000, true,
269 MCE_ERROR_TYPE_USER,MCE_USER_ERROR_SCV, MCE_ECLASS_SOFTWARE,
270 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
271 { 0x00000000081c0000, 0x00000000080c0000, true,
272 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
273 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
274 { 0x00000000081c0000, 0x0000000008100000, true,
275 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
276 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
277 { 0x00000000081c0000, 0x0000000008140000, false,
278 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
279 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
280 { 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
281 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
282 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
283 { 0, 0, 0, 0, 0, 0, 0 } };
284
285 struct mce_derror_table {
286 unsigned long dsisr_value;
287 bool dar_valid; /* dar is a valid indicator of faulting address */
288 unsigned int error_type;
289 unsigned int error_subtype;
290 unsigned int error_class;
291 unsigned int initiator;
292 unsigned int severity;
293 bool sync_error;
294 };
295
296 static const struct mce_derror_table mce_p7_derror_table[] = {
297 { 0x00008000, false,
298 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
299 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
300 { 0x00004000, true,
301 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
302 MCE_ECLASS_HARDWARE,
303 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
304 { 0x00000800, true,
305 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
306 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
307 { 0x00000400, true,
308 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
309 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
310 { 0x00000080, true,
311 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
312 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
313 { 0x00000100, true,
314 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
315 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
316 { 0x00000040, true,
317 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
318 MCE_ECLASS_HARD_INDETERMINATE,
319 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
320 { 0, false, 0, 0, 0, 0, 0 } };
321
322 static const struct mce_derror_table mce_p8_derror_table[] = {
323 { 0x00008000, false,
324 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
325 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
326 { 0x00004000, true,
327 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
328 MCE_ECLASS_HARDWARE,
329 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
330 { 0x00002000, true,
331 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
332 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
333 { 0x00001000, true,
334 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
335 MCE_ECLASS_HARDWARE,
336 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
337 { 0x00000800, true,
338 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
339 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
340 { 0x00000400, true,
341 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
342 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
343 { 0x00000200, true,
344 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
345 MCE_ECLASS_SOFT_INDETERMINATE,
346 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
347 { 0x00000080, true,
348 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
349 MCE_ECLASS_SOFT_INDETERMINATE,
350 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
351 { 0x00000100, true,
352 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
353 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
354 { 0, false, 0, 0, 0, 0, 0 } };
355
356 static const struct mce_derror_table mce_p9_derror_table[] = {
357 { 0x00008000, false,
358 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
359 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
360 { 0x00004000, true,
361 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
362 MCE_ECLASS_HARDWARE,
363 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
364 { 0x00002000, true,
365 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
366 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
367 { 0x00001000, true,
368 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
369 MCE_ECLASS_HARDWARE,
370 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
371 { 0x00000800, true,
372 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
373 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
374 { 0x00000400, true,
375 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
376 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
377 { 0x00000200, false,
378 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
379 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
380 { 0x00000080, true,
381 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
382 MCE_ECLASS_SOFT_INDETERMINATE,
383 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
384 { 0x00000100, true,
385 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
386 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
387 { 0x00000040, true,
388 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
389 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
390 { 0x00000020, false,
391 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
392 MCE_ECLASS_HARDWARE,
393 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
394 { 0x00000010, false,
395 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
396 MCE_ECLASS_HARDWARE,
397 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
398 { 0x00000008, false,
399 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
400 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
401 { 0, false, 0, 0, 0, 0, 0 } };
402
403 static const struct mce_derror_table mce_p10_derror_table[] = {
404 { 0x00008000, false,
405 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
406 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
407 { 0x00004000, true,
408 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
409 MCE_ECLASS_HARDWARE,
410 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
411 { 0x00000800, true,
412 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
413 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
414 { 0x00000400, true,
415 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
416 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
417 { 0x00000200, false,
418 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
419 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
420 { 0x00000080, true,
421 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
422 MCE_ECLASS_SOFT_INDETERMINATE,
423 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
424 { 0x00000100, true,
425 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
426 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
427 { 0x00000040, true,
428 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
429 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
430 { 0x00000020, false,
431 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
432 MCE_ECLASS_HARDWARE,
433 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
434 { 0x00000010, false,
435 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
436 MCE_ECLASS_HARDWARE,
437 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
438 { 0x00000008, false,
439 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
440 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
441 { 0, false, 0, 0, 0, 0, 0 } };
442
mce_find_instr_ea_and_phys(struct pt_regs * regs,uint64_t * addr,uint64_t * phys_addr)443 static int mce_find_instr_ea_and_phys(struct pt_regs *regs, uint64_t *addr,
444 uint64_t *phys_addr)
445 {
446 /*
447 * Carefully look at the NIP to determine
448 * the instruction to analyse. Reading the NIP
449 * in real-mode is tricky and can lead to recursive
450 * faults
451 */
452 struct ppc_inst instr;
453 unsigned long pfn, instr_addr;
454 struct instruction_op op;
455 struct pt_regs tmp = *regs;
456
457 pfn = addr_to_pfn(regs, regs->nip);
458 if (pfn != ULONG_MAX) {
459 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
460 instr = ppc_inst_read((struct ppc_inst *)instr_addr);
461 if (!analyse_instr(&op, &tmp, instr)) {
462 pfn = addr_to_pfn(regs, op.ea);
463 *addr = op.ea;
464 *phys_addr = (pfn << PAGE_SHIFT);
465 return 0;
466 }
467 /*
468 * analyse_instr() might fail if the instruction
469 * is not a load/store, although this is unexpected
470 * for load/store errors or if we got the NIP
471 * wrong
472 */
473 }
474 *addr = 0;
475 return -1;
476 }
477
mce_handle_ierror(struct pt_regs * regs,unsigned long srr1,const struct mce_ierror_table table[],struct mce_error_info * mce_err,uint64_t * addr,uint64_t * phys_addr)478 static int mce_handle_ierror(struct pt_regs *regs, unsigned long srr1,
479 const struct mce_ierror_table table[],
480 struct mce_error_info *mce_err, uint64_t *addr,
481 uint64_t *phys_addr)
482 {
483 int handled = 0;
484 int i;
485
486 *addr = 0;
487
488 for (i = 0; table[i].srr1_mask; i++) {
489 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
490 continue;
491
492 /* attempt to correct the error */
493 switch (table[i].error_type) {
494 case MCE_ERROR_TYPE_SLB:
495 if (local_paca->in_mce == 1)
496 slb_save_contents(local_paca->mce_faulty_slbs);
497 handled = mce_flush(MCE_FLUSH_SLB);
498 break;
499 case MCE_ERROR_TYPE_ERAT:
500 handled = mce_flush(MCE_FLUSH_ERAT);
501 break;
502 case MCE_ERROR_TYPE_TLB:
503 handled = mce_flush(MCE_FLUSH_TLB);
504 break;
505 }
506
507 /* now fill in mce_error_info */
508 mce_err->error_type = table[i].error_type;
509 mce_err->error_class = table[i].error_class;
510 switch (table[i].error_type) {
511 case MCE_ERROR_TYPE_UE:
512 mce_err->u.ue_error_type = table[i].error_subtype;
513 break;
514 case MCE_ERROR_TYPE_SLB:
515 mce_err->u.slb_error_type = table[i].error_subtype;
516 break;
517 case MCE_ERROR_TYPE_ERAT:
518 mce_err->u.erat_error_type = table[i].error_subtype;
519 break;
520 case MCE_ERROR_TYPE_TLB:
521 mce_err->u.tlb_error_type = table[i].error_subtype;
522 break;
523 case MCE_ERROR_TYPE_USER:
524 mce_err->u.user_error_type = table[i].error_subtype;
525 break;
526 case MCE_ERROR_TYPE_RA:
527 mce_err->u.ra_error_type = table[i].error_subtype;
528 break;
529 case MCE_ERROR_TYPE_LINK:
530 mce_err->u.link_error_type = table[i].error_subtype;
531 break;
532 }
533 mce_err->sync_error = table[i].sync_error;
534 mce_err->severity = table[i].severity;
535 mce_err->initiator = table[i].initiator;
536 if (table[i].nip_valid) {
537 *addr = regs->nip;
538 if (mce_err->sync_error &&
539 table[i].error_type == MCE_ERROR_TYPE_UE) {
540 unsigned long pfn;
541
542 if (get_paca()->in_mce < MAX_MCE_DEPTH) {
543 pfn = addr_to_pfn(regs, regs->nip);
544 if (pfn != ULONG_MAX) {
545 *phys_addr =
546 (pfn << PAGE_SHIFT);
547 }
548 }
549 }
550 }
551 return handled;
552 }
553
554 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
555 mce_err->error_class = MCE_ECLASS_UNKNOWN;
556 mce_err->severity = MCE_SEV_SEVERE;
557 mce_err->initiator = MCE_INITIATOR_CPU;
558 mce_err->sync_error = true;
559
560 return 0;
561 }
562
mce_handle_derror(struct pt_regs * regs,const struct mce_derror_table table[],struct mce_error_info * mce_err,uint64_t * addr,uint64_t * phys_addr)563 static int mce_handle_derror(struct pt_regs *regs,
564 const struct mce_derror_table table[],
565 struct mce_error_info *mce_err, uint64_t *addr,
566 uint64_t *phys_addr)
567 {
568 uint64_t dsisr = regs->dsisr;
569 int handled = 0;
570 int found = 0;
571 int i;
572
573 *addr = 0;
574
575 for (i = 0; table[i].dsisr_value; i++) {
576 if (!(dsisr & table[i].dsisr_value))
577 continue;
578
579 /* attempt to correct the error */
580 switch (table[i].error_type) {
581 case MCE_ERROR_TYPE_SLB:
582 if (local_paca->in_mce == 1)
583 slb_save_contents(local_paca->mce_faulty_slbs);
584 if (mce_flush(MCE_FLUSH_SLB))
585 handled = 1;
586 break;
587 case MCE_ERROR_TYPE_ERAT:
588 if (mce_flush(MCE_FLUSH_ERAT))
589 handled = 1;
590 break;
591 case MCE_ERROR_TYPE_TLB:
592 if (mce_flush(MCE_FLUSH_TLB))
593 handled = 1;
594 break;
595 }
596
597 /*
598 * Attempt to handle multiple conditions, but only return
599 * one. Ensure uncorrectable errors are first in the table
600 * to match.
601 */
602 if (found)
603 continue;
604
605 /* now fill in mce_error_info */
606 mce_err->error_type = table[i].error_type;
607 mce_err->error_class = table[i].error_class;
608 switch (table[i].error_type) {
609 case MCE_ERROR_TYPE_UE:
610 mce_err->u.ue_error_type = table[i].error_subtype;
611 break;
612 case MCE_ERROR_TYPE_SLB:
613 mce_err->u.slb_error_type = table[i].error_subtype;
614 break;
615 case MCE_ERROR_TYPE_ERAT:
616 mce_err->u.erat_error_type = table[i].error_subtype;
617 break;
618 case MCE_ERROR_TYPE_TLB:
619 mce_err->u.tlb_error_type = table[i].error_subtype;
620 break;
621 case MCE_ERROR_TYPE_USER:
622 mce_err->u.user_error_type = table[i].error_subtype;
623 break;
624 case MCE_ERROR_TYPE_RA:
625 mce_err->u.ra_error_type = table[i].error_subtype;
626 break;
627 case MCE_ERROR_TYPE_LINK:
628 mce_err->u.link_error_type = table[i].error_subtype;
629 break;
630 }
631 mce_err->sync_error = table[i].sync_error;
632 mce_err->severity = table[i].severity;
633 mce_err->initiator = table[i].initiator;
634 if (table[i].dar_valid)
635 *addr = regs->dar;
636 else if (mce_err->sync_error &&
637 table[i].error_type == MCE_ERROR_TYPE_UE) {
638 /*
639 * We do a maximum of 4 nested MCE calls, see
640 * kernel/exception-64s.h
641 */
642 if (get_paca()->in_mce < MAX_MCE_DEPTH)
643 mce_find_instr_ea_and_phys(regs, addr,
644 phys_addr);
645 }
646 found = 1;
647 }
648
649 if (found)
650 return handled;
651
652 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
653 mce_err->error_class = MCE_ECLASS_UNKNOWN;
654 mce_err->severity = MCE_SEV_SEVERE;
655 mce_err->initiator = MCE_INITIATOR_CPU;
656 mce_err->sync_error = true;
657
658 return 0;
659 }
660
mce_handle_ue_error(struct pt_regs * regs,struct mce_error_info * mce_err)661 static long mce_handle_ue_error(struct pt_regs *regs,
662 struct mce_error_info *mce_err)
663 {
664 long handled = 0;
665
666 mce_common_process_ue(regs, mce_err);
667 if (mce_err->ignore_event)
668 return 1;
669
670 /*
671 * On specific SCOM read via MMIO we may get a machine check
672 * exception with SRR0 pointing inside opal. If that is the
673 * case OPAL may have recovery address to re-read SCOM data in
674 * different way and hence we can recover from this MC.
675 */
676
677 if (ppc_md.mce_check_early_recovery) {
678 if (ppc_md.mce_check_early_recovery(regs))
679 handled = 1;
680 }
681 return handled;
682 }
683
mce_handle_error(struct pt_regs * regs,unsigned long srr1,const struct mce_derror_table dtable[],const struct mce_ierror_table itable[])684 static long mce_handle_error(struct pt_regs *regs,
685 unsigned long srr1,
686 const struct mce_derror_table dtable[],
687 const struct mce_ierror_table itable[])
688 {
689 struct mce_error_info mce_err = { 0 };
690 uint64_t addr, phys_addr = ULONG_MAX;
691 long handled;
692
693 if (SRR1_MC_LOADSTORE(srr1))
694 handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
695 &phys_addr);
696 else
697 handled = mce_handle_ierror(regs, srr1, itable, &mce_err, &addr,
698 &phys_addr);
699
700 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
701 handled = mce_handle_ue_error(regs, &mce_err);
702
703 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
704
705 return handled;
706 }
707
__machine_check_early_realmode_p7(struct pt_regs * regs)708 long __machine_check_early_realmode_p7(struct pt_regs *regs)
709 {
710 /* P7 DD1 leaves top bits of DSISR undefined */
711 regs->dsisr &= 0x0000ffff;
712
713 return mce_handle_error(regs, regs->msr,
714 mce_p7_derror_table, mce_p7_ierror_table);
715 }
716
__machine_check_early_realmode_p8(struct pt_regs * regs)717 long __machine_check_early_realmode_p8(struct pt_regs *regs)
718 {
719 return mce_handle_error(regs, regs->msr,
720 mce_p8_derror_table, mce_p8_ierror_table);
721 }
722
__machine_check_early_realmode_p9(struct pt_regs * regs)723 long __machine_check_early_realmode_p9(struct pt_regs *regs)
724 {
725 unsigned long srr1 = regs->msr;
726
727 /*
728 * On POWER9 DD2.1 and below, it's possible to get a machine check
729 * caused by a paste instruction where only DSISR bit 25 is set. This
730 * will result in the MCE handler seeing an unknown event and the kernel
731 * crashing. An MCE that occurs like this is spurious, so we don't need
732 * to do anything in terms of servicing it. If there is something that
733 * needs to be serviced, the CPU will raise the MCE again with the
734 * correct DSISR so that it can be serviced properly. So detect this
735 * case and mark it as handled.
736 */
737 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
738 return 1;
739
740 /*
741 * Async machine check due to bad real address from store or foreign
742 * link time out comes with the load/store bit (PPC bit 42) set in
743 * SRR1, but the cause comes in SRR1 not DSISR. Clear bit 42 so we're
744 * directed to the ierror table so it will find the cause (which
745 * describes it correctly as a store error).
746 */
747 if (SRR1_MC_LOADSTORE(srr1) &&
748 ((srr1 & 0x081c0000) == 0x08140000 ||
749 (srr1 & 0x081c0000) == 0x08180000)) {
750 srr1 &= ~PPC_BIT(42);
751 }
752
753 return mce_handle_error(regs, srr1,
754 mce_p9_derror_table, mce_p9_ierror_table);
755 }
756
__machine_check_early_realmode_p10(struct pt_regs * regs)757 long __machine_check_early_realmode_p10(struct pt_regs *regs)
758 {
759 unsigned long srr1 = regs->msr;
760
761 /*
762 * Async machine check due to bad real address from store comes with
763 * the load/store bit (PPC bit 42) set in SRR1, but the cause comes in
764 * SRR1 not DSISR. Clear bit 42 so we're directed to the ierror table
765 * so it will find the cause (which describes it correctly as a store
766 * error).
767 */
768 if (SRR1_MC_LOADSTORE(srr1) &&
769 (srr1 & 0x081c0000) == 0x08140000) {
770 srr1 &= ~PPC_BIT(42);
771 }
772
773 return mce_handle_error(regs, srr1,
774 mce_p10_derror_table, mce_p10_ierror_table);
775 }
776