1 /*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Hwmod common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/types.h>
18
19 #include "omap_hwmod.h"
20 #include "cm33xx.h"
21 #include "prm33xx.h"
22 #include "omap_hwmod_33xx_43xx_common_data.h"
23 #include "prcm43xx.h"
24 #include "common.h"
25
26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
27 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
28 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
29
30 /*
31 * 'l3' class
32 * instance(s): l3_main, l3_s, l3_instr
33 */
34 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
35 .name = "l3",
36 };
37
38 struct omap_hwmod am33xx_l3_main_hwmod = {
39 .name = "l3_main",
40 .class = &am33xx_l3_hwmod_class,
41 .clkdm_name = "l3_clkdm",
42 .flags = HWMOD_INIT_NO_IDLE,
43 .main_clk = "l3_gclk",
44 .prcm = {
45 .omap4 = {
46 .modulemode = MODULEMODE_SWCTRL,
47 },
48 },
49 };
50
51 /* l3_s */
52 struct omap_hwmod am33xx_l3_s_hwmod = {
53 .name = "l3_s",
54 .class = &am33xx_l3_hwmod_class,
55 .clkdm_name = "l3s_clkdm",
56 };
57
58 /* l3_instr */
59 struct omap_hwmod am33xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &am33xx_l3_hwmod_class,
62 .clkdm_name = "l3_clkdm",
63 .flags = HWMOD_INIT_NO_IDLE,
64 .main_clk = "l3_gclk",
65 .prcm = {
66 .omap4 = {
67 .modulemode = MODULEMODE_SWCTRL,
68 },
69 },
70 };
71
72 /*
73 * 'l4' class
74 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
75 */
76 struct omap_hwmod_class am33xx_l4_hwmod_class = {
77 .name = "l4",
78 };
79
80 /* l4_ls */
81 struct omap_hwmod am33xx_l4_ls_hwmod = {
82 .name = "l4_ls",
83 .class = &am33xx_l4_hwmod_class,
84 .clkdm_name = "l4ls_clkdm",
85 .flags = HWMOD_INIT_NO_IDLE,
86 .main_clk = "l4ls_gclk",
87 .prcm = {
88 .omap4 = {
89 .modulemode = MODULEMODE_SWCTRL,
90 },
91 },
92 };
93
94 /* l4_wkup */
95 struct omap_hwmod am33xx_l4_wkup_hwmod = {
96 .name = "l4_wkup",
97 .class = &am33xx_l4_hwmod_class,
98 .clkdm_name = "l4_wkup_clkdm",
99 .flags = HWMOD_INIT_NO_IDLE,
100 .prcm = {
101 .omap4 = {
102 .modulemode = MODULEMODE_SWCTRL,
103 },
104 },
105 };
106
107 /*
108 * 'mpu' class
109 */
110 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
111 .name = "mpu",
112 };
113
114 struct omap_hwmod am33xx_mpu_hwmod = {
115 .name = "mpu",
116 .class = &am33xx_mpu_hwmod_class,
117 .clkdm_name = "mpu_clkdm",
118 .flags = HWMOD_INIT_NO_IDLE,
119 .main_clk = "dpll_mpu_m2_ck",
120 .prcm = {
121 .omap4 = {
122 .modulemode = MODULEMODE_SWCTRL,
123 },
124 },
125 };
126
127 /*
128 * 'wakeup m3' class
129 * Wakeup controller sub-system under wakeup domain
130 */
131 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
132 .name = "wkup_m3",
133 };
134
135 /*
136 * 'prcm' class
137 * power and reset manager (whole prcm infrastructure)
138 */
139 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
140 .name = "prcm",
141 };
142
143 /* prcm */
144 struct omap_hwmod am33xx_prcm_hwmod = {
145 .name = "prcm",
146 .class = &am33xx_prcm_hwmod_class,
147 .clkdm_name = "l4_wkup_clkdm",
148 };
149
150 /*
151 * 'emif' class
152 * instance(s): emif
153 */
154 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
155 .rev_offs = 0x0000,
156 };
157
158 struct omap_hwmod_class am33xx_emif_hwmod_class = {
159 .name = "emif",
160 .sysc = &am33xx_emif_sysc,
161 };
162
163
164
165 /* ocmcram */
166 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
167 .name = "ocmcram",
168 };
169
170 struct omap_hwmod am33xx_ocmcram_hwmod = {
171 .name = "ocmcram",
172 .class = &am33xx_ocmcram_hwmod_class,
173 .clkdm_name = "l3_clkdm",
174 .flags = HWMOD_INIT_NO_IDLE,
175 .main_clk = "l3_gclk",
176 .prcm = {
177 .omap4 = {
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181 };
182
183 /* 'smartreflex' class */
184 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
185 .name = "smartreflex",
186 };
187
188 /* smartreflex0 */
189 struct omap_hwmod am33xx_smartreflex0_hwmod = {
190 .name = "smartreflex0",
191 .class = &am33xx_smartreflex_hwmod_class,
192 .clkdm_name = "l4_wkup_clkdm",
193 .main_clk = "smartreflex0_fck",
194 .prcm = {
195 .omap4 = {
196 .modulemode = MODULEMODE_SWCTRL,
197 },
198 },
199 };
200
201 /* smartreflex1 */
202 struct omap_hwmod am33xx_smartreflex1_hwmod = {
203 .name = "smartreflex1",
204 .class = &am33xx_smartreflex_hwmod_class,
205 .clkdm_name = "l4_wkup_clkdm",
206 .main_clk = "smartreflex1_fck",
207 .prcm = {
208 .omap4 = {
209 .modulemode = MODULEMODE_SWCTRL,
210 },
211 },
212 };
213
214 /*
215 * 'control' module class
216 */
217 struct omap_hwmod_class am33xx_control_hwmod_class = {
218 .name = "control",
219 };
220
221
222 /* gpmc */
223 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
224 .rev_offs = 0x0,
225 .sysc_offs = 0x10,
226 .syss_offs = 0x14,
227 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
228 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
230 .sysc_fields = &omap_hwmod_sysc_type1,
231 };
232
233 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
234 .name = "gpmc",
235 .sysc = &gpmc_sysc,
236 };
237
238 struct omap_hwmod am33xx_gpmc_hwmod = {
239 .name = "gpmc",
240 .class = &am33xx_gpmc_hwmod_class,
241 .clkdm_name = "l3s_clkdm",
242 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
243 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
244 .main_clk = "l3s_gclk",
245 .prcm = {
246 .omap4 = {
247 .modulemode = MODULEMODE_SWCTRL,
248 },
249 },
250 };
251
omap_hwmod_am33xx_clkctrl(void)252 static void omap_hwmod_am33xx_clkctrl(void)
253 {
254 CLKCTRL(am33xx_smartreflex0_hwmod,
255 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
256 CLKCTRL(am33xx_smartreflex1_hwmod,
257 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
258 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
259 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
260 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
261 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
262 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
263 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
264 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
265 }
266
omap_hwmod_am33xx_reg(void)267 void omap_hwmod_am33xx_reg(void)
268 {
269 omap_hwmod_am33xx_clkctrl();
270 }
271
omap_hwmod_am43xx_clkctrl(void)272 static void omap_hwmod_am43xx_clkctrl(void)
273 {
274 CLKCTRL(am33xx_smartreflex0_hwmod,
275 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
276 CLKCTRL(am33xx_smartreflex1_hwmod,
277 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
278 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
279 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
280 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
281 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
282 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
283 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
284 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
285 }
286
omap_hwmod_am43xx_reg(void)287 void omap_hwmod_am43xx_reg(void)
288 {
289 omap_hwmod_am43xx_clkctrl();
290 }
291