1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/types.h>
10 #include <linux/cpu.h>
11 #include <asm/cpu.h>
12 #include <asm/cputype.h>
13 #include <asm/cpufeature.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/smp_plat.h>
16
17 static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities * entry,int scope)18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
19 {
20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
24 if (!is_midr_in_range(midr, &entry->midr_range))
25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
34 }
35
36 static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities * entry,int scope)37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
39 {
40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
42 }
43
44 static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities * entry,int scope)45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46 {
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
55 return model == entry->midr_range.model;
56 }
57
58 static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities * entry,int scope)59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
61 {
62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
65
66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
88 }
89
90 static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities * cap)91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
92 {
93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
94 bool enable_uct_trap = false;
95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
107 }
108
109 #ifdef CONFIG_ARM64_ERRATUM_1463225
110 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
111
112 static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities * entry,int scope)113 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
114 int scope)
115 {
116 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
117 }
118 #endif
119
120 static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities * __unused)121 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
122 {
123 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
124 }
125
126 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
127 .matches = is_affected_midr_range, \
128 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
129
130 #define CAP_MIDR_ALL_VERSIONS(model) \
131 .matches = is_affected_midr_range, \
132 .midr_range = MIDR_ALL_VERSIONS(model)
133
134 #define MIDR_FIXED(rev, revidr_mask) \
135 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
136
137 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
138 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
139 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
140
141 #define CAP_MIDR_RANGE_LIST(list) \
142 .matches = is_affected_midr_range_list, \
143 .midr_range_list = list
144
145 /* Errata affecting a range of revisions of given model variant */
146 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
147 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
148
149 /* Errata affecting a single variant/revision of a model */
150 #define ERRATA_MIDR_REV(model, var, rev) \
151 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
152
153 /* Errata affecting all variants/revisions of a given a model */
154 #define ERRATA_MIDR_ALL_VERSIONS(model) \
155 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
156 CAP_MIDR_ALL_VERSIONS(model)
157
158 /* Errata affecting a list of midr ranges, with same work around */
159 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
160 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
161 CAP_MIDR_RANGE_LIST(midr_list)
162
163 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
164 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
165 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
166 {},
167 };
168
169 static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities * entry,int scope)170 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
171 int scope)
172 {
173 int i;
174
175 if (!is_affected_midr_range_list(entry, scope) ||
176 !is_hyp_mode_available())
177 return false;
178
179 for_each_possible_cpu(i) {
180 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
181 return true;
182 }
183
184 return false;
185 }
186
187 static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities * entry,int scope)188 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
189 int scope)
190 {
191 u32 midr = read_cpuid_id();
192 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
193 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
194
195 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
196 return is_midr_in_range(midr, &range) && has_dic;
197 }
198
199 #ifdef CONFIG_RANDOMIZE_BASE
200
201 static const struct midr_range ca57_a72[] = {
202 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
203 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
204 {},
205 };
206
207 #endif
208
209 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
210 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
211 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
212 {
213 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
214 },
215 {
216 .midr_range.model = MIDR_QCOM_KRYO,
217 .matches = is_kryo_midr,
218 },
219 #endif
220 #ifdef CONFIG_ARM64_ERRATUM_1286807
221 {
222 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
223 },
224 {
225 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
226 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
227 },
228 #endif
229 {},
230 };
231 #endif
232
233 #ifdef CONFIG_CAVIUM_ERRATUM_27456
234 const struct midr_range cavium_erratum_27456_cpus[] = {
235 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
236 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
237 /* Cavium ThunderX, T81 pass 1.0 */
238 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
239 {},
240 };
241 #endif
242
243 #ifdef CONFIG_CAVIUM_ERRATUM_30115
244 static const struct midr_range cavium_erratum_30115_cpus[] = {
245 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
246 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
247 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
248 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
249 /* Cavium ThunderX, T83 pass 1.0 */
250 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
251 {},
252 };
253 #endif
254
255 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
256 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
257 {
258 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
259 },
260 {
261 .midr_range.model = MIDR_QCOM_KRYO,
262 .matches = is_kryo_midr,
263 },
264 {},
265 };
266 #endif
267
268 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
269 static const struct midr_range workaround_clean_cache[] = {
270 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
271 defined(CONFIG_ARM64_ERRATUM_827319) || \
272 defined(CONFIG_ARM64_ERRATUM_824069)
273 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
274 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
275 #endif
276 #ifdef CONFIG_ARM64_ERRATUM_819472
277 /* Cortex-A53 r0p[01] : ARM errata 819472 */
278 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
279 #endif
280 {},
281 };
282 #endif
283
284 #ifdef CONFIG_ARM64_ERRATUM_1418040
285 /*
286 * - 1188873 affects r0p0 to r2p0
287 * - 1418040 affects r0p0 to r3p1
288 */
289 static const struct midr_range erratum_1418040_list[] = {
290 /* Cortex-A76 r0p0 to r3p1 */
291 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
292 /* Neoverse-N1 r0p0 to r3p1 */
293 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
294 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
295 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
296 {},
297 };
298 #endif
299
300 #ifdef CONFIG_ARM64_ERRATUM_845719
301 static const struct midr_range erratum_845719_list[] = {
302 /* Cortex-A53 r0p[01234] */
303 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
304 /* Brahma-B53 r0p[0] */
305 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
306 /* Kryo2XX Silver rAp4 */
307 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
308 {},
309 };
310 #endif
311
312 #ifdef CONFIG_ARM64_ERRATUM_843419
313 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
314 {
315 /* Cortex-A53 r0p[01234] */
316 .matches = is_affected_midr_range,
317 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
318 MIDR_FIXED(0x4, BIT(8)),
319 },
320 {
321 /* Brahma-B53 r0p[0] */
322 .matches = is_affected_midr_range,
323 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
324 },
325 {},
326 };
327 #endif
328
329 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
330 static const struct midr_range erratum_speculative_at_list[] = {
331 #ifdef CONFIG_ARM64_ERRATUM_1165522
332 /* Cortex A76 r0p0 to r2p0 */
333 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
334 #endif
335 #ifdef CONFIG_ARM64_ERRATUM_1319367
336 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
337 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
338 #endif
339 #ifdef CONFIG_ARM64_ERRATUM_1530923
340 /* Cortex A55 r0p0 to r2p0 */
341 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
342 /* Kryo4xx Silver (rdpe => r1p0) */
343 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
344 #endif
345 {},
346 };
347 #endif
348
349 #ifdef CONFIG_ARM64_ERRATUM_1463225
350 static const struct midr_range erratum_1463225[] = {
351 /* Cortex-A76 r0p0 - r3p1 */
352 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
353 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
354 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
355 {},
356 };
357 #endif
358
359 #ifdef CONFIG_ARM64_ERRATUM_1742098
360 static struct midr_range broken_aarch32_aes[] = {
361 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
363 {},
364 };
365 #endif
366
367 const struct arm64_cpu_capabilities arm64_errata[] = {
368 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
369 {
370 .desc = "ARM errata 826319, 827319, 824069, or 819472",
371 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
372 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
373 .cpu_enable = cpu_enable_cache_maint_trap,
374 },
375 #endif
376 #ifdef CONFIG_ARM64_ERRATUM_832075
377 {
378 /* Cortex-A57 r0p0 - r1p2 */
379 .desc = "ARM erratum 832075",
380 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
381 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
382 0, 0,
383 1, 2),
384 },
385 #endif
386 #ifdef CONFIG_ARM64_ERRATUM_834220
387 {
388 /* Cortex-A57 r0p0 - r1p2 */
389 .desc = "ARM erratum 834220",
390 .capability = ARM64_WORKAROUND_834220,
391 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
392 0, 0,
393 1, 2),
394 },
395 #endif
396 #ifdef CONFIG_ARM64_ERRATUM_843419
397 {
398 .desc = "ARM erratum 843419",
399 .capability = ARM64_WORKAROUND_843419,
400 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
401 .matches = cpucap_multi_entry_cap_matches,
402 .match_list = erratum_843419_list,
403 },
404 #endif
405 #ifdef CONFIG_ARM64_ERRATUM_845719
406 {
407 .desc = "ARM erratum 845719",
408 .capability = ARM64_WORKAROUND_845719,
409 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
410 },
411 #endif
412 #ifdef CONFIG_CAVIUM_ERRATUM_23154
413 {
414 /* Cavium ThunderX, pass 1.x */
415 .desc = "Cavium erratum 23154",
416 .capability = ARM64_WORKAROUND_CAVIUM_23154,
417 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
418 },
419 #endif
420 #ifdef CONFIG_CAVIUM_ERRATUM_27456
421 {
422 .desc = "Cavium erratum 27456",
423 .capability = ARM64_WORKAROUND_CAVIUM_27456,
424 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
425 },
426 #endif
427 #ifdef CONFIG_CAVIUM_ERRATUM_30115
428 {
429 .desc = "Cavium erratum 30115",
430 .capability = ARM64_WORKAROUND_CAVIUM_30115,
431 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
432 },
433 #endif
434 {
435 .desc = "Mismatched cache type (CTR_EL0)",
436 .capability = ARM64_MISMATCHED_CACHE_TYPE,
437 .matches = has_mismatched_cache_type,
438 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
439 .cpu_enable = cpu_enable_trap_ctr_access,
440 },
441 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
442 {
443 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
444 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
445 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
446 .matches = cpucap_multi_entry_cap_matches,
447 .match_list = qcom_erratum_1003_list,
448 },
449 #endif
450 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
451 {
452 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
453 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
454 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
455 .matches = cpucap_multi_entry_cap_matches,
456 .match_list = arm64_repeat_tlbi_list,
457 },
458 #endif
459 #ifdef CONFIG_ARM64_ERRATUM_858921
460 {
461 /* Cortex-A73 all versions */
462 .desc = "ARM erratum 858921",
463 .capability = ARM64_WORKAROUND_858921,
464 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
465 },
466 #endif
467 {
468 .desc = "Spectre-v2",
469 .capability = ARM64_SPECTRE_V2,
470 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
471 .matches = has_spectre_v2,
472 .cpu_enable = spectre_v2_enable_mitigation,
473 },
474 #ifdef CONFIG_RANDOMIZE_BASE
475 {
476 .desc = "EL2 vector hardening",
477 .capability = ARM64_HARDEN_EL2_VECTORS,
478 ERRATA_MIDR_RANGE_LIST(ca57_a72),
479 },
480 #endif
481 {
482 .desc = "Spectre-v4",
483 .capability = ARM64_SPECTRE_V4,
484 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
485 .matches = has_spectre_v4,
486 .cpu_enable = spectre_v4_enable_mitigation,
487 },
488 {
489 .desc = "Spectre-BHB",
490 .capability = ARM64_SPECTRE_BHB,
491 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
492 .matches = is_spectre_bhb_affected,
493 .cpu_enable = spectre_bhb_enable_mitigation,
494 },
495 #ifdef CONFIG_ARM64_ERRATUM_1418040
496 {
497 .desc = "ARM erratum 1418040",
498 .capability = ARM64_WORKAROUND_1418040,
499 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
500 /*
501 * We need to allow affected CPUs to come in late, but
502 * also need the non-affected CPUs to be able to come
503 * in at any point in time. Wonderful.
504 */
505 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
506 },
507 #endif
508 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
509 {
510 .desc = "ARM errata 1165522, 1319367, or 1530923",
511 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
512 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
513 },
514 #endif
515 #ifdef CONFIG_ARM64_ERRATUM_1463225
516 {
517 .desc = "ARM erratum 1463225",
518 .capability = ARM64_WORKAROUND_1463225,
519 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
520 .matches = has_cortex_a76_erratum_1463225,
521 .midr_range_list = erratum_1463225,
522 },
523 #endif
524 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
525 {
526 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
527 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
528 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
529 .matches = needs_tx2_tvm_workaround,
530 },
531 {
532 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
533 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
534 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
535 },
536 #endif
537 #ifdef CONFIG_ARM64_ERRATUM_1542419
538 {
539 /* we depend on the firmware portion for correctness */
540 .desc = "ARM erratum 1542419 (kernel portion)",
541 .capability = ARM64_WORKAROUND_1542419,
542 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
543 .matches = has_neoverse_n1_erratum_1542419,
544 .cpu_enable = cpu_enable_trap_ctr_access,
545 },
546 #endif
547 #ifdef CONFIG_ARM64_ERRATUM_1508412
548 {
549 /* we depend on the firmware portion for correctness */
550 .desc = "ARM erratum 1508412 (kernel portion)",
551 .capability = ARM64_WORKAROUND_1508412,
552 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
553 0, 0,
554 1, 0),
555 },
556 #endif
557 #ifdef CONFIG_ARM64_ERRATUM_2457168
558 {
559 .desc = "ARM erratum 2457168",
560 .capability = ARM64_WORKAROUND_2457168,
561 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
562 /* Cortex-A510 r0p0-r1p1 */
563 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
564 },
565 #endif
566 #ifdef CONFIG_ARM64_ERRATUM_1742098
567 {
568 .desc = "ARM erratum 1742098",
569 .capability = ARM64_WORKAROUND_1742098,
570 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
571 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
572 },
573 #endif
574 {
575 }
576 };
577