1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Marvell Technology Group Ltd. 4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 5 */ 6 7#include <dt-bindings/clock/marvell,mmp2.h> 8#include <dt-bindings/power/marvell,mmp2.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 aliases { 15 serial0 = &uart1; 16 serial1 = &uart2; 17 serial2 = &uart3; 18 serial3 = &uart4; 19 i2c0 = &twsi1; 20 i2c1 = &twsi2; 21 }; 22 23 soc { 24 #address-cells = <1>; 25 #size-cells = <1>; 26 compatible = "simple-bus"; 27 interrupt-parent = <&intc>; 28 ranges; 29 30 L2: l2-cache { 31 compatible = "marvell,tauros2-cache"; 32 marvell,tauros2-cache-features = <0x3>; 33 }; 34 35 axi@d4200000 { /* AXI */ 36 compatible = "mrvl,axi-bus", "simple-bus"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 reg = <0xd4200000 0x00200000>; 40 ranges; 41 42 gpu: gpu@d420d000 { 43 compatible = "vivante,gc"; 44 reg = <0xd420d000 0x4000>; 45 interrupts = <8>; 46 status = "disabled"; 47 clocks = <&soc_clocks MMP2_CLK_GPU_3D>, 48 <&soc_clocks MMP2_CLK_GPU_BUS>; 49 clock-names = "core", "bus"; 50 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; 51 }; 52 53 intc: interrupt-controller@d4282000 { 54 compatible = "mrvl,mmp2-intc"; 55 interrupt-controller; 56 #interrupt-cells = <1>; 57 reg = <0xd4282000 0x1000>; 58 mrvl,intc-nr-irqs = <64>; 59 }; 60 61 intcmux4: interrupt-controller@d4282150 { 62 compatible = "mrvl,mmp2-mux-intc"; 63 interrupts = <4>; 64 interrupt-controller; 65 #interrupt-cells = <1>; 66 reg = <0x150 0x4>, <0x168 0x4>; 67 reg-names = "mux status", "mux mask"; 68 mrvl,intc-nr-irqs = <2>; 69 }; 70 71 intcmux5: interrupt-controller@d4282154 { 72 compatible = "mrvl,mmp2-mux-intc"; 73 interrupts = <5>; 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 reg = <0x154 0x4>, <0x16c 0x4>; 77 reg-names = "mux status", "mux mask"; 78 mrvl,intc-nr-irqs = <2>; 79 mrvl,clr-mfp-irq = <1>; 80 }; 81 82 intcmux9: interrupt-controller@d4282180 { 83 compatible = "mrvl,mmp2-mux-intc"; 84 interrupts = <9>; 85 interrupt-controller; 86 #interrupt-cells = <1>; 87 reg = <0x180 0x4>, <0x17c 0x4>; 88 reg-names = "mux status", "mux mask"; 89 mrvl,intc-nr-irqs = <3>; 90 }; 91 92 intcmux17: interrupt-controller@d4282158 { 93 compatible = "mrvl,mmp2-mux-intc"; 94 interrupts = <17>; 95 interrupt-controller; 96 #interrupt-cells = <1>; 97 reg = <0x158 0x4>, <0x170 0x4>; 98 reg-names = "mux status", "mux mask"; 99 mrvl,intc-nr-irqs = <5>; 100 }; 101 102 intcmux35: interrupt-controller@d428215c { 103 compatible = "mrvl,mmp2-mux-intc"; 104 interrupts = <35>; 105 interrupt-controller; 106 #interrupt-cells = <1>; 107 reg = <0x15c 0x4>, <0x174 0x4>; 108 reg-names = "mux status", "mux mask"; 109 mrvl,intc-nr-irqs = <15>; 110 }; 111 112 intcmux51: interrupt-controller@d4282160 { 113 compatible = "mrvl,mmp2-mux-intc"; 114 interrupts = <51>; 115 interrupt-controller; 116 #interrupt-cells = <1>; 117 reg = <0x160 0x4>, <0x178 0x4>; 118 reg-names = "mux status", "mux mask"; 119 mrvl,intc-nr-irqs = <2>; 120 }; 121 122 intcmux55: interrupt-controller@d4282188 { 123 compatible = "mrvl,mmp2-mux-intc"; 124 interrupts = <55>; 125 interrupt-controller; 126 #interrupt-cells = <1>; 127 reg = <0x188 0x4>, <0x184 0x4>; 128 reg-names = "mux status", "mux mask"; 129 mrvl,intc-nr-irqs = <2>; 130 }; 131 132 usb_phy0: usb-phy@d4207000 { 133 compatible = "marvell,mmp2-usb-phy"; 134 reg = <0xd4207000 0x40>; 135 #phy-cells = <0>; 136 status = "disabled"; 137 }; 138 139 usb_otg0: usb-otg@d4208000 { 140 compatible = "marvell,pxau2o-ehci"; 141 reg = <0xd4208000 0x200>; 142 interrupts = <44>; 143 clocks = <&soc_clocks MMP2_CLK_USB>; 144 clock-names = "USBCLK"; 145 phys = <&usb_phy0>; 146 phy-names = "usb"; 147 status = "disabled"; 148 }; 149 150 mmc1: mmc@d4280000 { 151 compatible = "mrvl,pxav3-mmc"; 152 reg = <0xd4280000 0x120>; 153 clocks = <&soc_clocks MMP2_CLK_SDH0>; 154 clock-names = "io"; 155 interrupts = <39>; 156 status = "disabled"; 157 }; 158 159 mmc2: mmc@d4280800 { 160 compatible = "mrvl,pxav3-mmc"; 161 reg = <0xd4280800 0x120>; 162 clocks = <&soc_clocks MMP2_CLK_SDH1>; 163 clock-names = "io"; 164 interrupts = <52>; 165 status = "disabled"; 166 }; 167 168 mmc3: mmc@d4281000 { 169 compatible = "mrvl,pxav3-mmc"; 170 reg = <0xd4281000 0x120>; 171 clocks = <&soc_clocks MMP2_CLK_SDH2>; 172 clock-names = "io"; 173 interrupts = <53>; 174 status = "disabled"; 175 }; 176 177 mmc4: mmc@d4281800 { 178 compatible = "mrvl,pxav3-mmc"; 179 reg = <0xd4281800 0x120>; 180 clocks = <&soc_clocks MMP2_CLK_SDH3>; 181 clock-names = "io"; 182 interrupts = <54>; 183 status = "disabled"; 184 }; 185 186 camera0: camera@d420a000 { 187 compatible = "marvell,mmp2-ccic"; 188 reg = <0xd420a000 0x800>; 189 interrupts = <42>; 190 clocks = <&soc_clocks MMP2_CLK_CCIC0>; 191 clock-names = "axi"; 192 #clock-cells = <0>; 193 clock-output-names = "mclk"; 194 status = "disabled"; 195 }; 196 197 camera1: camera@d420a800 { 198 compatible = "marvell,mmp2-ccic"; 199 reg = <0xd420a800 0x800>; 200 interrupts = <30>; 201 clocks = <&soc_clocks MMP2_CLK_CCIC1>; 202 clock-names = "axi"; 203 #clock-cells = <0>; 204 clock-output-names = "mclk"; 205 status = "disabled"; 206 }; 207 208 adma0: dma-controller@d42a0800 { 209 compatible = "marvell,adma-1.0"; 210 reg = <0xd42a0800 0x100>; 211 interrupts = <48>; 212 #dma-cells = <1>; 213 asram = <&asram>; 214 iram = <&asram>; 215 status = "disabled"; 216 }; 217 218 adma1: dma-controller@d42a0900 { 219 compatible = "marvell,adma-1.0"; 220 reg = <0xd42a0900 0x100>; 221 interrupts = <48>; 222 #dma-cells = <1>; 223 status = "disabled"; 224 }; 225 226 audio_clk: clocks@d42a0c30 { 227 compatible = "marvell,mmp2-audio-clock"; 228 reg = <0xd42a0c30 0x10>; 229 clock-names = "audio", "vctcxo", "i2s0", "i2s1"; 230 clocks = <&soc_clocks MMP2_CLK_AUDIO>, 231 <&soc_clocks MMP2_CLK_VCTCXO>, 232 <&soc_clocks MMP2_CLK_I2S0>, 233 <&soc_clocks MMP2_CLK_I2S1>; 234 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; 235 #clock-cells = <1>; 236 status = "disabled"; 237 }; 238 239 sspa0: audio-controller@d42a0c00 { 240 compatible = "marvell,mmp-sspa"; 241 reg = <0xd42a0c00 0x30>, 242 <0xd42a0c80 0x30>; 243 interrupts = <2>; 244 clock-names = "audio", "bitclk"; 245 clocks = <&soc_clocks MMP2_CLK_AUDIO>, 246 <&audio_clk 1>; 247 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; 248 #sound-dai-cells = <0>; 249 status = "disabled"; 250 }; 251 252 sspa1: audio-controller@d42a0d00 { 253 compatible = "marvell,mmp-sspa"; 254 reg = <0xd42a0d00 0x30>, 255 <0xd42a0d80 0x30>; 256 interrupts = <3>; 257 clock-names = "audio", "bitclk"; 258 clocks = <&soc_clocks MMP2_CLK_AUDIO>, 259 <&audio_clk 2>; 260 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; 261 #sound-dai-cells = <0>; 262 status = "disabled"; 263 }; 264 }; 265 266 apb@d4000000 { /* APB */ 267 compatible = "mrvl,apb-bus", "simple-bus"; 268 #address-cells = <1>; 269 #size-cells = <1>; 270 reg = <0xd4000000 0x00200000>; 271 ranges; 272 273 dma-controller@d4000000 { 274 compatible = "marvell,pdma-1.0"; 275 reg = <0xd4000000 0x10000>; 276 interrupts = <48>; 277 #dma-channels = <16>; 278 status = "disabled"; 279 }; 280 281 timer0: timer@d4014000 { 282 compatible = "mrvl,mmp-timer"; 283 reg = <0xd4014000 0x100>; 284 interrupts = <13>; 285 clocks = <&soc_clocks MMP2_CLK_TIMER>; 286 }; 287 288 uart1: serial@d4030000 { 289 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 290 reg = <0xd4030000 0x1000>; 291 interrupts = <27>; 292 clocks = <&soc_clocks MMP2_CLK_UART0>; 293 resets = <&soc_clocks MMP2_CLK_UART0>; 294 reg-shift = <2>; 295 status = "disabled"; 296 }; 297 298 uart2: serial@d4017000 { 299 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 300 reg = <0xd4017000 0x1000>; 301 interrupts = <28>; 302 clocks = <&soc_clocks MMP2_CLK_UART1>; 303 resets = <&soc_clocks MMP2_CLK_UART1>; 304 reg-shift = <2>; 305 status = "disabled"; 306 }; 307 308 uart3: serial@d4018000 { 309 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 310 reg = <0xd4018000 0x1000>; 311 interrupts = <24>; 312 clocks = <&soc_clocks MMP2_CLK_UART2>; 313 resets = <&soc_clocks MMP2_CLK_UART2>; 314 reg-shift = <2>; 315 status = "disabled"; 316 }; 317 318 uart4: serial@d4016000 { 319 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 320 reg = <0xd4016000 0x1000>; 321 interrupts = <46>; 322 clocks = <&soc_clocks MMP2_CLK_UART3>; 323 resets = <&soc_clocks MMP2_CLK_UART3>; 324 reg-shift = <2>; 325 status = "disabled"; 326 }; 327 328 gpio: gpio@d4019000 { 329 compatible = "marvell,mmp2-gpio"; 330 #address-cells = <1>; 331 #size-cells = <1>; 332 reg = <0xd4019000 0x1000>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupts = <49>; 336 interrupt-names = "gpio_mux"; 337 clocks = <&soc_clocks MMP2_CLK_GPIO>; 338 resets = <&soc_clocks MMP2_CLK_GPIO>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 ranges; 342 343 gcb0: gpio@d4019000 { 344 reg = <0xd4019000 0x4>; 345 }; 346 347 gcb1: gpio@d4019004 { 348 reg = <0xd4019004 0x4>; 349 }; 350 351 gcb2: gpio@d4019008 { 352 reg = <0xd4019008 0x4>; 353 }; 354 355 gcb3: gpio@d4019100 { 356 reg = <0xd4019100 0x4>; 357 }; 358 359 gcb4: gpio@d4019104 { 360 reg = <0xd4019104 0x4>; 361 }; 362 363 gcb5: gpio@d4019108 { 364 reg = <0xd4019108 0x4>; 365 }; 366 }; 367 368 twsi1: i2c@d4011000 { 369 compatible = "mrvl,mmp-twsi"; 370 reg = <0xd4011000 0x1000>; 371 interrupts = <7>; 372 clocks = <&soc_clocks MMP2_CLK_TWSI0>; 373 resets = <&soc_clocks MMP2_CLK_TWSI0>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 mrvl,i2c-fast-mode; 377 status = "disabled"; 378 }; 379 380 twsi2: i2c@d4031000 { 381 compatible = "mrvl,mmp-twsi"; 382 reg = <0xd4031000 0x1000>; 383 interrupt-parent = <&intcmux17>; 384 interrupts = <0>; 385 clocks = <&soc_clocks MMP2_CLK_TWSI1>; 386 resets = <&soc_clocks MMP2_CLK_TWSI1>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 twsi3: i2c@d4032000 { 393 compatible = "mrvl,mmp-twsi"; 394 reg = <0xd4032000 0x1000>; 395 interrupt-parent = <&intcmux17>; 396 interrupts = <1>; 397 clocks = <&soc_clocks MMP2_CLK_TWSI2>; 398 resets = <&soc_clocks MMP2_CLK_TWSI2>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 twsi4: i2c@d4033000 { 405 compatible = "mrvl,mmp-twsi"; 406 reg = <0xd4033000 0x1000>; 407 interrupt-parent = <&intcmux17>; 408 interrupts = <2>; 409 clocks = <&soc_clocks MMP2_CLK_TWSI3>; 410 resets = <&soc_clocks MMP2_CLK_TWSI3>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 status = "disabled"; 414 }; 415 416 417 twsi5: i2c@d4033800 { 418 compatible = "mrvl,mmp-twsi"; 419 reg = <0xd4033800 0x1000>; 420 interrupt-parent = <&intcmux17>; 421 interrupts = <3>; 422 clocks = <&soc_clocks MMP2_CLK_TWSI4>; 423 resets = <&soc_clocks MMP2_CLK_TWSI4>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 twsi6: i2c@d4034000 { 430 compatible = "mrvl,mmp-twsi"; 431 reg = <0xd4034000 0x1000>; 432 interrupt-parent = <&intcmux17>; 433 interrupts = <4>; 434 clocks = <&soc_clocks MMP2_CLK_TWSI5>; 435 resets = <&soc_clocks MMP2_CLK_TWSI5>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 rtc: rtc@d4010000 { 442 compatible = "mrvl,mmp-rtc"; 443 reg = <0xd4010000 0x1000>; 444 interrupts = <1>, <0>; 445 interrupt-names = "rtc 1Hz", "rtc alarm"; 446 interrupt-parent = <&intcmux5>; 447 clocks = <&soc_clocks MMP2_CLK_RTC>; 448 resets = <&soc_clocks MMP2_CLK_RTC>; 449 status = "disabled"; 450 }; 451 452 ssp1: spi@d4035000 { 453 compatible = "marvell,mmp2-ssp"; 454 reg = <0xd4035000 0x1000>; 455 clocks = <&soc_clocks MMP2_CLK_SSP0>; 456 interrupts = <0>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 ssp2: spi@d4036000 { 463 compatible = "marvell,mmp2-ssp"; 464 reg = <0xd4036000 0x1000>; 465 clocks = <&soc_clocks MMP2_CLK_SSP1>; 466 interrupts = <1>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 ssp3: spi@d4037000 { 473 compatible = "marvell,mmp2-ssp"; 474 reg = <0xd4037000 0x1000>; 475 clocks = <&soc_clocks MMP2_CLK_SSP2>; 476 interrupts = <20>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 ssp4: spi@d4039000 { 483 compatible = "marvell,mmp2-ssp"; 484 reg = <0xd4039000 0x1000>; 485 clocks = <&soc_clocks MMP2_CLK_SSP3>; 486 interrupts = <21>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 }; 492 493 asram: sram@e0000000 { 494 compatible = "mmio-sram"; 495 reg = <0xe0000000 0x10000>; 496 ranges = <0 0xe0000000 0x10000>; 497 #address-cells = <1>; 498 #size-cells = <1>; 499 status = "disabled"; 500 }; 501 502 soc_clocks: clocks { 503 compatible = "marvell,mmp2-clock"; 504 reg = <0xd4050000 0x2000>, 505 <0xd4282800 0x400>, 506 <0xd4015000 0x1000>; 507 reg-names = "mpmu", "apmu", "apbc"; 508 #clock-cells = <1>; 509 #reset-cells = <1>; 510 #power-domain-cells = <1>; 511 }; 512 }; 513}; 514