1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef HDMI_EDID_H 10 #define HDMI_EDID_H 11 12 #include "hdf_base.h" 13 #include "hdmi_ddc.h" 14 #include "hdmi_if.h" 15 16 #ifdef __cplusplus 17 #if __cplusplus 18 extern "C" { 19 #endif 20 #endif /* __cplusplus */ 21 22 #define VIDEO_LENGTH_4 4 23 #define VIDEO_LENGTH_5 5 24 #define VIDEO_LENGTH_16 16 25 #define VIDEO_WIDTH_3 3 26 #define VIDEO_WIDTH_4 4 27 #define VIDEO_WIDTH_9 9 28 #define VIDEO_WIDTH_10 10 29 30 #define UINT8_ARRAY_TELEMENT_0 0 31 #define UINT8_ARRAY_TELEMENT_1 1 32 #define UINT8_ARRAY_TELEMENT_2 2 33 #define UINT8_ARRAY_TELEMENT_3 3 34 #define UINT8_ARRAY_TELEMENT_4 4 35 #define UINT8_ARRAY_TELEMENT_5 5 36 #define UINT8_ARRAY_TELEMENT_6 6 37 #define UINT8_ARRAY_TELEMENT_7 7 38 #define UINT8_ARRAY_TELEMENT_8 8 39 #define UINT8_ARRAY_TELEMENT_9 9 40 #define UINT8_ARRAY_TELEMENT_10 10 41 #define UINT8_ARRAY_TELEMENT_11 11 42 #define UINT8_ARRAY_TELEMENT_12 12 43 #define UINT8_ARRAY_TELEMENT_13 13 44 #define UINT8_ARRAY_TELEMENT_14 14 45 #define UINT8_ARRAY_TELEMENT_15 15 46 #define UINT8_ARRAY_TELEMENT_16 16 47 #define UINT8_ARRAY_TELEMENT_17 17 48 #define UINT8_ARRAY_TELEMENT_18 18 49 #define UINT8_ARRAY_TELEMENT_19 19 50 #define UINT8_ARRAY_TELEMENT_20 20 51 52 /* (EDID)Extended Display Identification Data */ 53 #define HDMI_EDID_SINGLE_BLOCK_SIZE 128 54 #define HDMI_EDID_MAX_BLOCK_NUM 4 55 #define HDMI_EDID_TOTAL_SIZE (HDMI_EDID_SINGLE_BLOCK_SIZE * HDMI_EDID_MAX_BLOCK_NUM) 56 #define HDMI_EDID_MAX_VIC_COUNT 128 57 #define HDMI_EDID_CHECK_SUM_MARK 0xff 58 59 /* edid header */ 60 #define HDMI_EDID_BLOCK_HEADER_FIELD_LEN 8 61 62 /* edid vendor/product info */ 63 #define HDMI_EDID_MANUFACRURER_NAME_FIELD_LEN 2 64 #define HDMI_EDID_MANUFACRURER_NAME_MAX_LEN 4 65 #define HDMI_EDID_MANUFACRURER_NAME_EFFECTIVE_LEN 3 66 #define HDMI_EDID_MANUFACRURER_NAME_CHAR_MARK 0x1F /* 5 bits */ 67 #define HDMI_EDID_MANUFACRURER_NAME_CHAR_SHIFT 5 68 #define HDMI_EDID_MANUFACRURER_NAME_LOW_INVALID 0 69 #define HDMI_EDID_MANUFACRURER_NAME_HIGH_INVALID 27 70 #define HDMI_EDID_MANUFACRURER_NAME_SHIFT 8 71 #define HDMI_EDID_PRODUCT_CODE_FIELD_LEN 2 72 #define HDMI_EDID_PRODUCT_CODE_SHIFT 8 73 #define HDMI_EDID_SERIAL_NUMBER_FIELD_LEN 4 74 #define HDMI_EDID_SERIAL_NUMBER_SHIFT 8 75 #define HDMI_EDID_YEAR_BASE 1990 76 77 struct HdmiEdidVendorInfo { 78 char mfrName[HDMI_EDID_MANUFACRURER_NAME_MAX_LEN]; 79 uint16_t productCode; 80 uint32_t serialNumber; 81 uint8_t week; 82 uint8_t year; 83 }; 84 85 #define HDMI_EDID_VERSION_NUM 1 86 #define HDMI_EDID_REVISION_NUM 3 87 88 /* edid version info */ 89 struct HdmiEdidVersionInfo { 90 uint8_t version; 91 uint8_t revision; 92 }; 93 94 /* edid basic display parameters and features */ 95 struct HdmiEdidBasicDispParamInfo { 96 uint8_t width; /* unit: cm */ 97 uint8_t height; /* unit: cm */ 98 }; 99 100 /* edid color characteristics */ 101 #define HDMI_EDID_COLOR_LOW_BITS_MARK 0x03 102 #define HDMI_EDID_COLOR_RED_X_LOW_OFFSET 6 103 #define HDMI_EDID_COLOR_RED_Y_LOW_OFFSET 4 104 #define HDMI_EDID_COLOR_GREEN_X_LOW_OFFSET 2 105 #define HDMI_EDID_COLOR_BLUE_X_LOW_OFFSET 6 106 #define HDMI_EDID_COLOR_BLUE_Y_LOW_OFFSET 4 107 #define HDMI_EDID_COLOR_WHITE_X_LOW_OFFSET 2 108 #define HDMI_EDID_COLOR_HIGH_OFFSET 2 109 110 struct HdmiEdidColorInfo { 111 uint16_t redX; 112 uint16_t redY; 113 uint16_t greenX; 114 uint16_t greenY; 115 uint16_t blueX; 116 uint16_t blueY; 117 uint16_t whiteX; 118 uint16_t whiteY; 119 }; 120 121 /* edid established timings */ 122 #define HDMI_EDID_ESTABLISHED_TIMINGS_FIELD_LEN 3 123 124 enum HdmiEdidEstablishTiming { 125 HDMI_EDID_ESTABLISHED_TIMING_VESA_800X600_60 = 0, 126 HDMI_EDID_ESTABLISHED_TIMING_VESA_800X600_56 = 1, 127 HDMI_EDID_ESTABLISHED_TIMING_VESA_640X480_75 = 2, 128 HDMI_EDID_ESTABLISHED_TIMING_VESA_640X480_72 = 3, 129 HDMI_EDID_ESTABLISHED_TIMING_640X480_67 = 4, 130 HDMI_EDID_ESTABLISHED_TIMING_VGA_640X480_60 = 5, 131 HDMI_EDID_ESTABLISHED_TIMING_XGA_720X400_88 = 6, 132 HDMI_EDID_ESTABLISHED_TIMING_VGA_720X400_70 = 7, 133 HDMI_EDID_ESTABLISHED_TIMING_VESA_1280X1024_75 = 8, 134 HDMI_EDID_ESTABLISHED_TIMING_VESA_1024X768_75 = 9, 135 HDMI_EDID_ESTABLISHED_TIMING_VESA_1024X768_70 = 10, 136 HDMI_EDID_ESTABLISHED_TIMING_VESA_1024X768_60 = 11, 137 HDMI_EDID_ESTABLISHED_TIMING_1024X768_87 = 12, 138 HDMI_EDID_ESTABLISHED_TIMING_832X624_75 = 13, 139 HDMI_EDID_ESTABLISHED_TIMING_VESA_800X600_75 = 14, 140 HDMI_EDID_ESTABLISHED_TIMING_VESA_800X600_72 = 15, 141 HDMI_EDID_ESTABLISHED_TIMING_VESA_1152X870_75 = 16, 142 HDMI_EDID_ESTABLISHED_TIMING_BUTT, 143 }; 144 145 struct HdmiEdidEstablishedTimingsInfo { 146 uint32_t estTimingsNum; 147 uint32_t estTimings[HDMI_EDID_ESTABLISHED_TIMING_BUTT]; 148 }; 149 150 /* edid standard timing */ 151 #define HDMI_EDID_STANDARD_TIMING_FIELD_LEN 16 152 #define HDMI_EDID_STANDARD_TIMING_COUNT 8 153 #define HDMI_EDID_PER_STANDARD_TIMING_BYTE_NUM 2 154 #define HDMI_EDID_STANDARD_TIMING_UNUSED_FLAG 0x01 155 #define HDMI_EDID_STANDARD_TIMING_HORIZ_PIXEL_BASE 31 156 #define HDMI_EDID_STANDARD_TIMING_HORIZ_PIXEL_FACTOR 8 157 #define HDMI_EDID_STANDARD_TIMING_REFRESH_RATE_BASE 60 158 #define HDMI_EDID_STANDARD_TIMING_REFRESH_RATE_MARK 0x3F 159 160 #define HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_MARK 0xC0 161 #define HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_SHIFT 6 162 163 enum HdmiEdidStdTimingAspectRate { 164 HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_16_10 = 0, 165 HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_5_4 = 1, 166 HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_4_3 = 2, 167 HDMI_EDID_STANDARD_TIMING_ASPECT_RATE_16_9 = 3, 168 }; 169 170 struct HdmiEdidStdTimingInfo { 171 uint32_t horizPixel; 172 uint32_t vertPixel; 173 uint32_t refreshRate; 174 }; 175 176 /* edid detailed timing descriptor */ 177 #define HDMI_EDID_DETAILED_TIMING_DESCRIPTOR_FIELD_LEN 18 178 #define HDMI_EDID_DETAILED_TIMING_PIXEL_CLK_FIELD_LEN 2 179 #define HDMI_EDID_DETAILED_TIMING_PIXEL_CLK_KHZ_FACTOR 10 180 #define HDMI_EDID_DETAILED_TIMING_UPPER_4BITS_MARK 0xF0 181 #define HDMI_EDID_DETAILED_TIMING_LOWER_4BITS_MARK 0x0F 182 #define HDMI_EDID_DETAILED_TIMING_HS_OFFSET_MARK 0xC0 183 #define HDMI_EDID_DETAILED_TIMING_HS_PULSE_WIDTH_MARK 0x30 184 #define HDMI_EDID_DETAILED_TIMING_VS_OFFSET_MARK 0x0C 185 #define HDMI_EDID_DETAILED_TIMING_VS_PULSE_WIDTH_MARK 0x03 186 #define HDMI_EDID_DETAILED_TIMING_STEREO_MARK 0x60 187 #define HDMI_EDID_DETAILED_TIMING_STEREO_SEQUENTIAL_R 0x02 188 #define HDMI_EDID_DETAILED_TIMING_STEREO_SEQUENTIAL_L 0x04 189 #define HDMI_EDID_DETAILED_TIMING_STEREO_INTERLEAVED_2R 0x03 190 #define HDMI_EDID_DETAILED_TIMING_STEREO_INTERLEAVED_2L 0x05 191 #define HDMI_EDID_DETAILED_TIMING_STEREO_INTERLEAVED_4 0x06 192 #define HDMI_EDID_DETAILED_TIMING_STEREO_INTERLEAVED_SBS 0x07 193 #define HDMI_EDID_DETAILED_TIMING_SYNC_SIGNAL_TYPE_MARK 0x0E 194 #define HDMI_EDID_DETAILED_TIMING_SYNC_DCS_WS_0 0x00 195 #define HDMI_EDID_DETAILED_TIMING_SYNC_DCS_WS_1 0x01 196 #define HDMI_EDID_DETAILED_TIMING_SYNC_DCS_DS_2 0x02 197 #define HDMI_EDID_DETAILED_TIMING_SYNC_DCS_DS_3 0x03 198 #define HDMI_EDID_DETAILED_TIMING_SYNC_DSS_VN_HN_4 0x04 199 #define HDMI_EDID_DETAILED_TIMING_SYNC_DSS_VN_HP_5 0x05 200 #define HDMI_EDID_DETAILED_TIMING_SYNC_DSS_VP_HN_6 0x06 201 #define HDMI_EDID_DETAILED_TIMING_SYNC_DSS_VP_HP_7 0x07 202 #define HDMI_EDID_MAX_DETAILED_TIMING_COUNT 10 203 204 struct HdmiEdidDetailedTimingBlockInfo { 205 uint8_t pixelClk[HDMI_EDID_DETAILED_TIMING_PIXEL_CLK_FIELD_LEN]; 206 uint8_t hActive; 207 uint8_t hBlanking; 208 uint8_t hActiveBlanking; 209 uint8_t vActive; 210 uint8_t vBlanking; 211 uint8_t vActiveBlanking; 212 uint8_t hSyncOffset; 213 uint8_t hSyncPulseWidth; 214 uint8_t vsOffesetPulseWidth; 215 uint8_t hsOffsetVsOffset; 216 uint8_t hImageSize; 217 uint8_t vImageSize; 218 uint8_t hvImageSize; 219 uint8_t hBorder; 220 uint8_t vBorder; 221 uint8_t flags; 222 }; 223 224 struct HdmiEdidPreferredTimingInfo { 225 uint32_t pixelClk; /* unit: KHz */ 226 uint32_t hActive; /* horizontal active area */ 227 uint32_t hBackBlank; /* horizontal back blank */ 228 uint32_t hFrontBlank; /* horizontal front blank */ 229 uint32_t hSyncPluseWidth; /* horizontal sync pluse width */ 230 uint32_t vActive; /* vertical active area */ 231 uint32_t vBackBlank; /* vertical back blank */ 232 uint32_t vFrontBlank; /* vertical front blank */ 233 uint32_t vSyncPluseWidth; /* vertical sync pluse width */ 234 uint32_t imageWidth; /* image width */ 235 uint32_t imageHeight; /* image height */ 236 bool interlaceFlag; /* interlace flag */ 237 bool idv; /* flag of data valid signal is needed flip */ 238 bool ihs; /* flag of horizontal sync pulse is needed flip */ 239 bool ivs; /* flag of vertical sync pulse is needed flip */ 240 }; 241 242 243 /* edid monitor descriptor */ 244 #define HDMI_EDID_MONITOR_FLAGS_FIELD_LEN 3 245 #define HDMI_EDID_MONITOR_DATA_FIELD_LEN 13 246 #define HDMI_EDID_MAX_SINK_NAME_COUNT 14 247 248 enum HdmiEdidMonitorDataType { 249 HDMI_EDID_MONITOR_DATA_NAME = 0xFC, 250 HDMI_EDID_MONITOR_DATA_RANGE_LIMIT = 0xFD, 251 HDMI_EDID_MONITOR_DATA_STRING = 0xFE, 252 HDMI_EDID_MONITOR_DATA_SERIAL_NUMBER = 0xFF, 253 }; 254 255 struct HdmiEdidMonitorBlockInfo { 256 uint8_t flags[HDMI_EDID_MONITOR_FLAGS_FIELD_LEN]; 257 uint8_t dataTag; 258 uint8_t flag; 259 uint8_t data[HDMI_EDID_MONITOR_DATA_FIELD_LEN]; 260 }; 261 262 /* edid extension flag and checksum */ 263 #define HDMI_EDID_EXTENSION_BLOCK_ADDR 0x7E 264 #define HDMI_EDID_CHECKSUM_ADDR 0x7F 265 266 struct HdmiEdidFirstBlockInfo { 267 uint8_t header[HDMI_EDID_BLOCK_HEADER_FIELD_LEN]; 268 uint8_t vendorName[HDMI_EDID_MANUFACRURER_NAME_FIELD_LEN]; 269 uint8_t productCode[HDMI_EDID_PRODUCT_CODE_FIELD_LEN]; 270 uint8_t serialNumber[HDMI_EDID_SERIAL_NUMBER_FIELD_LEN]; 271 uint8_t week; /* 272 * The designated values for this field range from 1 to 53. If this field is unused, the value 273 * should be set to 0. If the next field is used for Model Year, then 0xFF should be set. 274 */ 275 uint8_t year; /* This value is determined by the actual year of production minus 1990. */ 276 uint8_t version; 277 uint8_t revision; 278 uint8_t videoInput; 279 uint8_t width; /* unit: cm */ 280 uint8_t height; /* unit: cm */ 281 uint8_t gamma; /* Display Transfer Characteristics */ 282 uint8_t features; 283 uint8_t redGreenLow; 284 uint8_t blueWhiteLow; 285 uint8_t redX; 286 uint8_t redY; 287 uint8_t greenX; 288 uint8_t greenY; 289 uint8_t blueX; 290 uint8_t blueY; 291 uint8_t whiteX; 292 uint8_t whiteY; 293 uint8_t estTimings[HDMI_EDID_ESTABLISHED_TIMINGS_FIELD_LEN]; 294 uint8_t stdTiming[HDMI_EDID_STANDARD_TIMING_FIELD_LEN]; 295 uint8_t detailedTiming1[HDMI_EDID_DETAILED_TIMING_DESCRIPTOR_FIELD_LEN]; 296 uint8_t detailedTiming2[HDMI_EDID_DETAILED_TIMING_DESCRIPTOR_FIELD_LEN]; 297 uint8_t detailedTiming3[HDMI_EDID_DETAILED_TIMING_DESCRIPTOR_FIELD_LEN]; 298 uint8_t detailedTiming4[HDMI_EDID_DETAILED_TIMING_DESCRIPTOR_FIELD_LEN]; 299 uint8_t extensionFlag; 300 uint8_t checksum; 301 }; 302 303 /* edid extension block */ 304 #define HDMI_EDID_CTA_EXTENSION_TAG 0x02 305 #define HDMI_EDID_CTA_EXTENSION3_REVISION 0x03 306 #define HDMI_EDID_EXTENSION_DATA_BLOCK_LEN_MARK 0x1F 307 #define HDMI_EDID_EXTENSION_DATA_BLOCK_TAG_CODE_MARK 0xE0 308 #define HDMI_EDID_EXTENSION_DATA_BLOCK_TAG_CODE_SHIFT 5 309 #define HDMI_EDID_EXTENSION_BLOCK_OFFSET 4 310 #define HDMI_EDID_EXTENSION_D_INVALID_MIN_VAL 4 311 312 enum HdmiEdidExtDataBlockType { 313 HDMI_EDID_NULL_DATA_BLOCK = 0, 314 HDMI_EDID_AUDIO_DATA_BLOCK = 1, 315 HDMI_EDID_VIDEO_DATA_BLOCK = 2, 316 HDMI_EDID_VENDOR_SPECIFIC_DATA_BLOCK = 3, 317 HDMI_EDID_SPEAKER_ALLOCATION_DATA_BLOCK = 4, 318 HDMI_EDID_VESA_DTC_DATA_BLOCK = 5, /* VESA Display Transfer Characteristic Data Block */ 319 HDMI_EDID_USE_EXT_DATA_BLOCK = 7, /* Use Extended Tag */ 320 }; 321 322 struct HdmiEdidColorSpace { 323 bool rgb444; 324 bool ycbcr422; 325 bool ycbcr444; 326 bool ycbcr420; 327 }; 328 329 /* edid extension block: Audio Data Block */ 330 #define HDMI_EDID_EXTENSION_SHORT_AUDIO_DESCRIPTOR_LEN 3 331 #define HDMI_EDID_EXTENSION_MAX_SHORT_AUDIO_DESCRIPTOR_NUM 10 332 #define HDMI_EDID_EXTENSION_AUDIO_FORMAT_CODE_MARK 0x78 333 #define HDMI_EDID_EXTENSION_AUDIO_FORMAT_CODE_SHIFT 3 334 #define HDMI_EDID_EXTENSION_AUDIO_MAX_CHANNEL_MARK 0x07 335 #define HDMI_EDID_EXTENSION_AUDIO_MAX_SAMPLE_RATE_NUM 8 336 #define HDMI_EDID_EXTENSION_AUDIO_MAX_BIT_DEPTH_NUM 6 337 #define HDMI_EDID_EXTENSION_AUDIO_BIT_RATE_FACTOR 8 338 #define HDMI_EDID_EXTENSION_AUDIO_CAP_COUNT 16 339 340 struct HdmiEdidAudioInfo { 341 enum HdmiAudioCodingType formatCode; 342 uint32_t sampleRateNum; 343 enum HdmiSampleRate sampleRate[HDMI_EDID_EXTENSION_AUDIO_MAX_SAMPLE_RATE_NUM]; 344 uint32_t bitDepthNum; 345 enum HdmiAudioBitDepth bitDepth[HDMI_EDID_EXTENSION_AUDIO_MAX_BIT_DEPTH_NUM]; 346 uint8_t channels; 347 uint32_t maxBitRate; /* unit: KHz */ 348 }; 349 350 /* edid extension block: Video Data Block */ 351 #define HDMI_EDID_EXTENSION_VIC_NATIVE_MAX 64 352 #define HDMI_EDID_EXTENSION_VIC_LOWER7_MARK 0x7F 353 #define HDMI_EDID_EXTENSION_MAX_VIC_COUNT 128 354 #define HDMI_EDID_EXTENSION_VIC_INVALID_LOW 128 355 #define HDMI_EDID_EXTENSION_VIC_INVALID_HIGH 192 356 357 /* 358 * Each supported Video Format is represented by a Short Video Descriptor (SVD) containing 359 * a Video Identification Code (VIC) and, in the case of VICs 1 through 64, a Native Video Format indicator. 360 */ 361 struct HdmiEdidVideoInfo { 362 uint32_t vicNum; 363 uint32_t vic[HDMI_EDID_EXTENSION_MAX_VIC_COUNT]; 364 uint32_t nativeFormat; 365 }; 366 367 /* edid extension block: (VSDB)Vendor-Specific Data Block */ 368 #define HDMI_EDID_EXTENSION_VSDB_LEN 3 369 #define HDMI_EDID_EXTENSION_VSDB_IEEE_1ST 0x03 370 #define HDMI_EDID_EXTENSION_VSDB_IEEE_2ND 0x0C 371 #define HDMI_EDID_EXTENSION_VSDB_IEEE_3RD 0x00 372 #define HDMI_EDID_EXTENSION_VSDB_CEC_INVALID_ADDR 0xF 373 #define HDMI_EDID_EXTENSION_MAX_HDMI14_TMDS_RATE 340 /* unit: Mcsc */ 374 #define HDMI_EDID_EXTENSION_TMDS_FACTOR 5 /* unit: MHz */ 375 #define HDMI_EDID_EXTENSION_VSDB_3D_LEN_MARK 0x1F 376 #define HDMI_EDID_EXTENSION_VSDB_VIC_LEN_MARK 0xE0 377 #define HDMI_EDID_EXTENSION_VSDB_VIC_LEN_SHIFT 5 378 #define HDMI_EDID_EXTENSION_VSDB_3D_MULTI_PRESENT_MARK 0x60 379 #define HDMI_EDID_EXTENSION_VSDB_3D_MULTI_PRESENT_SHIFT 5 380 #define HDMI_EDID_EXTENSION_VSDB_3D_STR_INVALID_MARK 0x03 381 382 #define HDMI_EDID_VSDB_MIN_LEN_FOR_CEC_PHY_ADDR 5 383 #define HDMI_EDID_VSDB_MIN_LEN_FOR_COLOR_DEPTH 6 384 #define HDMI_EDID_VSDB_MIN_LEN_FOR_MAX_TMDS_CLOCK 7 385 #define HDMI_EDID_VSDB_MIN_LEN_FOR_SINK_PRESENT 8 386 #define HDMI_EDID_VSDB_MIN_LEN_FOR_VIDEO_LATENCY 9 387 #define HDMI_EDID_VSDB_MIN_LEN_FOR_AUDIO_LATENCY 10 388 #define HDMI_EDID_VSDB_MIN_LEN_FOR_INTERLACED_VIDEO_LATENCY 11 389 #define HDMI_EDID_VSDB_MIN_LEN_FOR_INTERLACED_AUDIO_LATENCY 12 390 #define HDMI_EDID_VSDB_MIN_LEN_FOR_3D_PRESENT_INFO 13 391 #define HDMI_EDID_VSDB_MIN_LEN_FOR_VIC_INFO 14 392 393 struct HdmiEdidVsdbCecAddr { 394 bool addrValid; 395 uint8_t phyAddrA; 396 uint8_t phyAddrB; 397 uint8_t phyAddrC; 398 uint8_t phyAddrD; 399 }; 400 401 struct HdmiEdidDeepColor { 402 bool dcY444; 403 bool dc30bit; 404 bool dc36bit; 405 bool dc48bit; 406 }; 407 408 struct HdmiEdidExtVsdbInfo { 409 struct HdmiEdidVsdbCecAddr cecAddr; 410 struct HdmiEdidDeepColor deepColor; 411 bool supportAi; 412 bool supportDviDual; 413 bool latencyFieldsPresent; 414 bool iLatencyFieldsPresent; 415 bool hdmiVideoPresent; 416 uint8_t videoLatency; 417 uint8_t audioLatency; 418 uint8_t interlacedVideoLatency; 419 uint8_t interlacedAudioLatency; 420 bool _3dPresent; 421 uint8_t _3dMultiPresent; 422 bool support3dType[HDMI_VS_VIDEO_3D_BUTT]; 423 }; 424 425 /* edid extension block: (HF-VSDB)HDMI Forum Vendor-Specific Data Block */ 426 #define HDMI_EDID_EXTENSION_HFVSDB_IEEE_1ST 0xD8 427 #define HDMI_EDID_EXTENSION_HFVSDB_IEEE_2ND 0x5D 428 #define HDMI_EDID_EXTENSION_HFVSDB_IEEE_3RD 0xC4 429 #define HDMI_EDID_EXTENSION_HFVSDB_VERSION 0x01 430 #define HDMI_EDID_EXTENSION_HFVSDB_MIN_INVALID_LEN 7 431 #define HDMI_EDID_EXTENSION_HFVSDB_MAX_INVALID_LEN 31 432 433 /* deep color Y420(4:2:0) */ 434 struct HdmiEdidExtHfVsdbDeepColor { 435 bool dc30bit; 436 bool dc36bit; 437 bool dc48bit; 438 }; 439 440 #define HDMI_EDID_EXTENSION_HFVSDB_DSC_TOTAL_CHUNK_MARK 0x3F 441 442 /* dsc(Display Stream Compression ) */ 443 struct HdmiEdidExtHfVsdbDscInfo { 444 bool dsc1p2; 445 bool dscNative420; 446 bool dscAllBpp; 447 bool dsc10bpc; 448 bool dsc20bpc; 449 bool dsc16bpc; 450 uint8_t dscMaxSlices; 451 uint8_t dscMaxFrlRate; 452 uint8_t dscTotalChunkKBytes; 453 }; 454 455 #define HDMI_EDID_EXTENSION_HFVSDB_VRRMIN_MARK 0x3F 456 #define HDMI_EDID_EXTENSION_HFVSDB_VRRMAX_MARK 0xC0 457 #define HDMI_EDID_EXTENSION_HFVSDB_VRRMAX_SHIFT 2 458 459 struct HdmiEdidExtHfVsdbInfo { 460 bool scdcPresent; 461 bool rrCapable; /* read request cap. */ 462 bool lte340McscScramble; 463 bool independentView; 464 bool dualView; 465 bool _3dOsdDisparity; 466 struct HdmiEdidExtHfVsdbDeepColor dc; 467 /* hdmi 2.1 */ 468 uint8_t maxFrlRate; 469 bool fapaStartLocation; 470 bool allm; 471 bool fva; 472 bool cnmVrr; 473 bool cinemaVrr; 474 bool mDelta; 475 uint8_t vrrMin; 476 uint16_t vrrMax; 477 struct HdmiEdidExtHfVsdbDscInfo dscInfo; 478 }; 479 480 /* edid extension block: Speaker Allocation Data Block */ 481 #define HDMI_EDID_EXTENSION_SADB_MIN_INVALID_LEN 2 482 483 enum HdmiEdidAudioSpeaker { 484 HDMI_EDID_AUDIO_SPEAKER_FL_FR = 0, 485 HDMI_EDID_AUDIO_SPEAKER_LFE = 1, 486 HDMI_EDID_AUDIO_SPEAKER_FC = 2, 487 HDMI_EDID_AUDIO_SPEAKER_BL_BR = 3, 488 HDMI_EDID_AUDIO_SPEAKER_BC = 4, 489 HDMI_EDID_AUDIO_SPEAKER_FLC_FRC = 5, 490 HDMI_EDID_AUDIO_SPEAKER_RLC_RRC = 6, 491 HDMI_EDID_AUDIO_SPEAKER_FLW_FRW = 7, 492 HDMI_EDID_AUDIO_SPEAKER_TPFL_TPFH = 8, 493 HDMI_EDID_AUDIO_SPEAKER_TPC = 9, 494 HDMI_EDID_AUDIO_SPEAKER_TPFC = 10, 495 HDMI_EDID_AUDIO_SPEAKER_BUTT, 496 }; 497 498 /* 499 * If the Tag Code is 7 (Use Extended Tag) then the second byte of the data block contains the Extended 500 * Tag Code, which indicates the actual type of the data block. 501 */ 502 enum HdmiEdidExtExtenedDataBlockType { 503 HDMI_EDID_EXT_VCDB = 0, /* Video Capability Data Block */ 504 HDMI_EDID_EXT_VSVDB = 1, /* Vendor-Specific Video Data Block */ 505 HDMI_EDID_EXT_VESA_DDDB = 2, /* VESA Display Device Data Block */ 506 HDMI_EDID_EXT_VESA_VTBE = 3, /* VESA Video Timing Block Extension */ 507 HDMI_EDID_EXT_CDB = 5, /* Colorimetry Data Block */ 508 HDMI_EDID_EXT_HDR_SMDB = 6, /* HDR Static Metadata Data Block */ 509 HDMI_EDID_EXT_HDR_DMDB = 7, /* HDR Dynamic Metadata Data Block */ 510 HDMI_EDID_EXT_VFPDB = 13, /* Video Format Preference Data Block */ 511 HDMI_EDID_EXT_YCBCR420_VDB = 14, /* YCBCR 4:2:0 Video Data Block */ 512 HDMI_EDID_EXT_YCBCR420_CMDB = 15, /* YCBCR 4:2:0 Capability Map Data Block */ 513 HDMI_EDID_EXT_VSADB = 17, /* Vendor-Specific Audio Data Block */ 514 HDMI_EDID_EXT_RCDB = 19, /* Room Configuration Data Block */ 515 HDMI_EDID_EXT_SLDB = 20, /* Speaker Location Data Block */ 516 HDMI_EDID_EXT_INFOFRAME_DB = 32, /* InfoFrame Data Block (includes one or more Short InfoFrame Descriptors) */ 517 HDMI_EDID_EXT_BUTT, 518 }; 519 520 /* edid extension block: Colorimetry Data Block */ 521 #define HDMI_EDID_CDB_LEN 3 522 523 struct HdmiEdidColorimetry { 524 bool xvYcc601; 525 bool xvYcc709; 526 bool sYcc601; 527 bool opYcc601; 528 bool opRgb; 529 bool bt2020cYcc; 530 bool bt2020Ycc; 531 bool bt2020Rgb; 532 bool dciP3; 533 uint8_t md; 534 }; 535 536 /* edid extension block: Vendor-Specific Video Data Block */ 537 #define HDMI_EDID_VSVDB_DOLBY_OUI 0x00D046 538 #define HDMI_EDID_VSVDB_DOLBY_VERSION_0 0x00 539 #define HDMI_EDID_VSVDB_DOLBY_VERSION_1 0x01 540 #define HDMI_EDID_VSVDB_DOLBY_VERSION_0_LEN 27 541 #define HDMI_EDID_VSVDB_DOLBY_VERSION_1_LEN 14 542 #define HDMI_EDID_VSVDB_DOLBY_LOWER_2BIT_MARK 0x03 543 #define HDMI_EDID_VSVDB_DOLBY_LOWER_3BIT_MARK 0x07 544 #define HDMI_EDID_VSVDB_DOLBY_LOWER_7BIT_MARK 0x7F 545 #define HDMI_EDID_VSVDB_DOLBY_VERSION_MARK 0xE0 546 #define HDMI_EDID_VSVDB_DOLBY_VERSION_SHIFT 5 547 #define HDMI_EDID_VSVDB_DOLBY_DM_VER_MARK 0x1C 548 #define HDMI_EDID_VSVDB_DOLBY_DM_VER_SHIFT 2 549 550 struct HdmiEdidVsvdbDolbyCap { 551 uint32_t oui; 552 uint8_t version; 553 bool yuv422; 554 bool b2160p60; /* capable of processing a max timing 3840X2160p60. */ 555 bool globalDimming; 556 uint16_t redX; 557 uint16_t redY; 558 uint16_t greenX; 559 uint16_t greenY; 560 uint16_t blueX; 561 uint16_t blueY; 562 uint16_t whiteX; /* only version0 support */ 563 uint16_t whiteY; /* only version0 support */ 564 uint16_t minLuminance; 565 uint16_t maxLuminance; 566 uint8_t dMajorVer; /* only version0 support */ 567 uint8_t dMinorVer; /* only version0 support */ 568 bool colorimetry; /* only version1 support */ 569 uint8_t dmVer; /* only version1 support */ 570 }; 571 572 /* edid extension block: Video Capability Data Block */ 573 #define HDMI_EDID_VCDB_LEN 2 574 575 struct HdmiEdidVideoCapability { 576 bool qy; /* Quantization Range(Applies to YCC only) */ 577 bool qs; /* Quantization Range Selectable(Applies to RGB only) */ 578 }; 579 580 /* edid extension block: HDR Static Metadata Data Block */ 581 #define HDMI_EDID_HDR_SMDB_MIN_LEN 3 582 #define HDMI_EDID_HDR_SMDB_MIN_LEN_FOR_MAX_LUMINANCE_DATA 4 583 #define HDMI_EDID_HDR_SMDB_MIN_LEN_FOR_MAX_FRAME_AVE_LUMINANCE_DATA 5 584 #define HDMI_EDID_HDR_SMDB_MIN_LEN_FOR_MIN_LUMINANCE_DATA 6 585 586 /* EOTF(Electro-Optical Transfer Functions) */ 587 struct HdmiEdidHdrSmdbEotf { 588 bool sdr; /* Traditional gamma - SDR Luminance Range */ 589 bool hdr; /* Traditional gamma - HDR Luminance Range */ 590 bool smpteSt2048; /* SMPTE ST 2084 */ 591 bool hlg; /* Hybrid Log-Gamma (HLG) based on Recommendation ITU-R BT.2100-0 */ 592 }; 593 594 struct HdmiEdidHdrCap { 595 struct HdmiEdidHdrSmdbEotf eotf; 596 bool smType1; /* Static Metadata Type 1 */ 597 uint8_t maxLuminancedata; /* Desired Content Max Luminance data */ 598 uint8_t maxFrameAverageLuminanceData; /* Desired Content Max Frame-average Luminance data */ 599 uint8_t minLuminanceData; /* Desired Content Min Luminance data */ 600 }; 601 602 /* edid extension block: YCBCR 4:2:0 Capability Map Data Block */ 603 struct HdmiEdidYcbcr420Cap { 604 uint32_t onlySupportY420VicNum; 605 uint32_t onlySupportY420Format[HDMI_EDID_EXTENSION_MAX_VIC_COUNT]; 606 uint32_t SupportY420VicNum; 607 uint32_t SupportY420Format[HDMI_EDID_EXTENSION_MAX_VIC_COUNT]; 608 }; 609 610 /* sink device cap */ 611 struct HdmiSinkDeviceCapability { 612 uint8_t extBlockNum; 613 struct HdmiEdidVendorInfo vendorInfo; 614 struct HdmiEdidVersionInfo verInfo; 615 char sinkDeviceName[HDMI_EDID_MAX_SINK_NAME_COUNT]; 616 struct HdmiEdidBasicDispParamInfo disp; 617 struct HdmiEdidEstablishedTimingsInfo establishedTimingsInfo; 618 struct HdmiEdidStdTimingInfo stdTimingsInfo[HDMI_EDID_STANDARD_TIMING_COUNT]; 619 struct HdmiEdidColorInfo colorInfo; 620 struct HdmiEdidColorSpace colorSpace; 621 uint32_t preTimingCnt; 622 struct HdmiEdidPreferredTimingInfo preTimingInfo[HDMI_EDID_MAX_DETAILED_TIMING_COUNT]; 623 uint32_t audioInfoCnt; 624 struct HdmiEdidAudioInfo audioInfo[HDMI_EDID_EXTENSION_AUDIO_CAP_COUNT]; 625 struct HdmiEdidVideoInfo videoInfo; 626 uint32_t maxTmdsClk; 627 bool supportHdmi14; 628 bool supportHdmi20; 629 bool supportAudio; 630 struct HdmiEdidExtVsdbInfo vsdbInfo; 631 struct HdmiEdidExtHfVsdbInfo hfVsdbInfo; 632 bool supportAudioSpeaker[HDMI_EDID_AUDIO_SPEAKER_BUTT]; 633 struct HdmiEdidColorimetry colorimetry; 634 struct HdmiEdidVideoCapability videoCap; 635 struct HdmiEdidYcbcr420Cap y420Cap; 636 struct HdmiEdidHdrCap hdrCap; 637 struct HdmiEdidVsvdbDolbyCap dolbyCap; 638 }; 639 640 /* 641 * EDID(Extended Display Identification Data). 642 * The Source read the Sink's EDID in order to discover the Sink's configuration and/or capabilities. 643 */ 644 struct HdmiEdid { 645 bool edidPhase; 646 uint32_t rawLen; 647 uint8_t raw[HDMI_EDID_TOTAL_SIZE]; 648 struct HdmiSinkDeviceCapability sinkCap; 649 }; 650 651 typedef int32_t (*HdmiEdidPhaseFunc)(struct HdmiEdid *edid); 652 653 int32_t HdmiEdidReset(struct HdmiEdid *edid); 654 int32_t HdmiEdidPhase(struct HdmiEdid *edid); 655 int32_t HdmiEdidGetRaw(struct HdmiEdid *edid, uint8_t *raw, uint32_t len); 656 int32_t HdmiEdidRawDataRead(struct HdmiEdid *edid, struct HdmiDdc *ddc); 657 658 #ifdef __cplusplus 659 #if __cplusplus 660 } 661 #endif 662 #endif /* __cplusplus */ 663 664 #endif /* HDMI_EDID_H */ 665