1 /**********************************************************
2 * Copyright 2009-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 /**
27 * @file
28 * Common definitions for the VMware SVGA winsys.
29 *
30 * @author Jose Fonseca <jfonseca@vmware.com>
31 */
32
33
34 #ifndef VMW_SCREEN_H_
35 #define VMW_SCREEN_H_
36
37
38 #include "pipe/p_compiler.h"
39 #include "pipe/p_state.h"
40
41 #include "svga_winsys.h"
42 #include "pipebuffer/pb_buffer_fenced.h"
43 #include <os/os_thread.h>
44 #include <sys/types.h>
45
46 #define VMW_GMR_POOL_SIZE (16*1024*1024)
47 #define VMW_QUERY_POOL_SIZE (8192)
48 #define VMW_DEBUG_FLUSH_STACK 10
49
50 /*
51 * Something big, but arbitrary. The kernel reports an error if it can't
52 * handle this, and the svga driver will resort to multiple partial
53 * uploads.
54 */
55 #define VMW_MAX_BUFFER_SIZE (512*1024*1024)
56
57 struct pb_manager;
58 struct vmw_region;
59
60 struct vmw_cap_3d {
61 boolean has_cap;
62 SVGA3dDevCapResult result;
63 };
64
65 struct vmw_winsys_screen
66 {
67 struct svga_winsys_screen base;
68
69 struct {
70 int drm_fd;
71 uint32_t hwversion;
72 uint32_t num_cap_3d;
73 struct vmw_cap_3d *cap_3d;
74 uint64_t max_mob_memory;
75 uint64_t max_surface_memory;
76 uint64_t max_texture_size;
77 boolean have_drm_2_6;
78 boolean have_drm_2_9;
79 uint32_t drm_execbuf_version;
80 boolean have_drm_2_15;
81 boolean have_drm_2_16;
82 boolean have_drm_2_17;
83 boolean have_drm_2_18;
84 boolean have_drm_2_19;
85 boolean have_drm_2_20;
86 } ioctl;
87
88 struct {
89 struct pb_manager *gmr;
90 struct pb_manager *gmr_mm;
91 struct pb_manager *gmr_fenced;
92 struct pb_manager *gmr_slab;
93 struct pb_manager *gmr_slab_fenced;
94 struct pb_manager *query_mm;
95 struct pb_manager *query_fenced;
96 struct pb_manager *mob_fenced;
97 struct pb_manager *mob_cache;
98 struct pb_manager *mob_shader_slab;
99 struct pb_manager *mob_shader_slab_fenced;
100 } pools;
101
102 struct pb_fence_ops *fence_ops;
103
104 #ifdef VMX86_STATS
105 /*
106 * mksGuestStats TLS array; length must be power of two
107 */
108 struct {
109 void * stat_pages;
110 uint64_t stat_id;
111 uint32_t pid;
112 } mksstat_tls[64];
113
114 #endif
115 /*
116 * Screen instances
117 */
118 dev_t device;
119 int open_count;
120
121 cnd_t cs_cond;
122 mtx_t cs_mutex;
123
124 boolean force_coherent;
125 boolean cache_maps;
126 };
127
128
129 static inline struct vmw_winsys_screen *
vmw_winsys_screen(struct svga_winsys_screen * base)130 vmw_winsys_screen(struct svga_winsys_screen *base)
131 {
132 return (struct vmw_winsys_screen *)base;
133 }
134
135 /* */
136 uint32_t
137 vmw_region_size(struct vmw_region *region);
138
139 uint32
140 vmw_ioctl_context_create(struct vmw_winsys_screen *vws);
141
142 uint32
143 vmw_ioctl_extended_context_create(struct vmw_winsys_screen *vws,
144 boolean vgpu10);
145
146 void
147 vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws,
148 uint32 cid);
149
150 uint32
151 vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
152 SVGA3dSurface1Flags flags,
153 SVGA3dSurfaceFormat format,
154 unsigned usage,
155 SVGA3dSize size,
156 uint32 numFaces,
157 uint32 numMipLevels,
158 unsigned sampleCount);
159 uint32
160 vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
161 SVGA3dSurfaceAllFlags flags,
162 SVGA3dSurfaceFormat format,
163 unsigned usage,
164 SVGA3dSize size,
165 uint32 numFaces,
166 uint32 numMipLevels,
167 unsigned sampleCount,
168 uint32 buffer_handle,
169 SVGA3dMSPattern multisamplePattern,
170 SVGA3dMSQualityLevel qualityLevel,
171 struct vmw_region **p_region);
172
173 int
174 vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
175 const struct winsys_handle *whandle,
176 SVGA3dSurfaceAllFlags *flags,
177 SVGA3dSurfaceFormat *format,
178 uint32_t *numMipLevels,
179 uint32_t *handle,
180 struct vmw_region **p_region);
181
182 void
183 vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws,
184 uint32 sid);
185
186 void
187 vmw_ioctl_command(struct vmw_winsys_screen *vws,
188 int32_t cid,
189 uint32_t throttle_us,
190 void *commands,
191 uint32_t size,
192 struct pipe_fence_handle **fence,
193 int32_t imported_fence_fd,
194 uint32_t flags);
195
196 struct vmw_region *
197 vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size);
198
199 void
200 vmw_ioctl_region_destroy(struct vmw_region *region);
201
202 struct SVGAGuestPtr
203 vmw_ioctl_region_ptr(struct vmw_region *region);
204
205 void *
206 vmw_ioctl_region_map(struct vmw_region *region);
207 void
208 vmw_ioctl_region_unmap(struct vmw_region *region);
209
210
211 int
212 vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
213 uint32_t handle, uint32_t flags);
214
215 int
216 vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
217 uint32_t handle, uint32_t flags);
218
219 void
220 vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
221 uint32_t handle);
222
223 uint32
224 vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
225 SVGA3dShaderType type,
226 uint32 code_len);
227 void
228 vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid);
229
230 int
231 vmw_ioctl_syncforcpu(struct vmw_region *region,
232 boolean dont_block,
233 boolean readonly,
234 boolean allow_cs);
235 void
236 vmw_ioctl_releasefromcpu(struct vmw_region *region,
237 boolean readonly,
238 boolean allow_cs);
239 /* Initialize parts of vmw_winsys_screen at startup:
240 */
241 boolean vmw_ioctl_init(struct vmw_winsys_screen *vws);
242 boolean vmw_pools_init(struct vmw_winsys_screen *vws);
243 boolean vmw_query_pools_init(struct vmw_winsys_screen *vws);
244 boolean vmw_mob_pools_init(struct vmw_winsys_screen *vws);
245 boolean vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws);
246
247 void vmw_ioctl_cleanup(struct vmw_winsys_screen *vws);
248 void vmw_pools_cleanup(struct vmw_winsys_screen *vws);
249
250 struct vmw_winsys_screen *vmw_winsys_create(int fd);
251 void vmw_winsys_destroy(struct vmw_winsys_screen *sws);
252 void vmw_winsys_screen_set_throttling(struct pipe_screen *screen,
253 uint32_t throttle_us);
254
255 struct pb_manager *
256 simple_fenced_bufmgr_create(struct pb_manager *provider,
257 struct pb_fence_ops *ops);
258 void
259 vmw_fences_signal(struct pb_fence_ops *fence_ops,
260 uint32_t signaled,
261 uint32_t emitted,
262 boolean has_emitted);
263
264 struct svga_winsys_gb_shader *
265 vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
266 SVGA3dShaderType type,
267 const uint32 *bytecode,
268 uint32 bytecodeLen);
269 void
270 vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
271 struct svga_winsys_gb_shader *shader);
272
273 size_t
274 vmw_svga_winsys_stats_len(void);
275
276 #endif /* VMW_SCREEN_H_ */
277