1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/init.h>
3 #include <linux/module.h>
4 #include <linux/types.h>
5 #include <linux/io.h>
6 #include <linux/export.h>
7 #include <linux/slab.h>
8 #include <linux/platform_device.h>
9 #include <linux/fs.h>
10 #include <linux/rwsem.h>
11 #include "kpc_dma_driver.h"
12
13 /********** IRQ Handlers **********/
14 static
ndd_irq_handler(int irq,void * dev_id)15 irqreturn_t ndd_irq_handler(int irq, void *dev_id)
16 {
17 struct kpc_dma_device *ldev = (struct kpc_dma_device *)dev_id;
18
19 if ((GetEngineControl(ldev) & ENG_CTL_IRQ_ACTIVE) || (ldev->desc_completed->MyDMAAddr != GetEngineCompletePtr(ldev)))
20 schedule_work(&ldev->irq_work);
21
22 return IRQ_HANDLED;
23 }
24
25 static
ndd_irq_worker(struct work_struct * ws)26 void ndd_irq_worker(struct work_struct *ws)
27 {
28 struct kpc_dma_descriptor *cur;
29 struct kpc_dma_device *eng = container_of(ws, struct kpc_dma_device, irq_work);
30
31 lock_engine(eng);
32
33 if (GetEngineCompletePtr(eng) == 0)
34 goto out;
35
36 if (eng->desc_completed->MyDMAAddr == GetEngineCompletePtr(eng))
37 goto out;
38
39 cur = eng->desc_completed;
40 do {
41 cur = cur->Next;
42 dev_dbg(&eng->pldev->dev, "Handling completed descriptor %p (acd = %p)\n", cur, cur->acd);
43 BUG_ON(cur == eng->desc_next); // Ordering failure.
44
45 if (cur->DescControlFlags & DMA_DESC_CTL_SOP) {
46 eng->accumulated_bytes = 0;
47 eng->accumulated_flags = 0;
48 }
49
50 eng->accumulated_bytes += cur->DescByteCount;
51 if (cur->DescStatusFlags & DMA_DESC_STS_ERROR)
52 eng->accumulated_flags |= ACD_FLAG_ENG_ACCUM_ERROR;
53
54 if (cur->DescStatusFlags & DMA_DESC_STS_SHORT)
55 eng->accumulated_flags |= ACD_FLAG_ENG_ACCUM_SHORT;
56
57 if (cur->DescControlFlags & DMA_DESC_CTL_EOP) {
58 if (cur->acd)
59 transfer_complete_cb(cur->acd, eng->accumulated_bytes, eng->accumulated_flags | ACD_FLAG_DONE);
60 }
61
62 eng->desc_completed = cur;
63 } while (cur->MyDMAAddr != GetEngineCompletePtr(eng));
64
65 out:
66 SetClearEngineControl(eng, ENG_CTL_IRQ_ACTIVE, 0);
67
68 unlock_engine(eng);
69 }
70
71 /********** DMA Engine Init/Teardown **********/
start_dma_engine(struct kpc_dma_device * eng)72 void start_dma_engine(struct kpc_dma_device *eng)
73 {
74 eng->desc_next = eng->desc_pool_first;
75 eng->desc_completed = eng->desc_pool_last;
76
77 // Setup the engine pointer registers
78 SetEngineNextPtr(eng, eng->desc_pool_first);
79 SetEngineSWPtr(eng, eng->desc_pool_first);
80 ClearEngineCompletePtr(eng);
81
82 WriteEngineControl(eng, ENG_CTL_DMA_ENABLE | ENG_CTL_IRQ_ENABLE);
83 }
84
setup_dma_engine(struct kpc_dma_device * eng,u32 desc_cnt)85 int setup_dma_engine(struct kpc_dma_device *eng, u32 desc_cnt)
86 {
87 u32 caps;
88 struct kpc_dma_descriptor *cur;
89 struct kpc_dma_descriptor *next;
90 dma_addr_t next_handle;
91 dma_addr_t head_handle;
92 unsigned int i;
93 int rv;
94
95 caps = GetEngineCapabilities(eng);
96
97 if (WARN(!(caps & ENG_CAP_PRESENT), "%s() called for DMA Engine at %p which isn't present in hardware!\n", __func__, eng))
98 return -ENXIO;
99
100 if (caps & ENG_CAP_DIRECTION)
101 eng->dir = DMA_FROM_DEVICE;
102 else
103 eng->dir = DMA_TO_DEVICE;
104
105 eng->desc_pool_cnt = desc_cnt;
106 eng->desc_pool = dma_pool_create("KPC DMA Descriptors", &eng->pldev->dev, sizeof(struct kpc_dma_descriptor), DMA_DESC_ALIGNMENT, 4096);
107
108 eng->desc_pool_first = dma_pool_alloc(eng->desc_pool, GFP_KERNEL | GFP_DMA, &head_handle);
109 if (!eng->desc_pool_first) {
110 dev_err(&eng->pldev->dev, "%s: couldn't allocate desc_pool_first!\n", __func__);
111 dma_pool_destroy(eng->desc_pool);
112 return -ENOMEM;
113 }
114
115 eng->desc_pool_first->MyDMAAddr = head_handle;
116 clear_desc(eng->desc_pool_first);
117
118 cur = eng->desc_pool_first;
119 for (i = 1 ; i < eng->desc_pool_cnt ; i++) {
120 next = dma_pool_alloc(eng->desc_pool, GFP_KERNEL | GFP_DMA, &next_handle);
121 if (!next)
122 goto done_alloc;
123
124 clear_desc(next);
125 next->MyDMAAddr = next_handle;
126
127 cur->DescNextDescPtr = next_handle;
128 cur->Next = next;
129 cur = next;
130 }
131
132 done_alloc:
133 // Link the last descriptor back to the first, so it's a circular linked list
134 cur->Next = eng->desc_pool_first;
135 cur->DescNextDescPtr = eng->desc_pool_first->MyDMAAddr;
136
137 eng->desc_pool_last = cur;
138 eng->desc_completed = eng->desc_pool_last;
139
140 // Setup work queue
141 INIT_WORK(&eng->irq_work, ndd_irq_worker);
142
143 // Grab IRQ line
144 rv = request_irq(eng->irq, ndd_irq_handler, IRQF_SHARED, KP_DRIVER_NAME_DMA_CONTROLLER, eng);
145 if (rv) {
146 dev_err(&eng->pldev->dev, "%s: failed to request_irq: %d\n", __func__, rv);
147 return rv;
148 }
149
150 // Turn on the engine!
151 start_dma_engine(eng);
152 unlock_engine(eng);
153
154 return 0;
155 }
156
stop_dma_engine(struct kpc_dma_device * eng)157 void stop_dma_engine(struct kpc_dma_device *eng)
158 {
159 unsigned long timeout;
160
161 // Disable the descriptor engine
162 WriteEngineControl(eng, 0);
163
164 // Wait for descriptor engine to finish current operaion
165 timeout = jiffies + (HZ / 2);
166 while (GetEngineControl(eng) & ENG_CTL_DMA_RUNNING) {
167 if (time_after(jiffies, timeout)) {
168 dev_crit(&eng->pldev->dev, "DMA_RUNNING still asserted!\n");
169 break;
170 }
171 }
172
173 // Request a reset
174 WriteEngineControl(eng, ENG_CTL_DMA_RESET_REQUEST);
175
176 // Wait for reset request to be processed
177 timeout = jiffies + (HZ / 2);
178 while (GetEngineControl(eng) & (ENG_CTL_DMA_RUNNING | ENG_CTL_DMA_RESET_REQUEST)) {
179 if (time_after(jiffies, timeout)) {
180 dev_crit(&eng->pldev->dev, "ENG_CTL_DMA_RESET_REQUEST still asserted!\n");
181 break;
182 }
183 }
184
185 // Request a reset
186 WriteEngineControl(eng, ENG_CTL_DMA_RESET);
187
188 // And wait for reset to complete
189 timeout = jiffies + (HZ / 2);
190 while (GetEngineControl(eng) & ENG_CTL_DMA_RESET) {
191 if (time_after(jiffies, timeout)) {
192 dev_crit(&eng->pldev->dev, "DMA_RESET still asserted!\n");
193 break;
194 }
195 }
196
197 // Clear any persistent bits just to make sure there is no residue from the reset
198 SetClearEngineControl(eng, (ENG_CTL_IRQ_ACTIVE | ENG_CTL_DESC_COMPLETE | ENG_CTL_DESC_ALIGN_ERR | ENG_CTL_DESC_FETCH_ERR | ENG_CTL_SW_ABORT_ERR | ENG_CTL_DESC_CHAIN_END | ENG_CTL_DMA_WAITING_PERSIST), 0);
199
200 // Reset performance counters
201
202 // Completely disable the engine
203 WriteEngineControl(eng, 0);
204 }
205
destroy_dma_engine(struct kpc_dma_device * eng)206 void destroy_dma_engine(struct kpc_dma_device *eng)
207 {
208 struct kpc_dma_descriptor *cur;
209 dma_addr_t cur_handle;
210 unsigned int i;
211
212 stop_dma_engine(eng);
213
214 cur = eng->desc_pool_first;
215 cur_handle = eng->desc_pool_first->MyDMAAddr;
216
217 for (i = 0 ; i < eng->desc_pool_cnt ; i++) {
218 struct kpc_dma_descriptor *next = cur->Next;
219 dma_addr_t next_handle = cur->DescNextDescPtr;
220
221 dma_pool_free(eng->desc_pool, cur, cur_handle);
222 cur_handle = next_handle;
223 cur = next;
224 }
225
226 dma_pool_destroy(eng->desc_pool);
227
228 free_irq(eng->irq, eng);
229 }
230
231 /********** Helper Functions **********/
count_descriptors_available(struct kpc_dma_device * eng)232 int count_descriptors_available(struct kpc_dma_device *eng)
233 {
234 u32 count = 0;
235 struct kpc_dma_descriptor *cur = eng->desc_next;
236
237 while (cur != eng->desc_completed) {
238 BUG_ON(!cur);
239 count++;
240 cur = cur->Next;
241 }
242 return count;
243 }
244
clear_desc(struct kpc_dma_descriptor * desc)245 void clear_desc(struct kpc_dma_descriptor *desc)
246 {
247 if (!desc)
248 return;
249 desc->DescByteCount = 0;
250 desc->DescStatusErrorFlags = 0;
251 desc->DescStatusFlags = 0;
252 desc->DescUserControlLS = 0;
253 desc->DescUserControlMS = 0;
254 desc->DescCardAddrLS = 0;
255 desc->DescBufferByteCount = 0;
256 desc->DescCardAddrMS = 0;
257 desc->DescControlFlags = 0;
258 desc->DescSystemAddrLS = 0;
259 desc->DescSystemAddrMS = 0;
260 desc->acd = NULL;
261 }
262