1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __isa(isa) (cpu_data[0].isa_level & (isa)) 19 #define __opt(opt) (cpu_data[0].options & (opt)) 20 21 /* 22 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 23 * boot (typically by cpu_probe()). 24 * 25 * Note that these should only be used in cases where a kernel built for an 26 * older ISA *cannot* run on a CPU which supports the feature in question. For 27 * example this may be used for features introduced with MIPSr6, since a kernel 28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 30 * MIPSr2 CPU. 31 */ 32 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 33 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 34 35 /* 36 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 37 * boot (typically by cpu_probe()). 38 * 39 * These are for use with features that are optional up until a particular ISA 40 * revision & then become required. 41 */ 42 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 43 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 44 45 /* 46 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 47 * boot (typically by cpu_probe()). 48 * 49 * These are for use with features that are optional up until a particular ISA 50 * revision & are then removed - ie. no longer present in any CPU implementing 51 * the given ISA revision. 52 */ 53 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 54 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 55 56 /* 57 * Similarly allow for ISA level checks that take into account knowledge of the 58 * ISA targeted by the kernel build, provided by MIPS_ISA_REV. 59 */ 60 #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) 61 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) 62 #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) 63 #define __isa_range(ge, lt) \ 64 ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) 65 #define __isa_range_or_flag(ge, lt, flag) \ 66 (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) 67 #define __isa_range_and_ase(ge, lt, ase) \ 68 (__isa_range(ge, lt) && __ase(ase)) 69 70 /* 71 * SMP assumption: Options of CPU 0 are a superset of all processors. 72 * This is true for all known MIPS systems. 73 */ 74 #ifndef cpu_has_tlb 75 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 76 #endif 77 #ifndef cpu_has_ftlb 78 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 79 #endif 80 #ifndef cpu_has_tlbinv 81 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 82 #endif 83 #ifndef cpu_has_segments 84 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 85 #endif 86 #ifndef cpu_has_eva 87 #define cpu_has_eva __opt(MIPS_CPU_EVA) 88 #endif 89 #ifndef cpu_has_htw 90 #define cpu_has_htw __opt(MIPS_CPU_HTW) 91 #endif 92 #ifndef cpu_has_ldpte 93 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 94 #endif 95 #ifndef cpu_has_rixiex 96 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 97 #endif 98 #ifndef cpu_has_maar 99 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 100 #endif 101 #ifndef cpu_has_rw_llb 102 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 103 #endif 104 105 /* 106 * For the moment we don't consider R6000 and R8000 so we can assume that 107 * anything that doesn't support R4000-style exceptions and interrupts is 108 * R3000-like. Users should still treat these two macro definitions as 109 * opaque. 110 */ 111 #ifndef cpu_has_3kex 112 #define cpu_has_3kex (!cpu_has_4kex) 113 #endif 114 #ifndef cpu_has_4kex 115 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 116 #endif 117 #ifndef cpu_has_3k_cache 118 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 119 #endif 120 #define cpu_has_6k_cache 0 121 #define cpu_has_8k_cache 0 122 #ifndef cpu_has_4k_cache 123 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 124 #endif 125 #ifndef cpu_has_tx39_cache 126 #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 127 #endif 128 #ifndef cpu_has_octeon_cache 129 #define cpu_has_octeon_cache 0 130 #endif 131 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 132 #ifndef cpu_has_fpu 133 # ifdef CONFIG_MIPS_FP_SUPPORT 134 # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 135 # define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 136 # else 137 # define cpu_has_fpu 0 138 # define raw_cpu_has_fpu 0 139 # endif 140 #else 141 # define raw_cpu_has_fpu cpu_has_fpu 142 #endif 143 #ifndef cpu_has_32fpr 144 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 145 #endif 146 #ifndef cpu_has_counter 147 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 148 #endif 149 #ifndef cpu_has_watch 150 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 151 #endif 152 #ifndef cpu_has_divec 153 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 154 #endif 155 #ifndef cpu_has_vce 156 #define cpu_has_vce __opt(MIPS_CPU_VCE) 157 #endif 158 #ifndef cpu_has_cache_cdex_p 159 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 160 #endif 161 #ifndef cpu_has_cache_cdex_s 162 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 163 #endif 164 #ifndef cpu_has_prefetch 165 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 166 #endif 167 #ifndef cpu_has_mcheck 168 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 169 #endif 170 #ifndef cpu_has_ejtag 171 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 172 #endif 173 #ifndef cpu_has_llsc 174 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 175 #endif 176 #ifndef kernel_uses_llsc 177 #define kernel_uses_llsc cpu_has_llsc 178 #endif 179 #ifndef cpu_has_guestctl0ext 180 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 181 #endif 182 #ifndef cpu_has_guestctl1 183 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 184 #endif 185 #ifndef cpu_has_guestctl2 186 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 187 #endif 188 #ifndef cpu_has_guestid 189 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 190 #endif 191 #ifndef cpu_has_drg 192 #define cpu_has_drg __opt(MIPS_CPU_DRG) 193 #endif 194 #ifndef cpu_has_mips16 195 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 196 #endif 197 #ifndef cpu_has_mips16e2 198 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 199 #endif 200 #ifndef cpu_has_mdmx 201 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 202 #endif 203 #ifndef cpu_has_mips3d 204 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 205 #endif 206 #ifndef cpu_has_smartmips 207 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 208 #endif 209 210 #ifndef cpu_has_rixi 211 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 212 #endif 213 214 #ifndef cpu_has_mmips 215 # if defined(__mips_micromips) 216 # define cpu_has_mmips 1 217 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 218 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 219 # else 220 # define cpu_has_mmips 0 221 # endif 222 #endif 223 224 #ifndef cpu_has_lpa 225 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 226 #endif 227 #ifndef cpu_has_mvh 228 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 229 #endif 230 #ifndef cpu_has_xpa 231 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 232 #endif 233 #ifndef cpu_has_vtag_icache 234 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 235 #endif 236 #ifndef cpu_has_dc_aliases 237 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 238 #endif 239 #ifndef cpu_has_ic_fills_f_dc 240 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 241 #endif 242 #ifndef cpu_has_pindexed_dcache 243 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 244 #endif 245 246 /* 247 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 248 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 249 * don't. For maintaining I-cache coherency this means we need to flush the 250 * D-cache all the way back to whever the I-cache does refills from, so the 251 * I-cache has a chance to see the new data at all. Then we have to flush the 252 * I-cache also. 253 * Note we may have been rescheduled and may no longer be running on the CPU 254 * that did the store so we can't optimize this into only doing the flush on 255 * the local CPU. 256 */ 257 #ifndef cpu_icache_snoops_remote_store 258 #ifdef CONFIG_SMP 259 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 260 #else 261 #define cpu_icache_snoops_remote_store 1 262 #endif 263 #endif 264 265 #ifndef cpu_has_mips_1 266 # define cpu_has_mips_1 (MIPS_ISA_REV < 6) 267 #endif 268 #ifndef cpu_has_mips_2 269 # define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) 270 #endif 271 #ifndef cpu_has_mips_3 272 # define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) 273 #endif 274 #ifndef cpu_has_mips_4 275 # define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) 276 #endif 277 #ifndef cpu_has_mips_5 278 # define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) 279 #endif 280 #ifndef cpu_has_mips32r1 281 # define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) 282 #endif 283 #ifndef cpu_has_mips32r2 284 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 285 #endif 286 #ifndef cpu_has_mips32r5 287 # define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5) 288 #endif 289 #ifndef cpu_has_mips32r6 290 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 291 #endif 292 #ifndef cpu_has_mips64r1 293 # define cpu_has_mips64r1 (cpu_has_64bits && \ 294 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)) 295 #endif 296 #ifndef cpu_has_mips64r2 297 # define cpu_has_mips64r2 (cpu_has_64bits && \ 298 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)) 299 #endif 300 #ifndef cpu_has_mips64r5 301 # define cpu_has_mips64r5 (cpu_has_64bits && \ 302 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5)) 303 #endif 304 #ifndef cpu_has_mips64r6 305 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) 306 #endif 307 308 /* 309 * Shortcuts ... 310 */ 311 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 312 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 313 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 314 315 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 316 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 317 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 318 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 319 320 #define cpu_has_mips_3_4_5_64_r2_r6 \ 321 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 322 #define cpu_has_mips_4_5_64_r2_r6 \ 323 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 324 cpu_has_mips_r2 | cpu_has_mips_r5 | \ 325 cpu_has_mips_r6) 326 327 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 328 cpu_has_mips32r5 | cpu_has_mips32r6) 329 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \ 330 cpu_has_mips64r5 | cpu_has_mips64r6) 331 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 332 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 333 #define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5) 334 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 335 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 336 cpu_has_mips32r5 | cpu_has_mips32r6 | \ 337 cpu_has_mips64r1 | cpu_has_mips64r2 | \ 338 cpu_has_mips64r5 | cpu_has_mips64r6) 339 340 /* MIPSR2 - MIPSR6 have a lot of similarities */ 341 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \ 342 cpu_has_mips_r6) 343 344 /* 345 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 346 * 347 * Returns non-zero value if the current processor implementation requires 348 * an IHB instruction to deal with an instruction hazard as per MIPS R2 349 * architecture specification, zero otherwise. 350 */ 351 #ifndef cpu_has_mips_r2_exec_hazard 352 #define cpu_has_mips_r2_exec_hazard \ 353 ({ \ 354 int __res; \ 355 \ 356 switch (current_cpu_type()) { \ 357 case CPU_M14KC: \ 358 case CPU_74K: \ 359 case CPU_1074K: \ 360 case CPU_PROAPTIV: \ 361 case CPU_P5600: \ 362 case CPU_M5150: \ 363 case CPU_QEMU_GENERIC: \ 364 case CPU_CAVIUM_OCTEON: \ 365 case CPU_CAVIUM_OCTEON_PLUS: \ 366 case CPU_CAVIUM_OCTEON2: \ 367 case CPU_CAVIUM_OCTEON3: \ 368 __res = 0; \ 369 break; \ 370 \ 371 default: \ 372 __res = 1; \ 373 } \ 374 \ 375 __res; \ 376 }) 377 #endif 378 379 /* 380 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 381 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 382 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 383 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 384 */ 385 #ifndef cpu_has_clo_clz 386 #define cpu_has_clo_clz cpu_has_mips_r 387 #endif 388 389 /* 390 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 391 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 392 * This indicates the availability of WSBH and in case of 64 bit CPUs also 393 * DSBH and DSHD. 394 */ 395 #ifndef cpu_has_wsbh 396 #define cpu_has_wsbh cpu_has_mips_r2 397 #endif 398 399 #ifndef cpu_has_dsp 400 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 401 #endif 402 403 #ifndef cpu_has_dsp2 404 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 405 #endif 406 407 #ifndef cpu_has_dsp3 408 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 409 #endif 410 411 #ifndef cpu_has_loongson_mmi 412 #define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 413 #endif 414 415 #ifndef cpu_has_loongson_cam 416 #define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 417 #endif 418 419 #ifndef cpu_has_loongson_ext 420 #define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 421 #endif 422 423 #ifndef cpu_has_loongson_ext2 424 #define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 425 #endif 426 427 #ifndef cpu_has_mipsmt 428 #define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) 429 #endif 430 431 #ifndef cpu_has_vp 432 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 433 #endif 434 435 #ifndef cpu_has_userlocal 436 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 437 #endif 438 439 #ifdef CONFIG_32BIT 440 # ifndef cpu_has_nofpuex 441 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 442 # endif 443 # ifndef cpu_has_64bits 444 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 445 # endif 446 # ifndef cpu_has_64bit_zero_reg 447 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 448 # endif 449 # ifndef cpu_has_64bit_gp_regs 450 # define cpu_has_64bit_gp_regs 0 451 # endif 452 # ifndef cpu_vmbits 453 # define cpu_vmbits 31 454 # endif 455 #endif 456 457 #ifdef CONFIG_64BIT 458 # ifndef cpu_has_nofpuex 459 # define cpu_has_nofpuex 0 460 # endif 461 # ifndef cpu_has_64bits 462 # define cpu_has_64bits 1 463 # endif 464 # ifndef cpu_has_64bit_zero_reg 465 # define cpu_has_64bit_zero_reg 1 466 # endif 467 # ifndef cpu_has_64bit_gp_regs 468 # define cpu_has_64bit_gp_regs 1 469 # endif 470 # ifndef cpu_vmbits 471 # define cpu_vmbits cpu_data[0].vmbits 472 # define __NEED_VMBITS_PROBE 473 # endif 474 #endif 475 476 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 477 # define cpu_has_vint __opt(MIPS_CPU_VINT) 478 #elif !defined(cpu_has_vint) 479 # define cpu_has_vint 0 480 #endif 481 482 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 483 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 484 #elif !defined(cpu_has_veic) 485 # define cpu_has_veic 0 486 #endif 487 488 #ifndef cpu_has_inclusive_pcaches 489 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 490 #endif 491 492 #ifndef cpu_dcache_line_size 493 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 494 #endif 495 #ifndef cpu_icache_line_size 496 #define cpu_icache_line_size() cpu_data[0].icache.linesz 497 #endif 498 #ifndef cpu_scache_line_size 499 #define cpu_scache_line_size() cpu_data[0].scache.linesz 500 #endif 501 #ifndef cpu_tcache_line_size 502 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 503 #endif 504 505 #ifndef cpu_hwrena_impl_bits 506 #define cpu_hwrena_impl_bits 0 507 #endif 508 509 #ifndef cpu_has_perf_cntr_intr_bit 510 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 511 #endif 512 513 #ifndef cpu_has_vz 514 #define cpu_has_vz __ase(MIPS_ASE_VZ) 515 #endif 516 517 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 518 # define cpu_has_msa __ase(MIPS_ASE_MSA) 519 #elif !defined(cpu_has_msa) 520 # define cpu_has_msa 0 521 #endif 522 523 #ifndef cpu_has_ufr 524 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 525 #endif 526 527 #ifndef cpu_has_fre 528 # define cpu_has_fre __opt(MIPS_CPU_FRE) 529 #endif 530 531 #ifndef cpu_has_cdmm 532 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 533 #endif 534 535 #ifndef cpu_has_small_pages 536 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 537 #endif 538 539 #ifndef cpu_has_nan_legacy 540 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 541 #endif 542 #ifndef cpu_has_nan_2008 543 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 544 #endif 545 546 #ifndef cpu_has_ebase_wg 547 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 548 #endif 549 550 #ifndef cpu_has_badinstr 551 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 552 #endif 553 554 #ifndef cpu_has_badinstrp 555 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 556 #endif 557 558 #ifndef cpu_has_contextconfig 559 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 560 #endif 561 562 #ifndef cpu_has_perf 563 # define cpu_has_perf __opt(MIPS_CPU_PERF) 564 #endif 565 566 #ifndef cpu_has_mac2008_only 567 # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) 568 #endif 569 570 #ifndef cpu_has_ftlbparex 571 # define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) 572 #endif 573 574 #ifndef cpu_has_gsexcex 575 # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) 576 #endif 577 578 #ifdef CONFIG_SMP 579 /* 580 * Some systems share FTLB RAMs between threads within a core (siblings in 581 * kernel parlance). This means that FTLB entries may become invalid at almost 582 * any point when an entry is evicted due to a sibling thread writing an entry 583 * to the shared FTLB RAM. 584 * 585 * This is only relevant to SMP systems, and the only systems that exhibit this 586 * property implement MIPSr6 or higher so we constrain support for this to 587 * kernels that will run on such systems. 588 */ 589 # ifndef cpu_has_shared_ftlb_ram 590 # define cpu_has_shared_ftlb_ram \ 591 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 592 # endif 593 594 /* 595 * Some systems take this a step further & share FTLB entries between siblings. 596 * This is implemented as TLB writes happening as usual, but if an entry 597 * written by a sibling exists in the shared FTLB for a translation which would 598 * otherwise cause a TLB refill exception then the CPU will use the entry 599 * written by its sibling rather than triggering a refill & writing a matching 600 * TLB entry for itself. 601 * 602 * This is naturally only valid if a TLB entry is known to be suitable for use 603 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 604 * rather than ASIDs or when a TLB entry is marked global. 605 */ 606 # ifndef cpu_has_shared_ftlb_entries 607 # define cpu_has_shared_ftlb_entries \ 608 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 609 # endif 610 #endif /* SMP */ 611 612 #ifndef cpu_has_shared_ftlb_ram 613 # define cpu_has_shared_ftlb_ram 0 614 #endif 615 #ifndef cpu_has_shared_ftlb_entries 616 # define cpu_has_shared_ftlb_entries 0 617 #endif 618 619 #ifdef CONFIG_MIPS_MT_SMP 620 # define cpu_has_mipsmt_pertccounters \ 621 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 622 #else 623 # define cpu_has_mipsmt_pertccounters 0 624 #endif /* CONFIG_MIPS_MT_SMP */ 625 626 /* 627 * We only enable MMID support for configurations which natively support 64 bit 628 * atomics because getting good performance from the allocator relies upon 629 * efficient atomic64_*() functions. 630 */ 631 #ifndef cpu_has_mmid 632 # ifdef CONFIG_GENERIC_ATOMIC64 633 # define cpu_has_mmid 0 634 # else 635 # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) 636 # endif 637 #endif 638 639 #ifndef cpu_has_mm_sysad 640 # define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD) 641 #endif 642 643 #ifndef cpu_has_mm_full 644 # define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL) 645 #endif 646 647 /* 648 * Guest capabilities 649 */ 650 #ifndef cpu_guest_has_conf1 651 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 652 #endif 653 #ifndef cpu_guest_has_conf2 654 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 655 #endif 656 #ifndef cpu_guest_has_conf3 657 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 658 #endif 659 #ifndef cpu_guest_has_conf4 660 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 661 #endif 662 #ifndef cpu_guest_has_conf5 663 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 664 #endif 665 #ifndef cpu_guest_has_conf6 666 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 667 #endif 668 #ifndef cpu_guest_has_conf7 669 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 670 #endif 671 #ifndef cpu_guest_has_fpu 672 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 673 #endif 674 #ifndef cpu_guest_has_watch 675 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 676 #endif 677 #ifndef cpu_guest_has_contextconfig 678 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 679 #endif 680 #ifndef cpu_guest_has_segments 681 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 682 #endif 683 #ifndef cpu_guest_has_badinstr 684 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 685 #endif 686 #ifndef cpu_guest_has_badinstrp 687 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 688 #endif 689 #ifndef cpu_guest_has_htw 690 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 691 #endif 692 #ifndef cpu_guest_has_ldpte 693 #define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE) 694 #endif 695 #ifndef cpu_guest_has_mvh 696 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 697 #endif 698 #ifndef cpu_guest_has_msa 699 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 700 #endif 701 #ifndef cpu_guest_has_kscr 702 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 703 #endif 704 #ifndef cpu_guest_has_rw_llb 705 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 706 #endif 707 #ifndef cpu_guest_has_perf 708 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 709 #endif 710 #ifndef cpu_guest_has_maar 711 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 712 #endif 713 #ifndef cpu_guest_has_userlocal 714 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 715 #endif 716 717 /* 718 * Guest dynamic capabilities 719 */ 720 #ifndef cpu_guest_has_dyn_fpu 721 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 722 #endif 723 #ifndef cpu_guest_has_dyn_watch 724 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 725 #endif 726 #ifndef cpu_guest_has_dyn_contextconfig 727 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 728 #endif 729 #ifndef cpu_guest_has_dyn_perf 730 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 731 #endif 732 #ifndef cpu_guest_has_dyn_msa 733 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 734 #endif 735 #ifndef cpu_guest_has_dyn_maar 736 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 737 #endif 738 739 #endif /* __ASM_CPU_FEATURES_H */ 740