1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/percpu.h>
69 #include <linux/sort.h>
70 #include <linux/stop_machine.h>
71 #include <linux/types.h>
72 #include <linux/mm.h>
73 #include <linux/cpu.h>
74
75 #include <asm/cpu.h>
76 #include <asm/cpufeature.h>
77 #include <asm/cpu_ops.h>
78 #include <asm/fpsimd.h>
79 #include <asm/hwcap.h>
80 #include <asm/mmu_context.h>
81 #include <asm/mte.h>
82 #include <asm/processor.h>
83 #include <asm/sysreg.h>
84 #include <asm/traps.h>
85 #include <asm/vectors.h>
86 #include <asm/virt.h>
87
88 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
89 static unsigned long elf_hwcap __read_mostly;
90
91 #ifdef CONFIG_COMPAT
92 #define COMPAT_ELF_HWCAP_DEFAULT \
93 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
94 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
95 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
96 COMPAT_HWCAP_LPAE)
97 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
98 unsigned int compat_elf_hwcap2 __read_mostly;
99 #endif
100
101 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
102 EXPORT_SYMBOL(cpu_hwcaps);
103 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
104
105 /* Need also bit for ARM64_CB_PATCH */
106 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
107
108 bool arm64_use_ng_mappings = false;
109 EXPORT_SYMBOL(arm64_use_ng_mappings);
110
111 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
112
113 /*
114 * Flag to indicate if we have computed the system wide
115 * capabilities based on the boot time active CPUs. This
116 * will be used to determine if a new booting CPU should
117 * go through the verification process to make sure that it
118 * supports the system capabilities, without using a hotplug
119 * notifier. This is also used to decide if we could use
120 * the fast path for checking constant CPU caps.
121 */
122 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
123 EXPORT_SYMBOL(arm64_const_caps_ready);
finalize_system_capabilities(void)124 static inline void finalize_system_capabilities(void)
125 {
126 static_branch_enable(&arm64_const_caps_ready);
127 }
128
dump_cpu_features(void)129 void dump_cpu_features(void)
130 {
131 /* file-wide pr_fmt adds "CPU features: " prefix */
132 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
133 }
134
135 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
136 EXPORT_SYMBOL(cpu_hwcap_keys);
137
138 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
139 { \
140 .sign = SIGNED, \
141 .visible = VISIBLE, \
142 .strict = STRICT, \
143 .type = TYPE, \
144 .shift = SHIFT, \
145 .width = WIDTH, \
146 .safe_val = SAFE_VAL, \
147 }
148
149 /* Define a feature with unsigned values */
150 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
151 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
152
153 /* Define a feature with a signed value */
154 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
155 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
156
157 #define ARM64_FTR_END \
158 { \
159 .width = 0, \
160 }
161
162 /* meta feature for alternatives */
163 static bool __maybe_unused
164 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
165
166 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
167
168 static bool __system_matches_cap(unsigned int n);
169
170 /*
171 * NOTE: Any changes to the visibility of features should be kept in
172 * sync with the documentation of the CPU feature register ABI.
173 */
174 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
189 ARM64_FTR_END,
190 };
191
192 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
207 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
209 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
211 ARM64_FTR_END,
212 };
213
214 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
217 ARM64_FTR_END,
218 };
219
220 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
228 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
231 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
232 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
237 ARM64_FTR_END,
238 };
239
240 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
248 ARM64_FTR_END,
249 };
250
251 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
270 ARM64_FTR_END,
271 };
272
273 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
277 /*
278 * Page size not being supported at Stage-2 is not fatal. You
279 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
280 * your favourite nesting hypervisor.
281 *
282 * There is a small corner case where the hypervisor explicitly
283 * advertises a given granule size at Stage-2 (value 2) on some
284 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
285 * vCPUs. Although this is not forbidden by the architecture, it
286 * indicates that the hypervisor is being silly (or buggy).
287 *
288 * We make no effort to cope with this and pretend that if these
289 * fields are inconsistent across vCPUs, then it isn't worth
290 * trying to bring KVM up.
291 */
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
295 /*
296 * We already refuse to boot CPUs that don't support our configured
297 * page size, so we can only detect mismatches for a page size other
298 * than the one we're currently using. Unfortunately, SoCs like this
299 * exist in the wild so, even though we don't like it, we'll have to go
300 * along with it and treat them as non-strict.
301 */
302 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
303 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
305
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
307 /* Linux shouldn't care about secure memory */
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
311 /*
312 * Differing PARange is fine as long as all peripherals and memory are mapped
313 * within the minimum PARange of all CPUs
314 */
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
316 ARM64_FTR_END,
317 };
318
319 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
320 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
331 ARM64_FTR_END,
332 };
333
334 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
350 ARM64_FTR_END,
351 };
352
353 static const struct arm64_ftr_bits ftr_ctr[] = {
354 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
355 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
356 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
357 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
358 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
359 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
360 /*
361 * Linux can handle differing I-cache policies. Userspace JITs will
362 * make use of *minLine.
363 * If we have differing I-cache policies, report it as the weakest - VIPT.
364 */
365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
367 ARM64_FTR_END,
368 };
369
370 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
371 .name = "SYS_CTR_EL0",
372 .ftr_bits = ftr_ctr
373 };
374
375 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
376 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
381 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
384 ARM64_FTR_END,
385 };
386
387 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
388 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
393 /*
394 * We can instantiate multiple PMU instances with different levels
395 * of support.
396 */
397 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
399 ARM64_FTR_END,
400 };
401
402 static const struct arm64_ftr_bits ftr_mvfr2[] = {
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
405 ARM64_FTR_END,
406 };
407
408 static const struct arm64_ftr_bits ftr_dczid[] = {
409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
411 ARM64_FTR_END,
412 };
413
414 static const struct arm64_ftr_bits ftr_id_isar0[] = {
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
422 ARM64_FTR_END,
423 };
424
425 static const struct arm64_ftr_bits ftr_id_isar5[] = {
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
432 ARM64_FTR_END,
433 };
434
435 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
443
444 /*
445 * SpecSEI = 1 indicates that the PE might generate an SError on an
446 * external abort on speculative read. It is safe to assume that an
447 * SError might be generated than it will not be. Hence it has been
448 * classified as FTR_HIGHER_SAFE.
449 */
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
451 ARM64_FTR_END,
452 };
453
454 static const struct arm64_ftr_bits ftr_id_isar4[] = {
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
463 ARM64_FTR_END,
464 };
465
466 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
468 ARM64_FTR_END,
469 };
470
471 static const struct arm64_ftr_bits ftr_id_isar6[] = {
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
479 ARM64_FTR_END,
480 };
481
482 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
489 ARM64_FTR_END,
490 };
491
492 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
501 ARM64_FTR_END,
502 };
503
504 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
507 ARM64_FTR_END,
508 };
509
510 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
511 /* [31:28] TraceFilt */
512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
519 ARM64_FTR_END,
520 };
521
522 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
523 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
524 ARM64_FTR_END,
525 };
526
527 static const struct arm64_ftr_bits ftr_zcr[] = {
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
529 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
530 ARM64_FTR_END,
531 };
532
533 /*
534 * Common ftr bits for a 32bit register with all hidden, strict
535 * attributes, with 4bit feature fields and a default safe value of
536 * 0. Covers the following 32bit registers:
537 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
538 */
539 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
548 ARM64_FTR_END,
549 };
550
551 /* Table for a single 32bit feature value */
552 static const struct arm64_ftr_bits ftr_single32[] = {
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
554 ARM64_FTR_END,
555 };
556
557 static const struct arm64_ftr_bits ftr_raz[] = {
558 ARM64_FTR_END,
559 };
560
561 #define ARM64_FTR_REG(id, table) { \
562 .sys_id = id, \
563 .reg = &(struct arm64_ftr_reg){ \
564 .name = #id, \
565 .ftr_bits = &((table)[0]), \
566 }}
567
568 static const struct __ftr_reg_entry {
569 u32 sys_id;
570 struct arm64_ftr_reg *reg;
571 } arm64_ftr_regs[] = {
572
573 /* Op1 = 0, CRn = 0, CRm = 1 */
574 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
575 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
576 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
577 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
578 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
579 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
580 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
581
582 /* Op1 = 0, CRn = 0, CRm = 2 */
583 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
584 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
585 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
586 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
587 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
588 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
589 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
590 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
591
592 /* Op1 = 0, CRn = 0, CRm = 3 */
593 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
594 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
595 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
596 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
597 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
598 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
599
600 /* Op1 = 0, CRn = 0, CRm = 4 */
601 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
602 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
603 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
604
605 /* Op1 = 0, CRn = 0, CRm = 5 */
606 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
607 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
608
609 /* Op1 = 0, CRn = 0, CRm = 6 */
610 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
611 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
612 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
613
614 /* Op1 = 0, CRn = 0, CRm = 7 */
615 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
616 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
617 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
618
619 /* Op1 = 0, CRn = 1, CRm = 2 */
620 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
621
622 /* Op1 = 3, CRn = 0, CRm = 0 */
623 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
624 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
625
626 /* Op1 = 3, CRn = 14, CRm = 0 */
627 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
628 };
629
search_cmp_ftr_reg(const void * id,const void * regp)630 static int search_cmp_ftr_reg(const void *id, const void *regp)
631 {
632 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
633 }
634
635 /*
636 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
637 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
638 * ascending order of sys_id, we use binary search to find a matching
639 * entry.
640 *
641 * returns - Upon success, matching ftr_reg entry for id.
642 * - NULL on failure. It is upto the caller to decide
643 * the impact of a failure.
644 */
get_arm64_ftr_reg_nowarn(u32 sys_id)645 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
646 {
647 const struct __ftr_reg_entry *ret;
648
649 ret = bsearch((const void *)(unsigned long)sys_id,
650 arm64_ftr_regs,
651 ARRAY_SIZE(arm64_ftr_regs),
652 sizeof(arm64_ftr_regs[0]),
653 search_cmp_ftr_reg);
654 if (ret)
655 return ret->reg;
656 return NULL;
657 }
658
659 /*
660 * get_arm64_ftr_reg - Looks up a feature register entry using
661 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
662 *
663 * returns - Upon success, matching ftr_reg entry for id.
664 * - NULL on failure but with an WARN_ON().
665 */
get_arm64_ftr_reg(u32 sys_id)666 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
667 {
668 struct arm64_ftr_reg *reg;
669
670 reg = get_arm64_ftr_reg_nowarn(sys_id);
671
672 /*
673 * Requesting a non-existent register search is an error. Warn
674 * and let the caller handle it.
675 */
676 WARN_ON(!reg);
677 return reg;
678 }
679
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)680 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
681 s64 ftr_val)
682 {
683 u64 mask = arm64_ftr_mask(ftrp);
684
685 reg &= ~mask;
686 reg |= (ftr_val << ftrp->shift) & mask;
687 return reg;
688 }
689
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)690 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
691 s64 cur)
692 {
693 s64 ret = 0;
694
695 switch (ftrp->type) {
696 case FTR_EXACT:
697 ret = ftrp->safe_val;
698 break;
699 case FTR_LOWER_SAFE:
700 ret = new < cur ? new : cur;
701 break;
702 case FTR_HIGHER_OR_ZERO_SAFE:
703 if (!cur || !new)
704 break;
705 fallthrough;
706 case FTR_HIGHER_SAFE:
707 ret = new > cur ? new : cur;
708 break;
709 default:
710 BUG();
711 }
712
713 return ret;
714 }
715
sort_ftr_regs(void)716 static void __init sort_ftr_regs(void)
717 {
718 unsigned int i;
719
720 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
721 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
722 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
723 unsigned int j = 0;
724
725 /*
726 * Features here must be sorted in descending order with respect
727 * to their shift values and should not overlap with each other.
728 */
729 for (; ftr_bits->width != 0; ftr_bits++, j++) {
730 unsigned int width = ftr_reg->ftr_bits[j].width;
731 unsigned int shift = ftr_reg->ftr_bits[j].shift;
732 unsigned int prev_shift;
733
734 WARN((shift + width) > 64,
735 "%s has invalid feature at shift %d\n",
736 ftr_reg->name, shift);
737
738 /*
739 * Skip the first feature. There is nothing to
740 * compare against for now.
741 */
742 if (j == 0)
743 continue;
744
745 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
746 WARN((shift + width) > prev_shift,
747 "%s has feature overlap at shift %d\n",
748 ftr_reg->name, shift);
749 }
750
751 /*
752 * Skip the first register. There is nothing to
753 * compare against for now.
754 */
755 if (i == 0)
756 continue;
757 /*
758 * Registers here must be sorted in ascending order with respect
759 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
760 * to work correctly.
761 */
762 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
763 }
764 }
765
766 /*
767 * Initialise the CPU feature register from Boot CPU values.
768 * Also initiliases the strict_mask for the register.
769 * Any bits that are not covered by an arm64_ftr_bits entry are considered
770 * RES0 for the system-wide value, and must strictly match.
771 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)772 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
773 {
774 u64 val = 0;
775 u64 strict_mask = ~0x0ULL;
776 u64 user_mask = 0;
777 u64 valid_mask = 0;
778
779 const struct arm64_ftr_bits *ftrp;
780 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
781
782 if (!reg)
783 return;
784
785 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
786 u64 ftr_mask = arm64_ftr_mask(ftrp);
787 s64 ftr_new = arm64_ftr_value(ftrp, new);
788
789 val = arm64_ftr_set_value(ftrp, val, ftr_new);
790
791 valid_mask |= ftr_mask;
792 if (!ftrp->strict)
793 strict_mask &= ~ftr_mask;
794 if (ftrp->visible)
795 user_mask |= ftr_mask;
796 else
797 reg->user_val = arm64_ftr_set_value(ftrp,
798 reg->user_val,
799 ftrp->safe_val);
800 }
801
802 val &= valid_mask;
803
804 reg->sys_val = val;
805 reg->strict_mask = strict_mask;
806 reg->user_mask = user_mask;
807 }
808
809 extern const struct arm64_cpu_capabilities arm64_errata[];
810 static const struct arm64_cpu_capabilities arm64_features[];
811
812 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)813 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
814 {
815 for (; caps->matches; caps++) {
816 if (WARN(caps->capability >= ARM64_NCAPS,
817 "Invalid capability %d\n", caps->capability))
818 continue;
819 if (WARN(cpu_hwcaps_ptrs[caps->capability],
820 "Duplicate entry for capability %d\n",
821 caps->capability))
822 continue;
823 cpu_hwcaps_ptrs[caps->capability] = caps;
824 }
825 }
826
init_cpu_hwcaps_indirect_list(void)827 static void __init init_cpu_hwcaps_indirect_list(void)
828 {
829 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
830 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
831 }
832
833 static void __init setup_boot_cpu_capabilities(void);
834
init_cpu_features(struct cpuinfo_arm64 * info)835 void __init init_cpu_features(struct cpuinfo_arm64 *info)
836 {
837 /* Before we start using the tables, make sure it is sorted */
838 sort_ftr_regs();
839
840 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
841 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
842 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
843 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
844 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
845 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
846 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
847 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
848 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
849 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
850 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
851 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
852 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
853 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
854
855 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
856 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
857 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
858 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
859 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
860 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
861 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
862 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
863 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
864 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
865 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
866 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
867 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
868 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
869 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
870 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
871 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
872 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
873 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
874 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
875 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
876 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
877 }
878
879 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
880 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
881 sve_init_vq_map();
882 }
883
884 /*
885 * Initialize the indirect array of CPU hwcaps capabilities pointers
886 * before we handle the boot CPU below.
887 */
888 init_cpu_hwcaps_indirect_list();
889
890 /*
891 * Detect and enable early CPU capabilities based on the boot CPU,
892 * after we have initialised the CPU feature infrastructure.
893 */
894 setup_boot_cpu_capabilities();
895 }
896
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)897 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
898 {
899 const struct arm64_ftr_bits *ftrp;
900
901 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
902 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
903 s64 ftr_new = arm64_ftr_value(ftrp, new);
904
905 if (ftr_cur == ftr_new)
906 continue;
907 /* Find a safe value */
908 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
909 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
910 }
911
912 }
913
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)914 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
915 {
916 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
917
918 if (!regp)
919 return 0;
920
921 update_cpu_ftr_reg(regp, val);
922 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
923 return 0;
924 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
925 regp->name, boot, cpu, val);
926 return 1;
927 }
928
relax_cpu_ftr_reg(u32 sys_id,int field)929 static void relax_cpu_ftr_reg(u32 sys_id, int field)
930 {
931 const struct arm64_ftr_bits *ftrp;
932 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
933
934 if (!regp)
935 return;
936
937 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
938 if (ftrp->shift == field) {
939 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
940 break;
941 }
942 }
943
944 /* Bogus field? */
945 WARN_ON(!ftrp->width);
946 }
947
update_32bit_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)948 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
949 struct cpuinfo_arm64 *boot)
950 {
951 int taint = 0;
952 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
953
954 /*
955 * If we don't have AArch32 at all then skip the checks entirely
956 * as the register values may be UNKNOWN and we're not going to be
957 * using them for anything.
958 */
959 if (!id_aa64pfr0_32bit_el0(pfr0))
960 return taint;
961
962 /*
963 * If we don't have AArch32 at EL1, then relax the strictness of
964 * EL1-dependent register fields to avoid spurious sanity check fails.
965 */
966 if (!id_aa64pfr0_32bit_el1(pfr0)) {
967 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
968 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
969 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
970 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
971 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
972 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
973 }
974
975 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
976 info->reg_id_dfr0, boot->reg_id_dfr0);
977 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
978 info->reg_id_dfr1, boot->reg_id_dfr1);
979 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
980 info->reg_id_isar0, boot->reg_id_isar0);
981 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
982 info->reg_id_isar1, boot->reg_id_isar1);
983 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
984 info->reg_id_isar2, boot->reg_id_isar2);
985 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
986 info->reg_id_isar3, boot->reg_id_isar3);
987 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
988 info->reg_id_isar4, boot->reg_id_isar4);
989 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
990 info->reg_id_isar5, boot->reg_id_isar5);
991 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
992 info->reg_id_isar6, boot->reg_id_isar6);
993
994 /*
995 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
996 * ACTLR formats could differ across CPUs and therefore would have to
997 * be trapped for virtualization anyway.
998 */
999 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1000 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1001 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1002 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1003 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1004 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1005 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1006 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1007 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1008 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1009 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1010 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1011 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1012 info->reg_id_pfr0, boot->reg_id_pfr0);
1013 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1014 info->reg_id_pfr1, boot->reg_id_pfr1);
1015 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1016 info->reg_id_pfr2, boot->reg_id_pfr2);
1017 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1018 info->reg_mvfr0, boot->reg_mvfr0);
1019 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1020 info->reg_mvfr1, boot->reg_mvfr1);
1021 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1022 info->reg_mvfr2, boot->reg_mvfr2);
1023
1024 return taint;
1025 }
1026
1027 /*
1028 * Update system wide CPU feature registers with the values from a
1029 * non-boot CPU. Also performs SANITY checks to make sure that there
1030 * aren't any insane variations from that of the boot CPU.
1031 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1032 void update_cpu_features(int cpu,
1033 struct cpuinfo_arm64 *info,
1034 struct cpuinfo_arm64 *boot)
1035 {
1036 int taint = 0;
1037
1038 /*
1039 * The kernel can handle differing I-cache policies, but otherwise
1040 * caches should look identical. Userspace JITs will make use of
1041 * *minLine.
1042 */
1043 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1044 info->reg_ctr, boot->reg_ctr);
1045
1046 /*
1047 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1048 * could result in too much or too little memory being zeroed if a
1049 * process is preempted and migrated between CPUs.
1050 */
1051 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1052 info->reg_dczid, boot->reg_dczid);
1053
1054 /* If different, timekeeping will be broken (especially with KVM) */
1055 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1056 info->reg_cntfrq, boot->reg_cntfrq);
1057
1058 /*
1059 * The kernel uses self-hosted debug features and expects CPUs to
1060 * support identical debug features. We presently need CTX_CMPs, WRPs,
1061 * and BRPs to be identical.
1062 * ID_AA64DFR1 is currently RES0.
1063 */
1064 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1065 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1066 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1067 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1068 /*
1069 * Even in big.LITTLE, processors should be identical instruction-set
1070 * wise.
1071 */
1072 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1073 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1074 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1075 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1076 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1077 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1078
1079 /*
1080 * Differing PARange support is fine as long as all peripherals and
1081 * memory are mapped within the minimum PARange of all CPUs.
1082 * Linux should not care about secure memory.
1083 */
1084 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1085 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1086 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1087 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1088 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1089 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1090
1091 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1092 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1093 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1094 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1095
1096 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1097 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1098
1099 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1100 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1101 info->reg_zcr, boot->reg_zcr);
1102
1103 /* Probe vector lengths, unless we already gave up on SVE */
1104 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1105 !system_capabilities_finalized())
1106 sve_update_vq_map();
1107 }
1108
1109 /*
1110 * This relies on a sanitised view of the AArch64 ID registers
1111 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1112 */
1113 taint |= update_32bit_cpu_features(cpu, info, boot);
1114
1115 /*
1116 * Mismatched CPU features are a recipe for disaster. Don't even
1117 * pretend to support them.
1118 */
1119 if (taint) {
1120 pr_warn_once("Unsupported CPU feature variation detected.\n");
1121 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1122 }
1123 }
1124
read_sanitised_ftr_reg(u32 id)1125 u64 read_sanitised_ftr_reg(u32 id)
1126 {
1127 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1128
1129 if (!regp)
1130 return 0;
1131 return regp->sys_val;
1132 }
1133 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1134
1135 #define read_sysreg_case(r) \
1136 case r: return read_sysreg_s(r)
1137
1138 /*
1139 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1140 * Read the system register on the current CPU
1141 */
__read_sysreg_by_encoding(u32 sys_id)1142 static u64 __read_sysreg_by_encoding(u32 sys_id)
1143 {
1144 switch (sys_id) {
1145 read_sysreg_case(SYS_ID_PFR0_EL1);
1146 read_sysreg_case(SYS_ID_PFR1_EL1);
1147 read_sysreg_case(SYS_ID_PFR2_EL1);
1148 read_sysreg_case(SYS_ID_DFR0_EL1);
1149 read_sysreg_case(SYS_ID_DFR1_EL1);
1150 read_sysreg_case(SYS_ID_MMFR0_EL1);
1151 read_sysreg_case(SYS_ID_MMFR1_EL1);
1152 read_sysreg_case(SYS_ID_MMFR2_EL1);
1153 read_sysreg_case(SYS_ID_MMFR3_EL1);
1154 read_sysreg_case(SYS_ID_MMFR4_EL1);
1155 read_sysreg_case(SYS_ID_MMFR5_EL1);
1156 read_sysreg_case(SYS_ID_ISAR0_EL1);
1157 read_sysreg_case(SYS_ID_ISAR1_EL1);
1158 read_sysreg_case(SYS_ID_ISAR2_EL1);
1159 read_sysreg_case(SYS_ID_ISAR3_EL1);
1160 read_sysreg_case(SYS_ID_ISAR4_EL1);
1161 read_sysreg_case(SYS_ID_ISAR5_EL1);
1162 read_sysreg_case(SYS_ID_ISAR6_EL1);
1163 read_sysreg_case(SYS_MVFR0_EL1);
1164 read_sysreg_case(SYS_MVFR1_EL1);
1165 read_sysreg_case(SYS_MVFR2_EL1);
1166
1167 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1168 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1169 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1170 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1171 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1172 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1173 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1174 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1175 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1176 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1177 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1178
1179 read_sysreg_case(SYS_CNTFRQ_EL0);
1180 read_sysreg_case(SYS_CTR_EL0);
1181 read_sysreg_case(SYS_DCZID_EL0);
1182
1183 default:
1184 BUG();
1185 return 0;
1186 }
1187 }
1188
1189 #include <linux/irqchip/arm-gic-v3.h>
1190
1191 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1192 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1193 {
1194 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1195
1196 return val >= entry->min_field_value;
1197 }
1198
1199 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1200 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1201 {
1202 u64 val;
1203
1204 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1205 if (scope == SCOPE_SYSTEM)
1206 val = read_sanitised_ftr_reg(entry->sys_reg);
1207 else
1208 val = __read_sysreg_by_encoding(entry->sys_reg);
1209
1210 return feature_matches(val, entry);
1211 }
1212
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1213 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1214 {
1215 bool has_sre;
1216
1217 if (!has_cpuid_feature(entry, scope))
1218 return false;
1219
1220 has_sre = gic_enable_sre();
1221 if (!has_sre)
1222 pr_warn_once("%s present but disabled by higher exception level\n",
1223 entry->desc);
1224
1225 return has_sre;
1226 }
1227
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)1228 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1229 {
1230 u32 midr = read_cpuid_id();
1231
1232 /* Cavium ThunderX pass 1.x and 2.x */
1233 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1234 MIDR_CPU_VAR_REV(0, 0),
1235 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1236 }
1237
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)1238 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1239 {
1240 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1241
1242 return cpuid_feature_extract_signed_field(pfr0,
1243 ID_AA64PFR0_FP_SHIFT) < 0;
1244 }
1245
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1246 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1247 int scope)
1248 {
1249 u64 ctr;
1250
1251 if (scope == SCOPE_SYSTEM)
1252 ctr = arm64_ftr_reg_ctrel0.sys_val;
1253 else
1254 ctr = read_cpuid_effective_cachetype();
1255
1256 return ctr & BIT(CTR_IDC_SHIFT);
1257 }
1258
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1259 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1260 {
1261 /*
1262 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1263 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1264 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1265 * value.
1266 */
1267 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1268 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1269 }
1270
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1271 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1272 int scope)
1273 {
1274 u64 ctr;
1275
1276 if (scope == SCOPE_SYSTEM)
1277 ctr = arm64_ftr_reg_ctrel0.sys_val;
1278 else
1279 ctr = read_cpuid_cachetype();
1280
1281 return ctr & BIT(CTR_DIC_SHIFT);
1282 }
1283
1284 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1285 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1286 {
1287 /*
1288 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1289 * may share TLB entries with a CPU stuck in the crashed
1290 * kernel.
1291 */
1292 if (is_kdump_kernel())
1293 return false;
1294
1295 return has_cpuid_feature(entry, scope);
1296 }
1297
1298 /*
1299 * This check is triggered during the early boot before the cpufeature
1300 * is initialised. Checking the status on the local CPU allows the boot
1301 * CPU to detect the need for non-global mappings and thus avoiding a
1302 * pagetable re-write after all the CPUs are booted. This check will be
1303 * anyway run on individual CPUs, allowing us to get the consistent
1304 * state once the SMP CPUs are up and thus make the switch to non-global
1305 * mappings if required.
1306 */
kaslr_requires_kpti(void)1307 bool kaslr_requires_kpti(void)
1308 {
1309 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1310 return false;
1311
1312 /*
1313 * E0PD does a similar job to KPTI so can be used instead
1314 * where available.
1315 */
1316 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1317 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1318 if (cpuid_feature_extract_unsigned_field(mmfr2,
1319 ID_AA64MMFR2_E0PD_SHIFT))
1320 return false;
1321 }
1322
1323 /*
1324 * Systems affected by Cavium erratum 24756 are incompatible
1325 * with KPTI.
1326 */
1327 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1328 extern const struct midr_range cavium_erratum_27456_cpus[];
1329
1330 if (is_midr_in_range_list(read_cpuid_id(),
1331 cavium_erratum_27456_cpus))
1332 return false;
1333 }
1334
1335 return kaslr_offset() > 0;
1336 }
1337
1338 static bool __meltdown_safe = true;
1339 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1340
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1341 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1342 int scope)
1343 {
1344 /* List of CPUs that are not vulnerable and don't need KPTI */
1345 static const struct midr_range kpti_safe_list[] = {
1346 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1347 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1348 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1350 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1351 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1352 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1353 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1354 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1355 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1356 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1357 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1358 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1359 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1360 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1361 { /* sentinel */ }
1362 };
1363 char const *str = "kpti command line option";
1364 bool meltdown_safe;
1365
1366 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1367
1368 /* Defer to CPU feature registers */
1369 if (has_cpuid_feature(entry, scope))
1370 meltdown_safe = true;
1371
1372 if (!meltdown_safe)
1373 __meltdown_safe = false;
1374
1375 /*
1376 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1377 * ThunderX leads to apparent I-cache corruption of kernel text, which
1378 * ends as well as you might imagine. Don't even try.
1379 */
1380 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1381 str = "ARM64_WORKAROUND_CAVIUM_27456";
1382 __kpti_forced = -1;
1383 }
1384
1385 /* Useful for KASLR robustness */
1386 if (kaslr_requires_kpti()) {
1387 if (!__kpti_forced) {
1388 str = "KASLR";
1389 __kpti_forced = 1;
1390 }
1391 }
1392
1393 if (cpu_mitigations_off() && !__kpti_forced) {
1394 str = "mitigations=off";
1395 __kpti_forced = -1;
1396 }
1397
1398 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1399 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1400 return false;
1401 }
1402
1403 /* Forced? */
1404 if (__kpti_forced) {
1405 pr_info_once("kernel page table isolation forced %s by %s\n",
1406 __kpti_forced > 0 ? "ON" : "OFF", str);
1407 return __kpti_forced > 0;
1408 }
1409
1410 return !meltdown_safe;
1411 }
1412
1413 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1414 static void __nocfi
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1415 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1416 {
1417 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1418 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1419 kpti_remap_fn *remap_fn;
1420
1421 int cpu = smp_processor_id();
1422
1423 if (__this_cpu_read(this_cpu_vector) == vectors) {
1424 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1425
1426 __this_cpu_write(this_cpu_vector, v);
1427 }
1428
1429 /*
1430 * We don't need to rewrite the page-tables if either we've done
1431 * it already or we have KASLR enabled and therefore have not
1432 * created any global mappings at all.
1433 */
1434 if (arm64_use_ng_mappings)
1435 return;
1436
1437 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1438
1439 cpu_install_idmap();
1440 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1441 cpu_uninstall_idmap();
1442
1443 if (!cpu)
1444 arm64_use_ng_mappings = true;
1445
1446 return;
1447 }
1448 #else
1449 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1450 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1451 {
1452 }
1453 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1454
parse_kpti(char * str)1455 static int __init parse_kpti(char *str)
1456 {
1457 bool enabled;
1458 int ret = strtobool(str, &enabled);
1459
1460 if (ret)
1461 return ret;
1462
1463 __kpti_forced = enabled ? 1 : -1;
1464 return 0;
1465 }
1466 early_param("kpti", parse_kpti);
1467
1468 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1469 static inline void __cpu_enable_hw_dbm(void)
1470 {
1471 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1472
1473 write_sysreg(tcr, tcr_el1);
1474 isb();
1475 local_flush_tlb_all();
1476 }
1477
cpu_has_broken_dbm(void)1478 static bool cpu_has_broken_dbm(void)
1479 {
1480 /* List of CPUs which have broken DBM support. */
1481 static const struct midr_range cpus[] = {
1482 #ifdef CONFIG_ARM64_ERRATUM_1024718
1483 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1484 /* Kryo4xx Silver (rdpe => r1p0) */
1485 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1486 #endif
1487 {},
1488 };
1489
1490 return is_midr_in_range_list(read_cpuid_id(), cpus);
1491 }
1492
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1493 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1494 {
1495 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1496 !cpu_has_broken_dbm();
1497 }
1498
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1499 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1500 {
1501 if (cpu_can_use_dbm(cap))
1502 __cpu_enable_hw_dbm();
1503 }
1504
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1505 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1506 int __unused)
1507 {
1508 static bool detected = false;
1509 /*
1510 * DBM is a non-conflicting feature. i.e, the kernel can safely
1511 * run a mix of CPUs with and without the feature. So, we
1512 * unconditionally enable the capability to allow any late CPU
1513 * to use the feature. We only enable the control bits on the
1514 * CPU, if it actually supports.
1515 *
1516 * We have to make sure we print the "feature" detection only
1517 * when at least one CPU actually uses it. So check if this CPU
1518 * can actually use it and print the message exactly once.
1519 *
1520 * This is safe as all CPUs (including secondary CPUs - due to the
1521 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1522 * goes through the "matches" check exactly once. Also if a CPU
1523 * matches the criteria, it is guaranteed that the CPU will turn
1524 * the DBM on, as the capability is unconditionally enabled.
1525 */
1526 if (!detected && cpu_can_use_dbm(cap)) {
1527 detected = true;
1528 pr_info("detected: Hardware dirty bit management\n");
1529 }
1530
1531 return true;
1532 }
1533
1534 #endif
1535
1536 #ifdef CONFIG_ARM64_AMU_EXTN
1537
1538 /*
1539 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1540 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1541 * information regarding all the events that it supports. When a CPU bit is
1542 * set in the cpumask, the user of this feature can only rely on the presence
1543 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1544 * counters are enabled or access to these counters is enabled by code
1545 * executed at higher exception levels (firmware).
1546 */
1547 static struct cpumask amu_cpus __read_mostly;
1548
cpu_has_amu_feat(int cpu)1549 bool cpu_has_amu_feat(int cpu)
1550 {
1551 return cpumask_test_cpu(cpu, &amu_cpus);
1552 }
1553
1554 /* Initialize the use of AMU counters for frequency invariance */
1555 extern void init_cpu_freq_invariance_counters(void);
1556
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1557 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1558 {
1559 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1560 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1561 smp_processor_id());
1562 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1563
1564 /* 0 reference values signal broken/disabled counters */
1565 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1566 init_cpu_freq_invariance_counters();
1567 }
1568 }
1569
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1570 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1571 int __unused)
1572 {
1573 /*
1574 * The AMU extension is a non-conflicting feature: the kernel can
1575 * safely run a mix of CPUs with and without support for the
1576 * activity monitors extension. Therefore, unconditionally enable
1577 * the capability to allow any late CPU to use the feature.
1578 *
1579 * With this feature unconditionally enabled, the cpu_enable
1580 * function will be called for all CPUs that match the criteria,
1581 * including secondary and hotplugged, marking this feature as
1582 * present on that respective CPU. The enable function will also
1583 * print a detection message.
1584 */
1585
1586 return true;
1587 }
1588 #endif
1589
1590 #ifdef CONFIG_ARM64_VHE
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1591 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1592 {
1593 return is_kernel_in_hyp_mode();
1594 }
1595
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1596 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1597 {
1598 /*
1599 * Copy register values that aren't redirected by hardware.
1600 *
1601 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1602 * this value to tpidr_el2 before we patch the code. Once we've done
1603 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1604 * do anything here.
1605 */
1606 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1607 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1608 }
1609 #endif
1610
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1611 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1612 {
1613 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1614
1615 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1616 WARN_ON(val & (7 << 27 | 7 << 21));
1617 }
1618
1619 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1620 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1621 {
1622 /*
1623 * We modify PSTATE. This won't work from irq context as the PSTATE
1624 * is discarded once we return from the exception.
1625 */
1626 WARN_ON_ONCE(in_interrupt());
1627
1628 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1629 asm(SET_PSTATE_PAN(1));
1630 }
1631 #endif /* CONFIG_ARM64_PAN */
1632
1633 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1634 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1635 {
1636 /* Firmware may have left a deferred SError in this register. */
1637 write_sysreg_s(0, SYS_DISR_EL1);
1638 }
1639 #endif /* CONFIG_ARM64_RAS_EXTN */
1640
1641 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)1642 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1643 {
1644 int boot_val, sec_val;
1645
1646 /* We don't expect to be called with SCOPE_SYSTEM */
1647 WARN_ON(scope == SCOPE_SYSTEM);
1648 /*
1649 * The ptr-auth feature levels are not intercompatible with lower
1650 * levels. Hence we must match ptr-auth feature level of the secondary
1651 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1652 * from the sanitised register whereas direct register read is done for
1653 * the secondary CPUs.
1654 * The sanitised feature state is guaranteed to match that of the
1655 * boot CPU as a mismatched secondary CPU is parked before it gets
1656 * a chance to update the state, with the capability.
1657 */
1658 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1659 entry->field_pos, entry->sign);
1660 if (scope & SCOPE_BOOT_CPU)
1661 return boot_val >= entry->min_field_value;
1662 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1663 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1664 entry->field_pos, entry->sign);
1665 return sec_val == boot_val;
1666 }
1667
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)1668 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1669 int scope)
1670 {
1671 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1672 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1673 }
1674
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)1675 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1676 int __unused)
1677 {
1678 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1679 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1680 }
1681 #endif /* CONFIG_ARM64_PTR_AUTH */
1682
1683 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)1684 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1685 {
1686 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1687 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1688 }
1689 #endif /* CONFIG_ARM64_E0PD */
1690
1691 #ifdef CONFIG_ARM64_PSEUDO_NMI
1692 static bool enable_pseudo_nmi;
1693
early_enable_pseudo_nmi(char * p)1694 static int __init early_enable_pseudo_nmi(char *p)
1695 {
1696 return strtobool(p, &enable_pseudo_nmi);
1697 }
1698 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1699
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1700 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1701 int scope)
1702 {
1703 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1704 }
1705 #endif
1706
1707 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)1708 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1709 {
1710 /*
1711 * Use of X16/X17 for tail-calls and trampolines that jump to
1712 * function entry points using BR is a requirement for
1713 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1714 * So, be strict and forbid other BRs using other registers to
1715 * jump onto a PACIxSP instruction:
1716 */
1717 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1718 isb();
1719 }
1720 #endif /* CONFIG_ARM64_BTI */
1721
1722 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)1723 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1724 {
1725 /*
1726 * Clear the tags in the zero page. This needs to be done via the
1727 * linear map which has the Tagged attribute.
1728 */
1729 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1730 mte_clear_page_tags(lm_alias(empty_zero_page));
1731 }
1732 #endif /* CONFIG_ARM64_MTE */
1733
elf_hwcap_fixup(void)1734 static void elf_hwcap_fixup(void)
1735 {
1736 #ifdef CONFIG_ARM64_ERRATUM_1742098
1737 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1738 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1739 #endif /* ARM64_ERRATUM_1742098 */
1740 }
1741
1742 /* Internal helper functions to match cpu capability type */
1743 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)1744 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1745 {
1746 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1747 }
1748
1749 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)1750 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1751 {
1752 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1753 }
1754
1755 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)1756 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1757 {
1758 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1759 }
1760
1761 static const struct arm64_cpu_capabilities arm64_features[] = {
1762 {
1763 .desc = "GIC system register CPU interface",
1764 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1765 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1766 .matches = has_useable_gicv3_cpuif,
1767 .sys_reg = SYS_ID_AA64PFR0_EL1,
1768 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1769 .sign = FTR_UNSIGNED,
1770 .min_field_value = 1,
1771 },
1772 #ifdef CONFIG_ARM64_PAN
1773 {
1774 .desc = "Privileged Access Never",
1775 .capability = ARM64_HAS_PAN,
1776 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1777 .matches = has_cpuid_feature,
1778 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1779 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1780 .sign = FTR_UNSIGNED,
1781 .min_field_value = 1,
1782 .cpu_enable = cpu_enable_pan,
1783 },
1784 #endif /* CONFIG_ARM64_PAN */
1785 #ifdef CONFIG_ARM64_LSE_ATOMICS
1786 {
1787 .desc = "LSE atomic instructions",
1788 .capability = ARM64_HAS_LSE_ATOMICS,
1789 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1790 .matches = has_cpuid_feature,
1791 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1792 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1793 .sign = FTR_UNSIGNED,
1794 .min_field_value = 2,
1795 },
1796 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1797 {
1798 .desc = "Software prefetching using PRFM",
1799 .capability = ARM64_HAS_NO_HW_PREFETCH,
1800 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1801 .matches = has_no_hw_prefetch,
1802 },
1803 #ifdef CONFIG_ARM64_UAO
1804 {
1805 .desc = "User Access Override",
1806 .capability = ARM64_HAS_UAO,
1807 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1808 .matches = has_cpuid_feature,
1809 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1810 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1811 .min_field_value = 1,
1812 /*
1813 * We rely on stop_machine() calling uao_thread_switch() to set
1814 * UAO immediately after patching.
1815 */
1816 },
1817 #endif /* CONFIG_ARM64_UAO */
1818 #ifdef CONFIG_ARM64_PAN
1819 {
1820 .capability = ARM64_ALT_PAN_NOT_UAO,
1821 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1822 .matches = cpufeature_pan_not_uao,
1823 },
1824 #endif /* CONFIG_ARM64_PAN */
1825 #ifdef CONFIG_ARM64_VHE
1826 {
1827 .desc = "Virtualization Host Extensions",
1828 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1829 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1830 .matches = runs_at_el2,
1831 .cpu_enable = cpu_copy_el2regs,
1832 },
1833 #endif /* CONFIG_ARM64_VHE */
1834 {
1835 .desc = "32-bit EL0 Support",
1836 .capability = ARM64_HAS_32BIT_EL0,
1837 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1838 .matches = has_cpuid_feature,
1839 .sys_reg = SYS_ID_AA64PFR0_EL1,
1840 .sign = FTR_UNSIGNED,
1841 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1842 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1843 },
1844 #ifdef CONFIG_KVM
1845 {
1846 .desc = "32-bit EL1 Support",
1847 .capability = ARM64_HAS_32BIT_EL1,
1848 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1849 .matches = has_cpuid_feature,
1850 .sys_reg = SYS_ID_AA64PFR0_EL1,
1851 .sign = FTR_UNSIGNED,
1852 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1853 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1854 },
1855 #endif
1856 {
1857 .desc = "Kernel page table isolation (KPTI)",
1858 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1859 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1860 /*
1861 * The ID feature fields below are used to indicate that
1862 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1863 * more details.
1864 */
1865 .sys_reg = SYS_ID_AA64PFR0_EL1,
1866 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1867 .min_field_value = 1,
1868 .matches = unmap_kernel_at_el0,
1869 .cpu_enable = kpti_install_ng_mappings,
1870 },
1871 {
1872 /* FP/SIMD is not implemented */
1873 .capability = ARM64_HAS_NO_FPSIMD,
1874 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1875 .min_field_value = 0,
1876 .matches = has_no_fpsimd,
1877 },
1878 #ifdef CONFIG_ARM64_PMEM
1879 {
1880 .desc = "Data cache clean to Point of Persistence",
1881 .capability = ARM64_HAS_DCPOP,
1882 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1883 .matches = has_cpuid_feature,
1884 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1885 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1886 .min_field_value = 1,
1887 },
1888 {
1889 .desc = "Data cache clean to Point of Deep Persistence",
1890 .capability = ARM64_HAS_DCPODP,
1891 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1892 .matches = has_cpuid_feature,
1893 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1894 .sign = FTR_UNSIGNED,
1895 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1896 .min_field_value = 2,
1897 },
1898 #endif
1899 #ifdef CONFIG_ARM64_SVE
1900 {
1901 .desc = "Scalable Vector Extension",
1902 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1903 .capability = ARM64_SVE,
1904 .sys_reg = SYS_ID_AA64PFR0_EL1,
1905 .sign = FTR_UNSIGNED,
1906 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1907 .min_field_value = ID_AA64PFR0_SVE,
1908 .matches = has_cpuid_feature,
1909 .cpu_enable = sve_kernel_enable,
1910 },
1911 #endif /* CONFIG_ARM64_SVE */
1912 #ifdef CONFIG_ARM64_RAS_EXTN
1913 {
1914 .desc = "RAS Extension Support",
1915 .capability = ARM64_HAS_RAS_EXTN,
1916 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1917 .matches = has_cpuid_feature,
1918 .sys_reg = SYS_ID_AA64PFR0_EL1,
1919 .sign = FTR_UNSIGNED,
1920 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1921 .min_field_value = ID_AA64PFR0_RAS_V1,
1922 .cpu_enable = cpu_clear_disr,
1923 },
1924 #endif /* CONFIG_ARM64_RAS_EXTN */
1925 #ifdef CONFIG_ARM64_AMU_EXTN
1926 {
1927 /*
1928 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1929 * Therefore, don't provide .desc as we don't want the detection
1930 * message to be shown until at least one CPU is detected to
1931 * support the feature.
1932 */
1933 .capability = ARM64_HAS_AMU_EXTN,
1934 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1935 .matches = has_amu,
1936 .sys_reg = SYS_ID_AA64PFR0_EL1,
1937 .sign = FTR_UNSIGNED,
1938 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1939 .min_field_value = ID_AA64PFR0_AMU,
1940 .cpu_enable = cpu_amu_enable,
1941 },
1942 #endif /* CONFIG_ARM64_AMU_EXTN */
1943 {
1944 .desc = "Data cache clean to the PoU not required for I/D coherence",
1945 .capability = ARM64_HAS_CACHE_IDC,
1946 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1947 .matches = has_cache_idc,
1948 .cpu_enable = cpu_emulate_effective_ctr,
1949 },
1950 {
1951 .desc = "Instruction cache invalidation not required for I/D coherence",
1952 .capability = ARM64_HAS_CACHE_DIC,
1953 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1954 .matches = has_cache_dic,
1955 },
1956 {
1957 .desc = "Stage-2 Force Write-Back",
1958 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1959 .capability = ARM64_HAS_STAGE2_FWB,
1960 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1961 .sign = FTR_UNSIGNED,
1962 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1963 .min_field_value = 1,
1964 .matches = has_cpuid_feature,
1965 .cpu_enable = cpu_has_fwb,
1966 },
1967 {
1968 .desc = "ARMv8.4 Translation Table Level",
1969 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1970 .capability = ARM64_HAS_ARMv8_4_TTL,
1971 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1972 .sign = FTR_UNSIGNED,
1973 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
1974 .min_field_value = 1,
1975 .matches = has_cpuid_feature,
1976 },
1977 {
1978 .desc = "TLB range maintenance instructions",
1979 .capability = ARM64_HAS_TLB_RANGE,
1980 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1981 .matches = has_cpuid_feature,
1982 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1983 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
1984 .sign = FTR_UNSIGNED,
1985 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
1986 },
1987 #ifdef CONFIG_ARM64_HW_AFDBM
1988 {
1989 /*
1990 * Since we turn this on always, we don't want the user to
1991 * think that the feature is available when it may not be.
1992 * So hide the description.
1993 *
1994 * .desc = "Hardware pagetable Dirty Bit Management",
1995 *
1996 */
1997 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1998 .capability = ARM64_HW_DBM,
1999 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2000 .sign = FTR_UNSIGNED,
2001 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2002 .min_field_value = 2,
2003 .matches = has_hw_dbm,
2004 .cpu_enable = cpu_enable_hw_dbm,
2005 },
2006 #endif
2007 {
2008 .desc = "CRC32 instructions",
2009 .capability = ARM64_HAS_CRC32,
2010 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2011 .matches = has_cpuid_feature,
2012 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2013 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2014 .min_field_value = 1,
2015 },
2016 {
2017 .desc = "Speculative Store Bypassing Safe (SSBS)",
2018 .capability = ARM64_SSBS,
2019 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2020 .matches = has_cpuid_feature,
2021 .sys_reg = SYS_ID_AA64PFR1_EL1,
2022 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2023 .sign = FTR_UNSIGNED,
2024 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2025 },
2026 #ifdef CONFIG_ARM64_CNP
2027 {
2028 .desc = "Common not Private translations",
2029 .capability = ARM64_HAS_CNP,
2030 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2031 .matches = has_useable_cnp,
2032 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2033 .sign = FTR_UNSIGNED,
2034 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2035 .min_field_value = 1,
2036 .cpu_enable = cpu_enable_cnp,
2037 },
2038 #endif
2039 {
2040 .desc = "Speculation barrier (SB)",
2041 .capability = ARM64_HAS_SB,
2042 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2043 .matches = has_cpuid_feature,
2044 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2045 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2046 .sign = FTR_UNSIGNED,
2047 .min_field_value = 1,
2048 },
2049 #ifdef CONFIG_ARM64_PTR_AUTH
2050 {
2051 .desc = "Address authentication (architected algorithm)",
2052 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2053 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2054 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2055 .sign = FTR_UNSIGNED,
2056 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2057 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2058 .matches = has_address_auth_cpucap,
2059 },
2060 {
2061 .desc = "Address authentication (IMP DEF algorithm)",
2062 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2063 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2064 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2065 .sign = FTR_UNSIGNED,
2066 .field_pos = ID_AA64ISAR1_API_SHIFT,
2067 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2068 .matches = has_address_auth_cpucap,
2069 },
2070 {
2071 .capability = ARM64_HAS_ADDRESS_AUTH,
2072 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2073 .matches = has_address_auth_metacap,
2074 },
2075 {
2076 .desc = "Generic authentication (architected algorithm)",
2077 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2078 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2079 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2080 .sign = FTR_UNSIGNED,
2081 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2082 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2083 .matches = has_cpuid_feature,
2084 },
2085 {
2086 .desc = "Generic authentication (IMP DEF algorithm)",
2087 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2088 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2089 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2090 .sign = FTR_UNSIGNED,
2091 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2092 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2093 .matches = has_cpuid_feature,
2094 },
2095 {
2096 .capability = ARM64_HAS_GENERIC_AUTH,
2097 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2098 .matches = has_generic_auth,
2099 },
2100 #endif /* CONFIG_ARM64_PTR_AUTH */
2101 #ifdef CONFIG_ARM64_PSEUDO_NMI
2102 {
2103 /*
2104 * Depends on having GICv3
2105 */
2106 .desc = "IRQ priority masking",
2107 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2108 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2109 .matches = can_use_gic_priorities,
2110 .sys_reg = SYS_ID_AA64PFR0_EL1,
2111 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2112 .sign = FTR_UNSIGNED,
2113 .min_field_value = 1,
2114 },
2115 #endif
2116 #ifdef CONFIG_ARM64_E0PD
2117 {
2118 .desc = "E0PD",
2119 .capability = ARM64_HAS_E0PD,
2120 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2121 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2122 .sign = FTR_UNSIGNED,
2123 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2124 .matches = has_cpuid_feature,
2125 .min_field_value = 1,
2126 .cpu_enable = cpu_enable_e0pd,
2127 },
2128 #endif
2129 #ifdef CONFIG_ARCH_RANDOM
2130 {
2131 .desc = "Random Number Generator",
2132 .capability = ARM64_HAS_RNG,
2133 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2134 .matches = has_cpuid_feature,
2135 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2136 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2137 .sign = FTR_UNSIGNED,
2138 .min_field_value = 1,
2139 },
2140 #endif
2141 #ifdef CONFIG_ARM64_BTI
2142 {
2143 .desc = "Branch Target Identification",
2144 .capability = ARM64_BTI,
2145 #ifdef CONFIG_ARM64_BTI_KERNEL
2146 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2147 #else
2148 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2149 #endif
2150 .matches = has_cpuid_feature,
2151 .cpu_enable = bti_enable,
2152 .sys_reg = SYS_ID_AA64PFR1_EL1,
2153 .field_pos = ID_AA64PFR1_BT_SHIFT,
2154 .min_field_value = ID_AA64PFR1_BT_BTI,
2155 .sign = FTR_UNSIGNED,
2156 },
2157 #endif
2158 #ifdef CONFIG_ARM64_MTE
2159 {
2160 .desc = "Memory Tagging Extension",
2161 .capability = ARM64_MTE,
2162 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2163 .matches = has_cpuid_feature,
2164 .sys_reg = SYS_ID_AA64PFR1_EL1,
2165 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2166 .min_field_value = ID_AA64PFR1_MTE,
2167 .sign = FTR_UNSIGNED,
2168 .cpu_enable = cpu_enable_mte,
2169 },
2170 #endif /* CONFIG_ARM64_MTE */
2171 {},
2172 };
2173
2174 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2175 .matches = has_cpuid_feature, \
2176 .sys_reg = reg, \
2177 .field_pos = field, \
2178 .sign = s, \
2179 .min_field_value = min_value,
2180
2181 #define __HWCAP_CAP(name, cap_type, cap) \
2182 .desc = name, \
2183 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2184 .hwcap_type = cap_type, \
2185 .hwcap = cap, \
2186
2187 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2188 { \
2189 __HWCAP_CAP(#cap, cap_type, cap) \
2190 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2191 }
2192
2193 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2194 { \
2195 __HWCAP_CAP(#cap, cap_type, cap) \
2196 .matches = cpucap_multi_entry_cap_matches, \
2197 .match_list = list, \
2198 }
2199
2200 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2201 { \
2202 __HWCAP_CAP(#cap, cap_type, cap) \
2203 .matches = match, \
2204 }
2205
2206 #ifdef CONFIG_ARM64_PTR_AUTH
2207 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2208 {
2209 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2210 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2211 },
2212 {
2213 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2214 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2215 },
2216 {},
2217 };
2218
2219 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2220 {
2221 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2222 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2223 },
2224 {
2225 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2226 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2227 },
2228 {},
2229 };
2230 #endif
2231
2232 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2233 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2234 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2235 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2236 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2237 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2238 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2239 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2240 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2241 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2242 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2243 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2244 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2245 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2246 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2247 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2248 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2249 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2250 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2251 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2252 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2253 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2254 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2255 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2256 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2257 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2258 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2259 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2260 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2261 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2262 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2263 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2264 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2265 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2266 #ifdef CONFIG_ARM64_SVE
2267 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2268 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2269 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2270 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2271 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2272 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2273 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2274 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2275 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2276 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2277 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2278 #endif
2279 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2280 #ifdef CONFIG_ARM64_BTI
2281 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2282 #endif
2283 #ifdef CONFIG_ARM64_PTR_AUTH
2284 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2285 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2286 #endif
2287 #ifdef CONFIG_ARM64_MTE
2288 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2289 #endif /* CONFIG_ARM64_MTE */
2290 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2291 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2292 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2293 {},
2294 };
2295
2296 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)2297 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2298 {
2299 /*
2300 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2301 * in line with that of arm32 as in vfp_init(). We make sure that the
2302 * check is future proof, by making sure value is non-zero.
2303 */
2304 u32 mvfr1;
2305
2306 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2307 if (scope == SCOPE_SYSTEM)
2308 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2309 else
2310 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2311
2312 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2313 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2314 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2315 }
2316 #endif
2317
2318 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2319 #ifdef CONFIG_COMPAT
2320 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2321 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2322 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2323 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2324 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2325 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2326 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2327 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2328 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2329 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2330 #endif
2331 {},
2332 };
2333
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)2334 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2335 {
2336 switch (cap->hwcap_type) {
2337 case CAP_HWCAP:
2338 cpu_set_feature(cap->hwcap);
2339 break;
2340 #ifdef CONFIG_COMPAT
2341 case CAP_COMPAT_HWCAP:
2342 compat_elf_hwcap |= (u32)cap->hwcap;
2343 break;
2344 case CAP_COMPAT_HWCAP2:
2345 compat_elf_hwcap2 |= (u32)cap->hwcap;
2346 break;
2347 #endif
2348 default:
2349 WARN_ON(1);
2350 break;
2351 }
2352 }
2353
2354 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)2355 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2356 {
2357 bool rc;
2358
2359 switch (cap->hwcap_type) {
2360 case CAP_HWCAP:
2361 rc = cpu_have_feature(cap->hwcap);
2362 break;
2363 #ifdef CONFIG_COMPAT
2364 case CAP_COMPAT_HWCAP:
2365 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2366 break;
2367 case CAP_COMPAT_HWCAP2:
2368 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2369 break;
2370 #endif
2371 default:
2372 WARN_ON(1);
2373 rc = false;
2374 }
2375
2376 return rc;
2377 }
2378
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)2379 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2380 {
2381 /* We support emulation of accesses to CPU ID feature registers */
2382 cpu_set_named_feature(CPUID);
2383 for (; hwcaps->matches; hwcaps++)
2384 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2385 cap_set_elf_hwcap(hwcaps);
2386 }
2387
update_cpu_capabilities(u16 scope_mask)2388 static void update_cpu_capabilities(u16 scope_mask)
2389 {
2390 int i;
2391 const struct arm64_cpu_capabilities *caps;
2392
2393 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2394 for (i = 0; i < ARM64_NCAPS; i++) {
2395 caps = cpu_hwcaps_ptrs[i];
2396 if (!caps || !(caps->type & scope_mask) ||
2397 cpus_have_cap(caps->capability) ||
2398 !caps->matches(caps, cpucap_default_scope(caps)))
2399 continue;
2400
2401 if (caps->desc)
2402 pr_info("detected: %s\n", caps->desc);
2403 cpus_set_cap(caps->capability);
2404
2405 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2406 set_bit(caps->capability, boot_capabilities);
2407 }
2408 }
2409
2410 /*
2411 * Enable all the available capabilities on this CPU. The capabilities
2412 * with BOOT_CPU scope are handled separately and hence skipped here.
2413 */
cpu_enable_non_boot_scope_capabilities(void * __unused)2414 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2415 {
2416 int i;
2417 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2418
2419 for_each_available_cap(i) {
2420 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2421
2422 if (WARN_ON(!cap))
2423 continue;
2424
2425 if (!(cap->type & non_boot_scope))
2426 continue;
2427
2428 if (cap->cpu_enable)
2429 cap->cpu_enable(cap);
2430 }
2431 return 0;
2432 }
2433
2434 /*
2435 * Run through the enabled capabilities and enable() it on all active
2436 * CPUs
2437 */
enable_cpu_capabilities(u16 scope_mask)2438 static void __init enable_cpu_capabilities(u16 scope_mask)
2439 {
2440 int i;
2441 const struct arm64_cpu_capabilities *caps;
2442 bool boot_scope;
2443
2444 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2445 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2446
2447 for (i = 0; i < ARM64_NCAPS; i++) {
2448 unsigned int num;
2449
2450 caps = cpu_hwcaps_ptrs[i];
2451 if (!caps || !(caps->type & scope_mask))
2452 continue;
2453 num = caps->capability;
2454 if (!cpus_have_cap(num))
2455 continue;
2456
2457 /* Ensure cpus_have_const_cap(num) works */
2458 static_branch_enable(&cpu_hwcap_keys[num]);
2459
2460 if (boot_scope && caps->cpu_enable)
2461 /*
2462 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2463 * before any secondary CPU boots. Thus, each secondary
2464 * will enable the capability as appropriate via
2465 * check_local_cpu_capabilities(). The only exception is
2466 * the boot CPU, for which the capability must be
2467 * enabled here. This approach avoids costly
2468 * stop_machine() calls for this case.
2469 */
2470 caps->cpu_enable(caps);
2471 }
2472
2473 /*
2474 * For all non-boot scope capabilities, use stop_machine()
2475 * as it schedules the work allowing us to modify PSTATE,
2476 * instead of on_each_cpu() which uses an IPI, giving us a
2477 * PSTATE that disappears when we return.
2478 */
2479 if (!boot_scope)
2480 stop_machine(cpu_enable_non_boot_scope_capabilities,
2481 NULL, cpu_online_mask);
2482 }
2483
2484 /*
2485 * Run through the list of capabilities to check for conflicts.
2486 * If the system has already detected a capability, take necessary
2487 * action on this CPU.
2488 */
verify_local_cpu_caps(u16 scope_mask)2489 static void verify_local_cpu_caps(u16 scope_mask)
2490 {
2491 int i;
2492 bool cpu_has_cap, system_has_cap;
2493 const struct arm64_cpu_capabilities *caps;
2494
2495 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2496
2497 for (i = 0; i < ARM64_NCAPS; i++) {
2498 caps = cpu_hwcaps_ptrs[i];
2499 if (!caps || !(caps->type & scope_mask))
2500 continue;
2501
2502 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2503 system_has_cap = cpus_have_cap(caps->capability);
2504
2505 if (system_has_cap) {
2506 /*
2507 * Check if the new CPU misses an advertised feature,
2508 * which is not safe to miss.
2509 */
2510 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2511 break;
2512 /*
2513 * We have to issue cpu_enable() irrespective of
2514 * whether the CPU has it or not, as it is enabeld
2515 * system wide. It is upto the call back to take
2516 * appropriate action on this CPU.
2517 */
2518 if (caps->cpu_enable)
2519 caps->cpu_enable(caps);
2520 } else {
2521 /*
2522 * Check if the CPU has this capability if it isn't
2523 * safe to have when the system doesn't.
2524 */
2525 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2526 break;
2527 }
2528 }
2529
2530 if (i < ARM64_NCAPS) {
2531 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2532 smp_processor_id(), caps->capability,
2533 caps->desc, system_has_cap, cpu_has_cap);
2534
2535 if (cpucap_panic_on_conflict(caps))
2536 cpu_panic_kernel();
2537 else
2538 cpu_die_early();
2539 }
2540 }
2541
2542 /*
2543 * Check for CPU features that are used in early boot
2544 * based on the Boot CPU value.
2545 */
check_early_cpu_features(void)2546 static void check_early_cpu_features(void)
2547 {
2548 verify_cpu_asid_bits();
2549
2550 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2551 }
2552
2553 static void
verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)2554 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2555 {
2556
2557 for (; caps->matches; caps++)
2558 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2559 pr_crit("CPU%d: missing HWCAP: %s\n",
2560 smp_processor_id(), caps->desc);
2561 cpu_die_early();
2562 }
2563 }
2564
verify_sve_features(void)2565 static void verify_sve_features(void)
2566 {
2567 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2568 u64 zcr = read_zcr_features();
2569
2570 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2571 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2572
2573 if (len < safe_len || sve_verify_vq_map()) {
2574 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2575 smp_processor_id());
2576 cpu_die_early();
2577 }
2578
2579 /* Add checks on other ZCR bits here if necessary */
2580 }
2581
verify_hyp_capabilities(void)2582 static void verify_hyp_capabilities(void)
2583 {
2584 u64 safe_mmfr1, mmfr0, mmfr1;
2585 int parange, ipa_max;
2586 unsigned int safe_vmid_bits, vmid_bits;
2587
2588 if (!IS_ENABLED(CONFIG_KVM))
2589 return;
2590
2591 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2592 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2593 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2594
2595 /* Verify VMID bits */
2596 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2597 vmid_bits = get_vmid_bits(mmfr1);
2598 if (vmid_bits < safe_vmid_bits) {
2599 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2600 cpu_die_early();
2601 }
2602
2603 /* Verify IPA range */
2604 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2605 ID_AA64MMFR0_PARANGE_SHIFT);
2606 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2607 if (ipa_max < get_kvm_ipa_limit()) {
2608 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2609 cpu_die_early();
2610 }
2611 }
2612
2613 /*
2614 * Run through the enabled system capabilities and enable() it on this CPU.
2615 * The capabilities were decided based on the available CPUs at the boot time.
2616 * Any new CPU should match the system wide status of the capability. If the
2617 * new CPU doesn't have a capability which the system now has enabled, we
2618 * cannot do anything to fix it up and could cause unexpected failures. So
2619 * we park the CPU.
2620 */
verify_local_cpu_capabilities(void)2621 static void verify_local_cpu_capabilities(void)
2622 {
2623 /*
2624 * The capabilities with SCOPE_BOOT_CPU are checked from
2625 * check_early_cpu_features(), as they need to be verified
2626 * on all secondary CPUs.
2627 */
2628 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2629
2630 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2631
2632 if (system_supports_32bit_el0())
2633 verify_local_elf_hwcaps(compat_elf_hwcaps);
2634
2635 if (system_supports_sve())
2636 verify_sve_features();
2637
2638 if (is_hyp_mode_available())
2639 verify_hyp_capabilities();
2640 }
2641
check_local_cpu_capabilities(void)2642 void check_local_cpu_capabilities(void)
2643 {
2644 /*
2645 * All secondary CPUs should conform to the early CPU features
2646 * in use by the kernel based on boot CPU.
2647 */
2648 check_early_cpu_features();
2649
2650 /*
2651 * If we haven't finalised the system capabilities, this CPU gets
2652 * a chance to update the errata work arounds and local features.
2653 * Otherwise, this CPU should verify that it has all the system
2654 * advertised capabilities.
2655 */
2656 if (!system_capabilities_finalized())
2657 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2658 else
2659 verify_local_cpu_capabilities();
2660 }
2661
setup_boot_cpu_capabilities(void)2662 static void __init setup_boot_cpu_capabilities(void)
2663 {
2664 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2665 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2666 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2667 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2668 }
2669
this_cpu_has_cap(unsigned int n)2670 bool this_cpu_has_cap(unsigned int n)
2671 {
2672 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2673 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2674
2675 if (cap)
2676 return cap->matches(cap, SCOPE_LOCAL_CPU);
2677 }
2678
2679 return false;
2680 }
2681
2682 /*
2683 * This helper function is used in a narrow window when,
2684 * - The system wide safe registers are set with all the SMP CPUs and,
2685 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2686 * In all other cases cpus_have_{const_}cap() should be used.
2687 */
__system_matches_cap(unsigned int n)2688 static bool __system_matches_cap(unsigned int n)
2689 {
2690 if (n < ARM64_NCAPS) {
2691 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2692
2693 if (cap)
2694 return cap->matches(cap, SCOPE_SYSTEM);
2695 }
2696 return false;
2697 }
2698
cpu_set_feature(unsigned int num)2699 void cpu_set_feature(unsigned int num)
2700 {
2701 WARN_ON(num >= MAX_CPU_FEATURES);
2702 elf_hwcap |= BIT(num);
2703 }
2704 EXPORT_SYMBOL_GPL(cpu_set_feature);
2705
cpu_have_feature(unsigned int num)2706 bool cpu_have_feature(unsigned int num)
2707 {
2708 WARN_ON(num >= MAX_CPU_FEATURES);
2709 return elf_hwcap & BIT(num);
2710 }
2711 EXPORT_SYMBOL_GPL(cpu_have_feature);
2712
cpu_get_elf_hwcap(void)2713 unsigned long cpu_get_elf_hwcap(void)
2714 {
2715 /*
2716 * We currently only populate the first 32 bits of AT_HWCAP. Please
2717 * note that for userspace compatibility we guarantee that bits 62
2718 * and 63 will always be returned as 0.
2719 */
2720 return lower_32_bits(elf_hwcap);
2721 }
2722
cpu_get_elf_hwcap2(void)2723 unsigned long cpu_get_elf_hwcap2(void)
2724 {
2725 return upper_32_bits(elf_hwcap);
2726 }
2727
setup_system_capabilities(void)2728 static void __init setup_system_capabilities(void)
2729 {
2730 /*
2731 * We have finalised the system-wide safe feature
2732 * registers, finalise the capabilities that depend
2733 * on it. Also enable all the available capabilities,
2734 * that are not enabled already.
2735 */
2736 update_cpu_capabilities(SCOPE_SYSTEM);
2737 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2738 }
2739
setup_cpu_features(void)2740 void __init setup_cpu_features(void)
2741 {
2742 u32 cwg;
2743
2744 setup_system_capabilities();
2745 setup_elf_hwcaps(arm64_elf_hwcaps);
2746
2747 if (system_supports_32bit_el0()) {
2748 setup_elf_hwcaps(compat_elf_hwcaps);
2749 elf_hwcap_fixup();
2750 }
2751
2752 if (system_uses_ttbr0_pan())
2753 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2754
2755 sve_setup();
2756 minsigstksz_setup();
2757
2758 /* Advertise that we have computed the system capabilities */
2759 finalize_system_capabilities();
2760
2761 /*
2762 * Check for sane CTR_EL0.CWG value.
2763 */
2764 cwg = cache_type_cwg();
2765 if (!cwg)
2766 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2767 ARCH_DMA_MINALIGN);
2768 }
2769
2770 static bool __maybe_unused
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities * entry,int __unused)2771 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2772 {
2773 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
2774 }
2775
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)2776 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2777 {
2778 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2779 }
2780
2781 /*
2782 * We emulate only the following system register space.
2783 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2784 * See Table C5-6 System instruction encodings for System register accesses,
2785 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2786 */
is_emulated(u32 id)2787 static inline bool __attribute_const__ is_emulated(u32 id)
2788 {
2789 return (sys_reg_Op0(id) == 0x3 &&
2790 sys_reg_CRn(id) == 0x0 &&
2791 sys_reg_Op1(id) == 0x0 &&
2792 (sys_reg_CRm(id) == 0 ||
2793 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2794 }
2795
2796 /*
2797 * With CRm == 0, reg should be one of :
2798 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2799 */
emulate_id_reg(u32 id,u64 * valp)2800 static inline int emulate_id_reg(u32 id, u64 *valp)
2801 {
2802 switch (id) {
2803 case SYS_MIDR_EL1:
2804 *valp = read_cpuid_id();
2805 break;
2806 case SYS_MPIDR_EL1:
2807 *valp = SYS_MPIDR_SAFE_VAL;
2808 break;
2809 case SYS_REVIDR_EL1:
2810 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2811 *valp = 0;
2812 break;
2813 default:
2814 return -EINVAL;
2815 }
2816
2817 return 0;
2818 }
2819
emulate_sys_reg(u32 id,u64 * valp)2820 static int emulate_sys_reg(u32 id, u64 *valp)
2821 {
2822 struct arm64_ftr_reg *regp;
2823
2824 if (!is_emulated(id))
2825 return -EINVAL;
2826
2827 if (sys_reg_CRm(id) == 0)
2828 return emulate_id_reg(id, valp);
2829
2830 regp = get_arm64_ftr_reg_nowarn(id);
2831 if (regp)
2832 *valp = arm64_ftr_reg_user_value(regp);
2833 else
2834 /*
2835 * The untracked registers are either IMPLEMENTATION DEFINED
2836 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2837 */
2838 *valp = 0;
2839 return 0;
2840 }
2841
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)2842 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2843 {
2844 int rc;
2845 u64 val;
2846
2847 rc = emulate_sys_reg(sys_reg, &val);
2848 if (!rc) {
2849 pt_regs_write_reg(regs, rt, val);
2850 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2851 }
2852 return rc;
2853 }
2854
emulate_mrs(struct pt_regs * regs,u32 insn)2855 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2856 {
2857 u32 sys_reg, rt;
2858
2859 /*
2860 * sys_reg values are defined as used in mrs/msr instruction.
2861 * shift the imm value to get the encoding.
2862 */
2863 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2864 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2865 return do_emulate_mrs(regs, sys_reg, rt);
2866 }
2867
2868 static struct undef_hook mrs_hook = {
2869 .instr_mask = 0xfff00000,
2870 .instr_val = 0xd5300000,
2871 .pstate_mask = PSR_AA32_MODE_MASK,
2872 .pstate_val = PSR_MODE_EL0t,
2873 .fn = emulate_mrs,
2874 };
2875
enable_mrs_emulation(void)2876 static int __init enable_mrs_emulation(void)
2877 {
2878 register_undef_hook(&mrs_hook);
2879 return 0;
2880 }
2881
2882 core_initcall(enable_mrs_emulation);
2883
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2884 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2885 char *buf)
2886 {
2887 if (__meltdown_safe)
2888 return sprintf(buf, "Not affected\n");
2889
2890 if (arm64_kernel_unmapped_at_el0())
2891 return sprintf(buf, "Mitigation: PTI\n");
2892
2893 return sprintf(buf, "Vulnerable\n");
2894 }
2895