1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27
28 #include "dm_services.h"
29 #include "dc.h"
30 #include "dc_bios_types.h"
31 #include "core_types.h"
32 #include "core_status.h"
33 #include "resource.h"
34 #include "dm_helpers.h"
35 #include "dce110_hw_sequencer.h"
36 #include "dce110_timing_generator.h"
37 #include "dce/dce_hwseq.h"
38 #include "gpio_service_interface.h"
39
40 #include "dce110_compressor.h"
41
42 #include "bios/bios_parser_helper.h"
43 #include "timing_generator.h"
44 #include "mem_input.h"
45 #include "opp.h"
46 #include "ipp.h"
47 #include "transform.h"
48 #include "stream_encoder.h"
49 #include "link_encoder.h"
50 #include "link_hwss.h"
51 #include "clock_source.h"
52 #include "clk_mgr.h"
53 #include "abm.h"
54 #include "audio.h"
55 #include "reg_helper.h"
56 #include "panel_cntl.h"
57
58 /* include DCE11 register header files */
59 #include "dce/dce_11_0_d.h"
60 #include "dce/dce_11_0_sh_mask.h"
61 #include "custom_float.h"
62
63 #include "atomfirmware.h"
64
65 #define GAMMA_HW_POINTS_NUM 256
66
67 /*
68 * All values are in milliseconds;
69 * For eDP, after power-up/power/down,
70 * 300/500 msec max. delay from LCDVCC to black video generation
71 */
72 #define PANEL_POWER_UP_TIMEOUT 300
73 #define PANEL_POWER_DOWN_TIMEOUT 500
74 #define HPD_CHECK_INTERVAL 10
75 #define OLED_POST_T7_DELAY 100
76 #define OLED_PRE_T11_DELAY 150
77
78 #define CTX \
79 hws->ctx
80
81 #define DC_LOGGER_INIT()
82
83 #define REG(reg)\
84 hws->regs->reg
85
86 #undef FN
87 #define FN(reg_name, field_name) \
88 hws->shifts->field_name, hws->masks->field_name
89
90 struct dce110_hw_seq_reg_offsets {
91 uint32_t crtc;
92 };
93
94 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
95 {
96 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
97 },
98 {
99 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
100 },
101 {
102 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 },
104 {
105 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 }
107 };
108
109 #define HW_REG_BLND(reg, id)\
110 (reg + reg_offsets[id].blnd)
111
112 #define HW_REG_CRTC(reg, id)\
113 (reg + reg_offsets[id].crtc)
114
115 #define MAX_WATERMARK 0xFFFF
116 #define SAFE_NBP_MARK 0x7FFF
117
118 /*******************************************************************************
119 * Private definitions
120 ******************************************************************************/
121 /***************************PIPE_CONTROL***********************************/
dce110_init_pte(struct dc_context * ctx)122 static void dce110_init_pte(struct dc_context *ctx)
123 {
124 uint32_t addr;
125 uint32_t value = 0;
126 uint32_t chunk_int = 0;
127 uint32_t chunk_mul = 0;
128
129 addr = mmUNP_DVMM_PTE_CONTROL;
130 value = dm_read_reg(ctx, addr);
131
132 set_reg_field_value(
133 value,
134 0,
135 DVMM_PTE_CONTROL,
136 DVMM_USE_SINGLE_PTE);
137
138 set_reg_field_value(
139 value,
140 1,
141 DVMM_PTE_CONTROL,
142 DVMM_PTE_BUFFER_MODE0);
143
144 set_reg_field_value(
145 value,
146 1,
147 DVMM_PTE_CONTROL,
148 DVMM_PTE_BUFFER_MODE1);
149
150 dm_write_reg(ctx, addr, value);
151
152 addr = mmDVMM_PTE_REQ;
153 value = dm_read_reg(ctx, addr);
154
155 chunk_int = get_reg_field_value(
156 value,
157 DVMM_PTE_REQ,
158 HFLIP_PTEREQ_PER_CHUNK_INT);
159
160 chunk_mul = get_reg_field_value(
161 value,
162 DVMM_PTE_REQ,
163 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
164
165 if (chunk_int != 0x4 || chunk_mul != 0x4) {
166
167 set_reg_field_value(
168 value,
169 255,
170 DVMM_PTE_REQ,
171 MAX_PTEREQ_TO_ISSUE);
172
173 set_reg_field_value(
174 value,
175 4,
176 DVMM_PTE_REQ,
177 HFLIP_PTEREQ_PER_CHUNK_INT);
178
179 set_reg_field_value(
180 value,
181 4,
182 DVMM_PTE_REQ,
183 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
184
185 dm_write_reg(ctx, addr, value);
186 }
187 }
188 /**************************************************************************/
189
enable_display_pipe_clock_gating(struct dc_context * ctx,bool clock_gating)190 static void enable_display_pipe_clock_gating(
191 struct dc_context *ctx,
192 bool clock_gating)
193 {
194 /*TODO*/
195 }
196
dce110_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)197 static bool dce110_enable_display_power_gating(
198 struct dc *dc,
199 uint8_t controller_id,
200 struct dc_bios *dcb,
201 enum pipe_gating_control power_gating)
202 {
203 enum bp_result bp_result = BP_RESULT_OK;
204 enum bp_pipe_control_action cntl;
205 struct dc_context *ctx = dc->ctx;
206 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
207
208 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
209 return true;
210
211 if (power_gating == PIPE_GATING_CONTROL_INIT)
212 cntl = ASIC_PIPE_INIT;
213 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
214 cntl = ASIC_PIPE_ENABLE;
215 else
216 cntl = ASIC_PIPE_DISABLE;
217
218 if (controller_id == underlay_idx)
219 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
220
221 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
222
223 bp_result = dcb->funcs->enable_disp_power_gating(
224 dcb, controller_id + 1, cntl);
225
226 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
227 * by default when command table is called
228 *
229 * Bios parser accepts controller_id = 6 as indicative of
230 * underlay pipe in dce110. But we do not support more
231 * than 3.
232 */
233 if (controller_id < CONTROLLER_ID_MAX - 1)
234 dm_write_reg(ctx,
235 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
236 0);
237 }
238
239 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
240 dce110_init_pte(ctx);
241
242 if (bp_result == BP_RESULT_OK)
243 return true;
244 else
245 return false;
246 }
247
build_prescale_params(struct ipp_prescale_params * prescale_params,const struct dc_plane_state * plane_state)248 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
249 const struct dc_plane_state *plane_state)
250 {
251 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
252
253 switch (plane_state->format) {
254 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
255 prescale_params->scale = 0x2082;
256 break;
257 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
258 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
259 prescale_params->scale = 0x2020;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
262 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
263 prescale_params->scale = 0x2008;
264 break;
265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
267 prescale_params->scale = 0x2000;
268 break;
269 default:
270 ASSERT(false);
271 break;
272 }
273 }
274
275 static bool
dce110_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)276 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
277 const struct dc_plane_state *plane_state)
278 {
279 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
280 const struct dc_transfer_func *tf = NULL;
281 struct ipp_prescale_params prescale_params = { 0 };
282 bool result = true;
283
284 if (ipp == NULL)
285 return false;
286
287 if (plane_state->in_transfer_func)
288 tf = plane_state->in_transfer_func;
289
290 build_prescale_params(&prescale_params, plane_state);
291 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
292
293 if (plane_state->gamma_correction &&
294 !plane_state->gamma_correction->is_identity &&
295 dce_use_lut(plane_state->format))
296 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
297
298 if (tf == NULL) {
299 /* Default case if no input transfer function specified */
300 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
301 } else if (tf->type == TF_TYPE_PREDEFINED) {
302 switch (tf->tf) {
303 case TRANSFER_FUNCTION_SRGB:
304 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
305 break;
306 case TRANSFER_FUNCTION_BT709:
307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
308 break;
309 case TRANSFER_FUNCTION_LINEAR:
310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
311 break;
312 case TRANSFER_FUNCTION_PQ:
313 default:
314 result = false;
315 break;
316 }
317 } else if (tf->type == TF_TYPE_BYPASS) {
318 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
319 } else {
320 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
321 result = false;
322 }
323
324 return result;
325 }
326
convert_to_custom_float(struct pwl_result_data * rgb_resulted,struct curve_points * arr_points,uint32_t hw_points_num)327 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
328 struct curve_points *arr_points,
329 uint32_t hw_points_num)
330 {
331 struct custom_float_format fmt;
332
333 struct pwl_result_data *rgb = rgb_resulted;
334
335 uint32_t i = 0;
336
337 fmt.exponenta_bits = 6;
338 fmt.mantissa_bits = 12;
339 fmt.sign = true;
340
341 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
342 &arr_points[0].custom_float_x)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
348 &arr_points[0].custom_float_offset)) {
349 BREAK_TO_DEBUGGER();
350 return false;
351 }
352
353 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
354 &arr_points[0].custom_float_slope)) {
355 BREAK_TO_DEBUGGER();
356 return false;
357 }
358
359 fmt.mantissa_bits = 10;
360 fmt.sign = false;
361
362 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
363 &arr_points[1].custom_float_x)) {
364 BREAK_TO_DEBUGGER();
365 return false;
366 }
367
368 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
369 &arr_points[1].custom_float_y)) {
370 BREAK_TO_DEBUGGER();
371 return false;
372 }
373
374 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
375 &arr_points[1].custom_float_slope)) {
376 BREAK_TO_DEBUGGER();
377 return false;
378 }
379
380 fmt.mantissa_bits = 12;
381 fmt.sign = true;
382
383 while (i != hw_points_num) {
384 if (!convert_to_custom_float_format(rgb->red, &fmt,
385 &rgb->red_reg)) {
386 BREAK_TO_DEBUGGER();
387 return false;
388 }
389
390 if (!convert_to_custom_float_format(rgb->green, &fmt,
391 &rgb->green_reg)) {
392 BREAK_TO_DEBUGGER();
393 return false;
394 }
395
396 if (!convert_to_custom_float_format(rgb->blue, &fmt,
397 &rgb->blue_reg)) {
398 BREAK_TO_DEBUGGER();
399 return false;
400 }
401
402 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
403 &rgb->delta_red_reg)) {
404 BREAK_TO_DEBUGGER();
405 return false;
406 }
407
408 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
409 &rgb->delta_green_reg)) {
410 BREAK_TO_DEBUGGER();
411 return false;
412 }
413
414 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
415 &rgb->delta_blue_reg)) {
416 BREAK_TO_DEBUGGER();
417 return false;
418 }
419
420 ++rgb;
421 ++i;
422 }
423
424 return true;
425 }
426
427 #define MAX_LOW_POINT 25
428 #define NUMBER_REGIONS 16
429 #define NUMBER_SW_SEGMENTS 16
430
431 static bool
dce110_translate_regamma_to_hw_format(const struct dc_transfer_func * output_tf,struct pwl_params * regamma_params)432 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
433 struct pwl_params *regamma_params)
434 {
435 struct curve_points *arr_points;
436 struct pwl_result_data *rgb_resulted;
437 struct pwl_result_data *rgb;
438 struct pwl_result_data *rgb_plus_1;
439 struct fixed31_32 y_r;
440 struct fixed31_32 y_g;
441 struct fixed31_32 y_b;
442 struct fixed31_32 y1_min;
443 struct fixed31_32 y3_max;
444
445 int32_t region_start, region_end;
446 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
447
448 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
449 return false;
450
451 arr_points = regamma_params->arr_points;
452 rgb_resulted = regamma_params->rgb_resulted;
453 hw_points = 0;
454
455 memset(regamma_params, 0, sizeof(struct pwl_params));
456
457 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
458 /* 16 segments
459 * segments are from 2^-11 to 2^5
460 */
461 region_start = -11;
462 region_end = region_start + NUMBER_REGIONS;
463
464 for (i = 0; i < NUMBER_REGIONS; i++)
465 seg_distr[i] = 4;
466
467 } else {
468 /* 10 segments
469 * segment is from 2^-10 to 2^1
470 * We include an extra segment for range [2^0, 2^1). This is to
471 * ensure that colors with normalized values of 1 don't miss the
472 * LUT.
473 */
474 region_start = -10;
475 region_end = 1;
476
477 seg_distr[0] = 4;
478 seg_distr[1] = 4;
479 seg_distr[2] = 4;
480 seg_distr[3] = 4;
481 seg_distr[4] = 4;
482 seg_distr[5] = 4;
483 seg_distr[6] = 4;
484 seg_distr[7] = 4;
485 seg_distr[8] = 4;
486 seg_distr[9] = 4;
487 seg_distr[10] = 0;
488 seg_distr[11] = -1;
489 seg_distr[12] = -1;
490 seg_distr[13] = -1;
491 seg_distr[14] = -1;
492 seg_distr[15] = -1;
493 }
494
495 for (k = 0; k < 16; k++) {
496 if (seg_distr[k] != -1)
497 hw_points += (1 << seg_distr[k]);
498 }
499
500 j = 0;
501 for (k = 0; k < (region_end - region_start); k++) {
502 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
503 start_index = (region_start + k + MAX_LOW_POINT) *
504 NUMBER_SW_SEGMENTS;
505 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
506 i += increment) {
507 if (j == hw_points - 1)
508 break;
509 rgb_resulted[j].red = output_tf->tf_pts.red[i];
510 rgb_resulted[j].green = output_tf->tf_pts.green[i];
511 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 j++;
513 }
514 }
515
516 /* last point */
517 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
518 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
519 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
520 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
521
522 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
523 dc_fixpt_from_int(region_start));
524 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
525 dc_fixpt_from_int(region_end));
526
527 y_r = rgb_resulted[0].red;
528 y_g = rgb_resulted[0].green;
529 y_b = rgb_resulted[0].blue;
530
531 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
532
533 arr_points[0].y = y1_min;
534 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
535 arr_points[0].x);
536
537 y_r = rgb_resulted[hw_points - 1].red;
538 y_g = rgb_resulted[hw_points - 1].green;
539 y_b = rgb_resulted[hw_points - 1].blue;
540
541 /* see comment above, m_arrPoints[1].y should be the Y value for the
542 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
543 */
544 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
545
546 arr_points[1].y = y3_max;
547
548 arr_points[1].slope = dc_fixpt_zero;
549
550 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
551 /* for PQ, we want to have a straight line from last HW X point,
552 * and the slope to be such that we hit 1.0 at 10000 nits.
553 */
554 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
555
556 arr_points[1].slope = dc_fixpt_div(
557 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
558 dc_fixpt_sub(end_value, arr_points[1].x));
559 }
560
561 regamma_params->hw_points_num = hw_points;
562
563 k = 0;
564 for (i = 1; i < 16; i++) {
565 if (seg_distr[k] != -1) {
566 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
567 regamma_params->arr_curve_points[i].offset =
568 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
569 }
570 k++;
571 }
572
573 if (seg_distr[k] != -1)
574 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
575
576 rgb = rgb_resulted;
577 rgb_plus_1 = rgb_resulted + 1;
578
579 i = 1;
580
581 while (i != hw_points + 1) {
582 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
583 rgb_plus_1->red = rgb->red;
584 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
585 rgb_plus_1->green = rgb->green;
586 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
587 rgb_plus_1->blue = rgb->blue;
588
589 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
590 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
591 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
592
593 ++rgb_plus_1;
594 ++rgb;
595 ++i;
596 }
597
598 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
599
600 return true;
601 }
602
603 static bool
dce110_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)604 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
605 const struct dc_stream_state *stream)
606 {
607 struct transform *xfm = pipe_ctx->plane_res.xfm;
608
609 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
610 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
611
612 if (stream->out_transfer_func &&
613 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
614 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
616 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
617 &xfm->regamma_params)) {
618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
620 } else {
621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
622 }
623
624 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
625
626 return true;
627 }
628
dce110_update_info_frame(struct pipe_ctx * pipe_ctx)629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
630 {
631 bool is_hdmi_tmds;
632 bool is_dp;
633
634 ASSERT(pipe_ctx->stream);
635
636 if (pipe_ctx->stream_res.stream_enc == NULL)
637 return; /* this is not root pipe */
638
639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
641
642 if (!is_hdmi_tmds && !is_dp)
643 return;
644
645 if (is_hdmi_tmds)
646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
647 pipe_ctx->stream_res.stream_enc,
648 &pipe_ctx->stream_res.encoder_info_frame);
649 else
650 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
651 pipe_ctx->stream_res.stream_enc,
652 &pipe_ctx->stream_res.encoder_info_frame);
653 }
654
dce110_enable_stream(struct pipe_ctx * pipe_ctx)655 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
656 {
657 enum dc_lane_count lane_count =
658 pipe_ctx->stream->link->cur_link_settings.lane_count;
659 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
660 struct dc_link *link = pipe_ctx->stream->link;
661 const struct dc *dc = link->dc;
662
663 uint32_t active_total_with_borders;
664 uint32_t early_control = 0;
665 struct timing_generator *tg = pipe_ctx->stream_res.tg;
666
667 /* For MST, there are multiply stream go to only one link.
668 * connect DIG back_end to front_end while enable_stream and
669 * disconnect them during disable_stream
670 * BY this, it is logic clean to separate stream and link */
671 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
672 pipe_ctx->stream_res.stream_enc->id, true);
673
674 dc->hwss.update_info_frame(pipe_ctx);
675
676 /* enable early control to avoid corruption on DP monitor*/
677 active_total_with_borders =
678 timing->h_addressable
679 + timing->h_border_left
680 + timing->h_border_right;
681
682 if (lane_count != 0)
683 early_control = active_total_with_borders % lane_count;
684
685 if (early_control == 0)
686 early_control = lane_count;
687
688 tg->funcs->set_early_control(tg, early_control);
689
690 /* enable audio only within mode set */
691 if (pipe_ctx->stream_res.audio != NULL) {
692 if (dc_is_dp_signal(pipe_ctx->stream->signal))
693 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
694 }
695
696
697
698
699 }
700
link_transmitter_control(struct dc_bios * bios,struct bp_transmitter_control * cntl)701 static enum bp_result link_transmitter_control(
702 struct dc_bios *bios,
703 struct bp_transmitter_control *cntl)
704 {
705 enum bp_result result;
706
707 result = bios->funcs->transmitter_control(bios, cntl);
708
709 return result;
710 }
711
712 /*
713 * @brief
714 * eDP only.
715 */
dce110_edp_wait_for_hpd_ready(struct dc_link * link,bool power_up)716 void dce110_edp_wait_for_hpd_ready(
717 struct dc_link *link,
718 bool power_up)
719 {
720 struct dc_context *ctx = link->ctx;
721 struct graphics_object_id connector = link->link_enc->connector;
722 struct gpio *hpd;
723 struct dc_sink *sink = link->local_sink;
724 bool edp_hpd_high = false;
725 uint32_t time_elapsed = 0;
726 uint32_t timeout = power_up ?
727 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
728
729 if (dal_graphics_object_id_get_connector_id(connector)
730 != CONNECTOR_ID_EDP) {
731 BREAK_TO_DEBUGGER();
732 return;
733 }
734
735 if (!power_up)
736 /*
737 * From KV, we will not HPD low after turning off VCC -
738 * instead, we will check the SW timer in power_up().
739 */
740 return;
741
742 /*
743 * When we power on/off the eDP panel,
744 * we need to wait until SENSE bit is high/low.
745 */
746
747 /* obtain HPD */
748 /* TODO what to do with this? */
749 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
750
751 if (!hpd) {
752 BREAK_TO_DEBUGGER();
753 return;
754 }
755
756 if (sink != NULL) {
757 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
758 int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
759
760 msleep(extra_t3_in_ms);
761 }
762 }
763
764 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
765
766 /* wait until timeout or panel detected */
767
768 do {
769 uint32_t detected = 0;
770
771 dal_gpio_get_value(hpd, &detected);
772
773 if (!(detected ^ power_up)) {
774 edp_hpd_high = true;
775 break;
776 }
777
778 msleep(HPD_CHECK_INTERVAL);
779
780 time_elapsed += HPD_CHECK_INTERVAL;
781 } while (time_elapsed < timeout);
782
783 dal_gpio_close(hpd);
784
785 dal_gpio_destroy_irq(&hpd);
786
787 if (false == edp_hpd_high) {
788 DC_LOG_ERROR(
789 "%s: wait timed out!\n", __func__);
790 }
791 }
792
dce110_edp_power_control(struct dc_link * link,bool power_up)793 void dce110_edp_power_control(
794 struct dc_link *link,
795 bool power_up)
796 {
797 struct dc_context *ctx = link->ctx;
798 struct bp_transmitter_control cntl = { 0 };
799 enum bp_result bp_result;
800
801
802 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
803 != CONNECTOR_ID_EDP) {
804 BREAK_TO_DEBUGGER();
805 return;
806 }
807
808 if (!link->panel_cntl)
809 return;
810
811 if (power_up !=
812 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
813
814 unsigned long long current_ts = dm_get_timestamp(ctx);
815 unsigned long long time_since_edp_poweroff_ms =
816 div64_u64(dm_get_elapse_time_in_ns(
817 ctx,
818 current_ts,
819 link->link_trace.time_stamp.edp_poweroff), 1000000);
820 unsigned long long time_since_edp_poweron_ms =
821 div64_u64(dm_get_elapse_time_in_ns(
822 ctx,
823 current_ts,
824 link->link_trace.time_stamp.edp_poweron), 1000000);
825 DC_LOG_HW_RESUME_S3(
826 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
827 __func__,
828 power_up,
829 current_ts,
830 link->link_trace.time_stamp.edp_poweroff,
831 link->link_trace.time_stamp.edp_poweron,
832 time_since_edp_poweroff_ms,
833 time_since_edp_poweron_ms);
834
835 /* Send VBIOS command to prompt eDP panel power */
836 if (power_up) {
837 /* edp requires a min of 500ms from LCDVDD off to on */
838 unsigned long long remaining_min_edp_poweroff_time_ms = 500;
839
840 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
841 if (link->local_sink != NULL)
842 remaining_min_edp_poweroff_time_ms +=
843 link->local_sink->edid_caps.panel_patch.extra_t12_ms;
844
845 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
846 if (link->link_trace.time_stamp.edp_poweroff != 0) {
847 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
848 remaining_min_edp_poweroff_time_ms =
849 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
850 else
851 remaining_min_edp_poweroff_time_ms = 0;
852 }
853
854 if (remaining_min_edp_poweroff_time_ms) {
855 DC_LOG_HW_RESUME_S3(
856 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
857 __func__, remaining_min_edp_poweroff_time_ms);
858 msleep(remaining_min_edp_poweroff_time_ms);
859 DC_LOG_HW_RESUME_S3(
860 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
861 __func__, remaining_min_edp_poweroff_time_ms);
862 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
863 __func__, remaining_min_edp_poweroff_time_ms);
864 } else {
865 DC_LOG_HW_RESUME_S3(
866 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
867 __func__, remaining_min_edp_poweroff_time_ms);
868 }
869 }
870
871 DC_LOG_HW_RESUME_S3(
872 "%s: BEGIN: Panel Power action: %s\n",
873 __func__, (power_up ? "On":"Off"));
874
875 cntl.action = power_up ?
876 TRANSMITTER_CONTROL_POWER_ON :
877 TRANSMITTER_CONTROL_POWER_OFF;
878 cntl.transmitter = link->link_enc->transmitter;
879 cntl.connector_obj_id = link->link_enc->connector;
880 cntl.coherent = false;
881 cntl.lanes_number = LANE_COUNT_FOUR;
882 cntl.hpd_sel = link->link_enc->hpd_source;
883
884 if (ctx->dc->ctx->dmub_srv &&
885 ctx->dc->debug.dmub_command_table) {
886 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
887 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
888 LVTMA_CONTROL_POWER_ON);
889 else
890 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
891 LVTMA_CONTROL_POWER_OFF);
892 }
893
894 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
895
896 DC_LOG_HW_RESUME_S3(
897 "%s: END: Panel Power action: %s bp_result=%u\n",
898 __func__, (power_up ? "On":"Off"),
899 bp_result);
900
901 if (!power_up)
902 /*save driver power off time stamp*/
903 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
904 else
905 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
906
907 DC_LOG_HW_RESUME_S3(
908 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
909 __func__,
910 link->link_trace.time_stamp.edp_poweroff,
911 link->link_trace.time_stamp.edp_poweron);
912
913 if (bp_result != BP_RESULT_OK)
914 DC_LOG_ERROR(
915 "%s: Panel Power bp_result: %d\n",
916 __func__, bp_result);
917 } else {
918 DC_LOG_HW_RESUME_S3(
919 "%s: Skipping Panel Power action: %s\n",
920 __func__, (power_up ? "On":"Off"));
921 }
922 }
923
924 /*todo: cloned in stream enc, fix*/
925 /*
926 * @brief
927 * eDP only. Control the backlight of the eDP panel
928 */
dce110_edp_backlight_control(struct dc_link * link,bool enable)929 void dce110_edp_backlight_control(
930 struct dc_link *link,
931 bool enable)
932 {
933 struct dc_context *ctx = link->ctx;
934 struct bp_transmitter_control cntl = { 0 };
935
936 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
937 != CONNECTOR_ID_EDP) {
938 BREAK_TO_DEBUGGER();
939 return;
940 }
941
942 if (enable && link->panel_cntl &&
943 link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl)) {
944 DC_LOG_HW_RESUME_S3(
945 "%s: panel already powered up. Do nothing.\n",
946 __func__);
947 return;
948 }
949
950 /* Send VBIOS command to control eDP panel backlight */
951
952 DC_LOG_HW_RESUME_S3(
953 "%s: backlight action: %s\n",
954 __func__, (enable ? "On":"Off"));
955
956 cntl.action = enable ?
957 TRANSMITTER_CONTROL_BACKLIGHT_ON :
958 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
959
960 /*cntl.engine_id = ctx->engine;*/
961 cntl.transmitter = link->link_enc->transmitter;
962 cntl.connector_obj_id = link->link_enc->connector;
963 /*todo: unhardcode*/
964 cntl.lanes_number = LANE_COUNT_FOUR;
965 cntl.hpd_sel = link->link_enc->hpd_source;
966 cntl.signal = SIGNAL_TYPE_EDP;
967
968 /* For eDP, the following delays might need to be considered
969 * after link training completed:
970 * idle period - min. accounts for required BS-Idle pattern,
971 * max. allows for source frame synchronization);
972 * 50 msec max. delay from valid video data from source
973 * to video on dislpay or backlight enable.
974 *
975 * Disable the delay for now.
976 * Enable it in the future if necessary.
977 */
978 /* dc_service_sleep_in_milliseconds(50); */
979 /*edp 1.2*/
980 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
981 edp_receiver_ready_T7(link);
982
983 if (ctx->dc->ctx->dmub_srv &&
984 ctx->dc->debug.dmub_command_table) {
985 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
986 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
987 LVTMA_CONTROL_LCD_BLON);
988 else
989 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
990 LVTMA_CONTROL_LCD_BLOFF);
991 }
992
993 link_transmitter_control(ctx->dc_bios, &cntl);
994
995
996
997 if (enable && link->dpcd_sink_ext_caps.bits.oled)
998 msleep(OLED_POST_T7_DELAY);
999
1000 if (link->dpcd_sink_ext_caps.bits.oled ||
1001 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1002 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1003 dc_link_backlight_enable_aux(link, enable);
1004
1005 /*edp 1.2*/
1006 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
1007 edp_receiver_ready_T9(link);
1008
1009 if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1010 msleep(OLED_PRE_T11_DELAY);
1011 }
1012
dce110_enable_audio_stream(struct pipe_ctx * pipe_ctx)1013 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1014 {
1015 /* notify audio driver for audio modes of monitor */
1016 struct dc *dc;
1017 struct clk_mgr *clk_mgr;
1018 unsigned int i, num_audio = 1;
1019
1020 if (!pipe_ctx->stream)
1021 return;
1022
1023 dc = pipe_ctx->stream->ctx->dc;
1024 clk_mgr = dc->clk_mgr;
1025
1026 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1027 return;
1028
1029 if (pipe_ctx->stream_res.audio) {
1030 for (i = 0; i < MAX_PIPES; i++) {
1031 /*current_state not updated yet*/
1032 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1033 num_audio++;
1034 }
1035
1036 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1037
1038 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1039 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1040 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1041 /* un-mute audio */
1042 /* TODO: audio should be per stream rather than per link */
1043 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1044 pipe_ctx->stream_res.stream_enc, false);
1045 if (pipe_ctx->stream_res.audio)
1046 pipe_ctx->stream_res.audio->enabled = true;
1047 }
1048 }
1049
dce110_disable_audio_stream(struct pipe_ctx * pipe_ctx)1050 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1051 {
1052 struct dc *dc;
1053 struct clk_mgr *clk_mgr;
1054
1055 if (!pipe_ctx || !pipe_ctx->stream)
1056 return;
1057
1058 dc = pipe_ctx->stream->ctx->dc;
1059 clk_mgr = dc->clk_mgr;
1060
1061 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1062 return;
1063
1064 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1065 pipe_ctx->stream_res.stream_enc, true);
1066 if (pipe_ctx->stream_res.audio) {
1067 pipe_ctx->stream_res.audio->enabled = false;
1068
1069 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1070 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1071 pipe_ctx->stream_res.stream_enc);
1072 else
1073 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1074 pipe_ctx->stream_res.stream_enc);
1075
1076 if (clk_mgr->funcs->enable_pme_wa)
1077 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1078 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1079
1080 /* TODO: notify audio driver for if audio modes list changed
1081 * add audio mode list change flag */
1082 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1083 * stream->stream_engine_id);
1084 */
1085 }
1086 }
1087
dce110_disable_stream(struct pipe_ctx * pipe_ctx)1088 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1089 {
1090 struct dc_stream_state *stream = pipe_ctx->stream;
1091 struct dc_link *link = stream->link;
1092 struct dc *dc = pipe_ctx->stream->ctx->dc;
1093
1094 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1095 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1096 pipe_ctx->stream_res.stream_enc);
1097 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1098 pipe_ctx->stream_res.stream_enc);
1099 }
1100
1101 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1102 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1103 pipe_ctx->stream_res.stream_enc);
1104
1105 dc->hwss.disable_audio_stream(pipe_ctx);
1106
1107 link->link_enc->funcs->connect_dig_be_to_fe(
1108 link->link_enc,
1109 pipe_ctx->stream_res.stream_enc->id,
1110 false);
1111
1112 }
1113
dce110_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1114 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1115 struct dc_link_settings *link_settings)
1116 {
1117 struct encoder_unblank_param params = { { 0 } };
1118 struct dc_stream_state *stream = pipe_ctx->stream;
1119 struct dc_link *link = stream->link;
1120 struct dce_hwseq *hws = link->dc->hwseq;
1121
1122 /* only 3 items below are used by unblank */
1123 params.timing = pipe_ctx->stream->timing;
1124 params.link_settings.link_rate = link_settings->link_rate;
1125
1126 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1127 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1128
1129 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1130 hws->funcs.edp_backlight_control(link, true);
1131 }
1132 }
1133
dce110_blank_stream(struct pipe_ctx * pipe_ctx)1134 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1135 {
1136 struct dc_stream_state *stream = pipe_ctx->stream;
1137 struct dc_link *link = stream->link;
1138 struct dce_hwseq *hws = link->dc->hwseq;
1139
1140 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1141 hws->funcs.edp_backlight_control(link, false);
1142 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1143 }
1144
1145 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1146 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1147
1148 /*
1149 * After output is idle pattern some sinks need time to recognize the stream
1150 * has changed or they enter protection state and hang.
1151 */
1152 if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
1153 msleep(60);
1154 }
1155
1156 }
1157
1158
dce110_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)1159 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1160 {
1161 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1162 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1163 }
1164
translate_to_dto_source(enum controller_id crtc_id)1165 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1166 {
1167 switch (crtc_id) {
1168 case CONTROLLER_ID_D0:
1169 return DTO_SOURCE_ID0;
1170 case CONTROLLER_ID_D1:
1171 return DTO_SOURCE_ID1;
1172 case CONTROLLER_ID_D2:
1173 return DTO_SOURCE_ID2;
1174 case CONTROLLER_ID_D3:
1175 return DTO_SOURCE_ID3;
1176 case CONTROLLER_ID_D4:
1177 return DTO_SOURCE_ID4;
1178 case CONTROLLER_ID_D5:
1179 return DTO_SOURCE_ID5;
1180 default:
1181 return DTO_SOURCE_UNKNOWN;
1182 }
1183 }
1184
build_audio_output(struct dc_state * state,const struct pipe_ctx * pipe_ctx,struct audio_output * audio_output)1185 static void build_audio_output(
1186 struct dc_state *state,
1187 const struct pipe_ctx *pipe_ctx,
1188 struct audio_output *audio_output)
1189 {
1190 const struct dc_stream_state *stream = pipe_ctx->stream;
1191 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1192
1193 audio_output->signal = pipe_ctx->stream->signal;
1194
1195 /* audio_crtc_info */
1196
1197 audio_output->crtc_info.h_total =
1198 stream->timing.h_total;
1199
1200 /*
1201 * Audio packets are sent during actual CRTC blank physical signal, we
1202 * need to specify actual active signal portion
1203 */
1204 audio_output->crtc_info.h_active =
1205 stream->timing.h_addressable
1206 + stream->timing.h_border_left
1207 + stream->timing.h_border_right;
1208
1209 audio_output->crtc_info.v_active =
1210 stream->timing.v_addressable
1211 + stream->timing.v_border_top
1212 + stream->timing.v_border_bottom;
1213
1214 audio_output->crtc_info.pixel_repetition = 1;
1215
1216 audio_output->crtc_info.interlaced =
1217 stream->timing.flags.INTERLACE;
1218
1219 audio_output->crtc_info.refresh_rate =
1220 (stream->timing.pix_clk_100hz*100)/
1221 (stream->timing.h_total*stream->timing.v_total);
1222
1223 audio_output->crtc_info.color_depth =
1224 stream->timing.display_color_depth;
1225
1226 audio_output->crtc_info.requested_pixel_clock_100Hz =
1227 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1228
1229 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1230 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1231
1232 /*for HDMI, audio ACR is with deep color ratio factor*/
1233 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1234 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1235 (stream->timing.pix_clk_100hz)) {
1236 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1237 audio_output->crtc_info.requested_pixel_clock_100Hz =
1238 audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1239 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1240 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1241
1242 }
1243 }
1244
1245 if (state->clk_mgr &&
1246 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1247 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1248 audio_output->pll_info.dp_dto_source_clock_in_khz =
1249 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1250 state->clk_mgr);
1251 }
1252
1253 audio_output->pll_info.feed_back_divider =
1254 pipe_ctx->pll_settings.feedback_divider;
1255
1256 audio_output->pll_info.dto_source =
1257 translate_to_dto_source(
1258 pipe_ctx->stream_res.tg->inst + 1);
1259
1260 /* TODO hard code to enable for now. Need get from stream */
1261 audio_output->pll_info.ss_enabled = true;
1262
1263 audio_output->pll_info.ss_percentage =
1264 pipe_ctx->pll_settings.ss_percentage;
1265 }
1266
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)1267 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1268 struct tg_color *color)
1269 {
1270 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1271
1272 switch (pipe_ctx->plane_res.scl_data.format) {
1273 case PIXEL_FORMAT_ARGB8888:
1274 /* set boarder color to red */
1275 color->color_r_cr = color_value;
1276 break;
1277
1278 case PIXEL_FORMAT_ARGB2101010:
1279 /* set boarder color to blue */
1280 color->color_b_cb = color_value;
1281 break;
1282 case PIXEL_FORMAT_420BPP8:
1283 /* set boarder color to green */
1284 color->color_g_y = color_value;
1285 break;
1286 case PIXEL_FORMAT_420BPP10:
1287 /* set boarder color to yellow */
1288 color->color_g_y = color_value;
1289 color->color_r_cr = color_value;
1290 break;
1291 case PIXEL_FORMAT_FP16:
1292 /* set boarder color to white */
1293 color->color_r_cr = color_value;
1294 color->color_b_cb = color_value;
1295 color->color_g_y = color_value;
1296 break;
1297 default:
1298 break;
1299 }
1300 }
1301
program_scaler(const struct dc * dc,const struct pipe_ctx * pipe_ctx)1302 static void program_scaler(const struct dc *dc,
1303 const struct pipe_ctx *pipe_ctx)
1304 {
1305 struct tg_color color = {0};
1306
1307 #if defined(CONFIG_DRM_AMD_DC_DCN)
1308 /* TOFPGA */
1309 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1310 return;
1311 #endif
1312
1313 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1314 get_surface_visual_confirm_color(pipe_ctx, &color);
1315 else
1316 color_space_to_black_color(dc,
1317 pipe_ctx->stream->output_color_space,
1318 &color);
1319
1320 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1321 pipe_ctx->plane_res.xfm,
1322 pipe_ctx->plane_res.scl_data.lb_params.depth,
1323 &pipe_ctx->stream->bit_depth_params);
1324
1325 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1326 /*
1327 * The way 420 is packed, 2 channels carry Y component, 1 channel
1328 * alternate between Cb and Cr, so both channels need the pixel
1329 * value for Y
1330 */
1331 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1332 color.color_r_cr = color.color_g_y;
1333
1334 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1335 pipe_ctx->stream_res.tg,
1336 &color);
1337 }
1338
1339 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1340 &pipe_ctx->plane_res.scl_data);
1341 }
1342
dce110_enable_stream_timing(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1343 static enum dc_status dce110_enable_stream_timing(
1344 struct pipe_ctx *pipe_ctx,
1345 struct dc_state *context,
1346 struct dc *dc)
1347 {
1348 struct dc_stream_state *stream = pipe_ctx->stream;
1349 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1350 pipe_ctx[pipe_ctx->pipe_idx];
1351 struct tg_color black_color = {0};
1352
1353 if (!pipe_ctx_old->stream) {
1354
1355 /* program blank color */
1356 color_space_to_black_color(dc,
1357 stream->output_color_space, &black_color);
1358 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1359 pipe_ctx->stream_res.tg,
1360 &black_color);
1361
1362 /*
1363 * Must blank CRTC after disabling power gating and before any
1364 * programming, otherwise CRTC will be hung in bad state
1365 */
1366 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1367
1368 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1369 pipe_ctx->clock_source,
1370 &pipe_ctx->stream_res.pix_clk_params,
1371 &pipe_ctx->pll_settings)) {
1372 BREAK_TO_DEBUGGER();
1373 return DC_ERROR_UNEXPECTED;
1374 }
1375
1376 pipe_ctx->stream_res.tg->funcs->program_timing(
1377 pipe_ctx->stream_res.tg,
1378 &stream->timing,
1379 0,
1380 0,
1381 0,
1382 0,
1383 pipe_ctx->stream->signal,
1384 true);
1385 }
1386
1387 if (!pipe_ctx_old->stream) {
1388 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1389 pipe_ctx->stream_res.tg)) {
1390 BREAK_TO_DEBUGGER();
1391 return DC_ERROR_UNEXPECTED;
1392 }
1393 }
1394
1395 return DC_OK;
1396 }
1397
apply_single_controller_ctx_to_hw(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1398 static enum dc_status apply_single_controller_ctx_to_hw(
1399 struct pipe_ctx *pipe_ctx,
1400 struct dc_state *context,
1401 struct dc *dc)
1402 {
1403 struct dc_stream_state *stream = pipe_ctx->stream;
1404 struct drr_params params = {0};
1405 unsigned int event_triggers = 0;
1406 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1407 struct dce_hwseq *hws = dc->hwseq;
1408
1409 if (hws->funcs.disable_stream_gating) {
1410 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1411 }
1412
1413 if (pipe_ctx->stream_res.audio != NULL) {
1414 struct audio_output audio_output;
1415
1416 build_audio_output(context, pipe_ctx, &audio_output);
1417
1418 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1419 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1420 pipe_ctx->stream_res.stream_enc,
1421 pipe_ctx->stream_res.audio->inst,
1422 &pipe_ctx->stream->audio_info);
1423 else
1424 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1425 pipe_ctx->stream_res.stream_enc,
1426 pipe_ctx->stream_res.audio->inst,
1427 &pipe_ctx->stream->audio_info,
1428 &audio_output.crtc_info);
1429
1430 pipe_ctx->stream_res.audio->funcs->az_configure(
1431 pipe_ctx->stream_res.audio,
1432 pipe_ctx->stream->signal,
1433 &audio_output.crtc_info,
1434 &pipe_ctx->stream->audio_info);
1435 }
1436
1437 /* */
1438 /* Do not touch stream timing on seamless boot optimization. */
1439 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1440 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1441
1442 if (hws->funcs.setup_vupdate_interrupt)
1443 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1444
1445 params.vertical_total_min = stream->adjust.v_total_min;
1446 params.vertical_total_max = stream->adjust.v_total_max;
1447 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1448 pipe_ctx->stream_res.tg->funcs->set_drr(
1449 pipe_ctx->stream_res.tg, ¶ms);
1450
1451 // DRR should set trigger event to monitor surface update event
1452 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1453 event_triggers = 0x80;
1454 /* Event triggers and num frames initialized for DRR, but can be
1455 * later updated for PSR use. Note DRR trigger events are generated
1456 * regardless of whether num frames met.
1457 */
1458 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1459 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1460 pipe_ctx->stream_res.tg, event_triggers, 2);
1461
1462 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1463 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1464 pipe_ctx->stream_res.stream_enc,
1465 pipe_ctx->stream_res.tg->inst);
1466
1467 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1468 pipe_ctx->stream_res.opp,
1469 COLOR_SPACE_YCBCR601,
1470 stream->timing.display_color_depth,
1471 stream->signal);
1472
1473 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1474 pipe_ctx->stream_res.opp,
1475 &stream->bit_depth_params,
1476 &stream->clamping);
1477 while (odm_pipe) {
1478 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1479 odm_pipe->stream_res.opp,
1480 COLOR_SPACE_YCBCR601,
1481 stream->timing.display_color_depth,
1482 stream->signal);
1483
1484 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1485 odm_pipe->stream_res.opp,
1486 &stream->bit_depth_params,
1487 &stream->clamping);
1488 odm_pipe = odm_pipe->next_odm_pipe;
1489 }
1490
1491 if (!stream->dpms_off)
1492 core_link_enable_stream(context, pipe_ctx);
1493
1494 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1495
1496 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1497
1498 return DC_OK;
1499 }
1500
1501 /******************************************************************************/
1502
power_down_encoders(struct dc * dc)1503 static void power_down_encoders(struct dc *dc)
1504 {
1505 int i;
1506
1507 /* do not know BIOS back-front mapping, simply blank all. It will not
1508 * hurt for non-DP
1509 */
1510 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1511 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1512 dc->res_pool->stream_enc[i]);
1513 }
1514
1515 for (i = 0; i < dc->link_count; i++) {
1516 enum signal_type signal = dc->links[i]->connector_signal;
1517
1518 if ((signal == SIGNAL_TYPE_EDP) ||
1519 (signal == SIGNAL_TYPE_DISPLAY_PORT))
1520 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1521 dp_receiver_power_ctrl(dc->links[i], false);
1522
1523 if (signal != SIGNAL_TYPE_EDP)
1524 signal = SIGNAL_TYPE_NONE;
1525
1526 dc->links[i]->link_enc->funcs->disable_output(
1527 dc->links[i]->link_enc, signal);
1528
1529 dc->links[i]->link_status.link_active = false;
1530 }
1531 }
1532
power_down_controllers(struct dc * dc)1533 static void power_down_controllers(struct dc *dc)
1534 {
1535 int i;
1536
1537 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1538 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1539 dc->res_pool->timing_generators[i]);
1540 }
1541 }
1542
power_down_clock_sources(struct dc * dc)1543 static void power_down_clock_sources(struct dc *dc)
1544 {
1545 int i;
1546
1547 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1548 dc->res_pool->dp_clock_source) == false)
1549 dm_error("Failed to power down pll! (dp clk src)\n");
1550
1551 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1552 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1553 dc->res_pool->clock_sources[i]) == false)
1554 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1555 }
1556 }
1557
power_down_all_hw_blocks(struct dc * dc)1558 static void power_down_all_hw_blocks(struct dc *dc)
1559 {
1560 power_down_encoders(dc);
1561
1562 power_down_controllers(dc);
1563
1564 power_down_clock_sources(dc);
1565
1566 if (dc->fbc_compressor)
1567 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1568 }
1569
disable_vga_and_power_gate_all_controllers(struct dc * dc)1570 static void disable_vga_and_power_gate_all_controllers(
1571 struct dc *dc)
1572 {
1573 int i;
1574 struct timing_generator *tg;
1575 struct dc_context *ctx = dc->ctx;
1576
1577 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1578 tg = dc->res_pool->timing_generators[i];
1579
1580 if (tg->funcs->disable_vga)
1581 tg->funcs->disable_vga(tg);
1582 }
1583 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1584 /* Enable CLOCK gating for each pipe BEFORE controller
1585 * powergating. */
1586 enable_display_pipe_clock_gating(ctx,
1587 true);
1588
1589 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1590 dc->hwss.disable_plane(dc,
1591 &dc->current_state->res_ctx.pipe_ctx[i]);
1592 }
1593 }
1594
1595
get_edp_stream(struct dc_state * context)1596 static struct dc_stream_state *get_edp_stream(struct dc_state *context)
1597 {
1598 int i;
1599
1600 for (i = 0; i < context->stream_count; i++) {
1601 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1602 return context->streams[i];
1603 }
1604 return NULL;
1605 }
1606
get_edp_link_with_sink(struct dc * dc,struct dc_state * context)1607 static struct dc_link *get_edp_link_with_sink(
1608 struct dc *dc,
1609 struct dc_state *context)
1610 {
1611 int i;
1612 struct dc_link *link = NULL;
1613
1614 /* check if there is an eDP panel not in use */
1615 for (i = 0; i < dc->link_count; i++) {
1616 if (dc->links[i]->local_sink &&
1617 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1618 link = dc->links[i];
1619 break;
1620 }
1621 }
1622
1623 return link;
1624 }
1625
1626 /**
1627 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1628 * 1. Power down all DC HW blocks
1629 * 2. Disable VGA engine on all controllers
1630 * 3. Enable power gating for controller
1631 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1632 */
dce110_enable_accelerated_mode(struct dc * dc,struct dc_state * context)1633 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1634 {
1635 int i;
1636 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
1637 struct dc_link *edp_link = get_edp_link(dc);
1638 struct dc_stream_state *edp_stream = NULL;
1639 bool can_apply_edp_fast_boot = false;
1640 bool can_apply_seamless_boot = false;
1641 bool keep_edp_vdd_on = false;
1642 struct dce_hwseq *hws = dc->hwseq;
1643
1644 if (hws->funcs.init_pipes)
1645 hws->funcs.init_pipes(dc, context);
1646
1647 edp_stream = get_edp_stream(context);
1648
1649 // Check fastboot support, disable on DCE8 because of blank screens
1650 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1651 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1652 dc->ctx->dce_version != DCE_VERSION_8_3) {
1653
1654 // enable fastboot if backend is enabled on eDP
1655 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1656 /* Set optimization flag on eDP stream*/
1657 if (edp_stream && edp_link->link_status.link_active) {
1658 edp_stream->apply_edp_fast_boot_optimization = true;
1659 can_apply_edp_fast_boot = true;
1660 }
1661 }
1662
1663 // We are trying to enable eDP, don't power down VDD
1664 if (edp_stream)
1665 keep_edp_vdd_on = true;
1666 }
1667
1668 // Check seamless boot support
1669 for (i = 0; i < context->stream_count; i++) {
1670 if (context->streams[i]->apply_seamless_boot_optimization) {
1671 can_apply_seamless_boot = true;
1672 break;
1673 }
1674 }
1675
1676 /* eDP should not have stream in resume from S4 and so even with VBios post
1677 * it should get turned off
1678 */
1679 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1680 if (edp_link_with_sink && !keep_edp_vdd_on) {
1681 /*turn off backlight before DP_blank and encoder powered down*/
1682 hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1683 }
1684 /*resume from S3, no vbios posting, no need to power down again*/
1685 power_down_all_hw_blocks(dc);
1686 disable_vga_and_power_gate_all_controllers(dc);
1687 if (edp_link_with_sink && !keep_edp_vdd_on)
1688 dc->hwss.edp_power_control(edp_link_with_sink, false);
1689 }
1690 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1691 }
1692
compute_pstate_blackout_duration(struct bw_fixed blackout_duration,const struct dc_stream_state * stream)1693 static uint32_t compute_pstate_blackout_duration(
1694 struct bw_fixed blackout_duration,
1695 const struct dc_stream_state *stream)
1696 {
1697 uint32_t total_dest_line_time_ns;
1698 uint32_t pstate_blackout_duration_ns;
1699
1700 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1701
1702 total_dest_line_time_ns = 1000000UL *
1703 (stream->timing.h_total * 10) /
1704 stream->timing.pix_clk_100hz +
1705 pstate_blackout_duration_ns;
1706
1707 return total_dest_line_time_ns;
1708 }
1709
dce110_set_displaymarks(const struct dc * dc,struct dc_state * context)1710 static void dce110_set_displaymarks(
1711 const struct dc *dc,
1712 struct dc_state *context)
1713 {
1714 uint8_t i, num_pipes;
1715 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1716
1717 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1718 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1719 uint32_t total_dest_line_time_ns;
1720
1721 if (pipe_ctx->stream == NULL)
1722 continue;
1723
1724 total_dest_line_time_ns = compute_pstate_blackout_duration(
1725 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1726 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1727 pipe_ctx->plane_res.mi,
1728 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1729 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1730 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1731 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1732 total_dest_line_time_ns);
1733 if (i == underlay_idx) {
1734 num_pipes++;
1735 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1736 pipe_ctx->plane_res.mi,
1737 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1738 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1739 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1740 total_dest_line_time_ns);
1741 }
1742 num_pipes++;
1743 }
1744 }
1745
dce110_set_safe_displaymarks(struct resource_context * res_ctx,const struct resource_pool * pool)1746 void dce110_set_safe_displaymarks(
1747 struct resource_context *res_ctx,
1748 const struct resource_pool *pool)
1749 {
1750 int i;
1751 int underlay_idx = pool->underlay_pipe_index;
1752 struct dce_watermarks max_marks = {
1753 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1754 struct dce_watermarks nbp_marks = {
1755 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1756 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1757
1758 for (i = 0; i < MAX_PIPES; i++) {
1759 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1760 continue;
1761
1762 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1763 res_ctx->pipe_ctx[i].plane_res.mi,
1764 nbp_marks,
1765 max_marks,
1766 min_marks,
1767 max_marks,
1768 MAX_WATERMARK);
1769
1770 if (i == underlay_idx)
1771 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1772 res_ctx->pipe_ctx[i].plane_res.mi,
1773 nbp_marks,
1774 max_marks,
1775 max_marks,
1776 MAX_WATERMARK);
1777
1778 }
1779 }
1780
1781 /*******************************************************************************
1782 * Public functions
1783 ******************************************************************************/
1784
set_drr(struct pipe_ctx ** pipe_ctx,int num_pipes,unsigned int vmin,unsigned int vmax,unsigned int vmid,unsigned int vmid_frame_number)1785 static void set_drr(struct pipe_ctx **pipe_ctx,
1786 int num_pipes, unsigned int vmin, unsigned int vmax,
1787 unsigned int vmid, unsigned int vmid_frame_number)
1788 {
1789 int i = 0;
1790 struct drr_params params = {0};
1791 // DRR should set trigger event to monitor surface update event
1792 unsigned int event_triggers = 0x80;
1793 // Note DRR trigger events are generated regardless of whether num frames met.
1794 unsigned int num_frames = 2;
1795
1796 params.vertical_total_max = vmax;
1797 params.vertical_total_min = vmin;
1798
1799 /* TODO: If multiple pipes are to be supported, you need
1800 * some GSL stuff. Static screen triggers may be programmed differently
1801 * as well.
1802 */
1803 for (i = 0; i < num_pipes; i++) {
1804 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1805 pipe_ctx[i]->stream_res.tg, ¶ms);
1806
1807 if (vmax != 0 && vmin != 0)
1808 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1809 pipe_ctx[i]->stream_res.tg,
1810 event_triggers, num_frames);
1811 }
1812 }
1813
get_position(struct pipe_ctx ** pipe_ctx,int num_pipes,struct crtc_position * position)1814 static void get_position(struct pipe_ctx **pipe_ctx,
1815 int num_pipes,
1816 struct crtc_position *position)
1817 {
1818 int i = 0;
1819
1820 /* TODO: handle pipes > 1
1821 */
1822 for (i = 0; i < num_pipes; i++)
1823 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1824 }
1825
set_static_screen_control(struct pipe_ctx ** pipe_ctx,int num_pipes,const struct dc_static_screen_params * params)1826 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1827 int num_pipes, const struct dc_static_screen_params *params)
1828 {
1829 unsigned int i;
1830 unsigned int triggers = 0;
1831
1832 if (params->triggers.overlay_update)
1833 triggers |= 0x100;
1834 if (params->triggers.surface_update)
1835 triggers |= 0x80;
1836 if (params->triggers.cursor_update)
1837 triggers |= 0x2;
1838 if (params->triggers.force_trigger)
1839 triggers |= 0x1;
1840
1841 if (num_pipes) {
1842 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1843
1844 if (dc->fbc_compressor)
1845 triggers |= 0x84;
1846 }
1847
1848 for (i = 0; i < num_pipes; i++)
1849 pipe_ctx[i]->stream_res.tg->funcs->
1850 set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1851 triggers, params->num_frames);
1852 }
1853
1854 /*
1855 * Check if FBC can be enabled
1856 */
should_enable_fbc(struct dc * dc,struct dc_state * context,uint32_t * pipe_idx)1857 static bool should_enable_fbc(struct dc *dc,
1858 struct dc_state *context,
1859 uint32_t *pipe_idx)
1860 {
1861 uint32_t i;
1862 struct pipe_ctx *pipe_ctx = NULL;
1863 struct resource_context *res_ctx = &context->res_ctx;
1864 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1865
1866
1867 ASSERT(dc->fbc_compressor);
1868
1869 /* FBC memory should be allocated */
1870 if (!dc->ctx->fbc_gpu_addr)
1871 return false;
1872
1873 /* Only supports single display */
1874 if (context->stream_count != 1)
1875 return false;
1876
1877 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1878 if (res_ctx->pipe_ctx[i].stream) {
1879
1880 pipe_ctx = &res_ctx->pipe_ctx[i];
1881
1882 if (!pipe_ctx)
1883 continue;
1884
1885 /* fbc not applicable on underlay pipe */
1886 if (pipe_ctx->pipe_idx != underlay_idx) {
1887 *pipe_idx = i;
1888 break;
1889 }
1890 }
1891 }
1892
1893 if (i == dc->res_pool->pipe_count)
1894 return false;
1895
1896 if (!pipe_ctx->stream->link)
1897 return false;
1898
1899 /* Only supports eDP */
1900 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1901 return false;
1902
1903 /* PSR should not be enabled */
1904 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
1905 return false;
1906
1907 /* Nothing to compress */
1908 if (!pipe_ctx->plane_state)
1909 return false;
1910
1911 /* Only for non-linear tiling */
1912 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1913 return false;
1914
1915 return true;
1916 }
1917
1918 /*
1919 * Enable FBC
1920 */
enable_fbc(struct dc * dc,struct dc_state * context)1921 static void enable_fbc(
1922 struct dc *dc,
1923 struct dc_state *context)
1924 {
1925 uint32_t pipe_idx = 0;
1926
1927 if (should_enable_fbc(dc, context, &pipe_idx)) {
1928 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1929 struct compr_addr_and_pitch_params params = {0, 0, 0};
1930 struct compressor *compr = dc->fbc_compressor;
1931 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1932
1933 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1934 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1935 params.inst = pipe_ctx->stream_res.tg->inst;
1936 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1937
1938 compr->funcs->surface_address_and_pitch(compr, ¶ms);
1939 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1940
1941 compr->funcs->enable_fbc(compr, ¶ms);
1942 }
1943 }
1944
dce110_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)1945 static void dce110_reset_hw_ctx_wrap(
1946 struct dc *dc,
1947 struct dc_state *context)
1948 {
1949 int i;
1950
1951 /* Reset old context */
1952 /* look up the targets that have been removed since last commit */
1953 for (i = 0; i < MAX_PIPES; i++) {
1954 struct pipe_ctx *pipe_ctx_old =
1955 &dc->current_state->res_ctx.pipe_ctx[i];
1956 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1957
1958 /* Note: We need to disable output if clock sources change,
1959 * since bios does optimization and doesn't apply if changing
1960 * PHY when not already disabled.
1961 */
1962
1963 /* Skip underlay pipe since it will be handled in commit surface*/
1964 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1965 continue;
1966
1967 if (!pipe_ctx->stream ||
1968 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1969 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1970
1971 /* Disable if new stream is null. O/w, if stream is
1972 * disabled already, no need to disable again.
1973 */
1974 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
1975 core_link_disable_stream(pipe_ctx_old);
1976
1977 /* free acquired resources*/
1978 if (pipe_ctx_old->stream_res.audio) {
1979 /*disable az_endpoint*/
1980 pipe_ctx_old->stream_res.audio->funcs->
1981 az_disable(pipe_ctx_old->stream_res.audio);
1982
1983 /*free audio*/
1984 if (dc->caps.dynamic_audio == true) {
1985 /*we have to dynamic arbitrate the audio endpoints*/
1986 /*we free the resource, need reset is_audio_acquired*/
1987 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1988 pipe_ctx_old->stream_res.audio, false);
1989 pipe_ctx_old->stream_res.audio = NULL;
1990 }
1991 }
1992 }
1993
1994 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1995 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1996 dm_error("DC: failed to blank crtc!\n");
1997 BREAK_TO_DEBUGGER();
1998 }
1999 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2000 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2001 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2002
2003 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2004 dc->res_pool,
2005 old_clk))
2006 old_clk->funcs->cs_power_down(old_clk);
2007
2008 dc->hwss.disable_plane(dc, pipe_ctx_old);
2009
2010 pipe_ctx_old->stream = NULL;
2011 }
2012 }
2013 }
2014
dce110_setup_audio_dto(struct dc * dc,struct dc_state * context)2015 static void dce110_setup_audio_dto(
2016 struct dc *dc,
2017 struct dc_state *context)
2018 {
2019 int i;
2020
2021 /* program audio wall clock. use HDMI as clock source if HDMI
2022 * audio active. Otherwise, use DP as clock source
2023 * first, loop to find any HDMI audio, if not, loop find DP audio
2024 */
2025 /* Setup audio rate clock source */
2026 /* Issue:
2027 * Audio lag happened on DP monitor when unplug a HDMI monitor
2028 *
2029 * Cause:
2030 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2031 * is set to either dto0 or dto1, audio should work fine.
2032 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2033 * set to dto0 will cause audio lag.
2034 *
2035 * Solution:
2036 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2037 * find first available pipe with audio, setup audio wall DTO per topology
2038 * instead of per pipe.
2039 */
2040 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2041 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2042
2043 if (pipe_ctx->stream == NULL)
2044 continue;
2045
2046 if (pipe_ctx->top_pipe)
2047 continue;
2048 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2049 continue;
2050 if (pipe_ctx->stream_res.audio != NULL &&
2051 pipe_ctx->stream_res.audio->enabled == false) {
2052 struct audio_output audio_output;
2053
2054 build_audio_output(context, pipe_ctx, &audio_output);
2055
2056 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2057 pipe_ctx->stream_res.audio,
2058 pipe_ctx->stream->signal,
2059 &audio_output.crtc_info,
2060 &audio_output.pll_info);
2061 break;
2062 }
2063 }
2064
2065 /* no HDMI audio is found, try DP audio */
2066 if (i == dc->res_pool->pipe_count) {
2067 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2068 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2069
2070 if (pipe_ctx->stream == NULL)
2071 continue;
2072
2073 if (pipe_ctx->top_pipe)
2074 continue;
2075
2076 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2077 continue;
2078
2079 if (pipe_ctx->stream_res.audio != NULL &&
2080 pipe_ctx->stream_res.audio->enabled == false) {
2081 struct audio_output audio_output;
2082
2083 build_audio_output(context, pipe_ctx, &audio_output);
2084
2085 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2086 pipe_ctx->stream_res.audio,
2087 pipe_ctx->stream->signal,
2088 &audio_output.crtc_info,
2089 &audio_output.pll_info);
2090 break;
2091 }
2092 }
2093 }
2094 }
2095
dce110_apply_ctx_to_hw(struct dc * dc,struct dc_state * context)2096 enum dc_status dce110_apply_ctx_to_hw(
2097 struct dc *dc,
2098 struct dc_state *context)
2099 {
2100 struct dce_hwseq *hws = dc->hwseq;
2101 struct dc_bios *dcb = dc->ctx->dc_bios;
2102 enum dc_status status;
2103 int i;
2104
2105 /* Reset old context */
2106 /* look up the targets that have been removed since last commit */
2107 hws->funcs.reset_hw_ctx_wrap(dc, context);
2108
2109 /* Skip applying if no targets */
2110 if (context->stream_count <= 0)
2111 return DC_OK;
2112
2113 /* Apply new context */
2114 dcb->funcs->set_scratch_critical_state(dcb, true);
2115
2116 /* below is for real asic only */
2117 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2118 struct pipe_ctx *pipe_ctx_old =
2119 &dc->current_state->res_ctx.pipe_ctx[i];
2120 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2121
2122 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2123 continue;
2124
2125 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2126 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2127 dce_crtc_switch_to_clk_src(dc->hwseq,
2128 pipe_ctx->clock_source, i);
2129 continue;
2130 }
2131
2132 hws->funcs.enable_display_power_gating(
2133 dc, i, dc->ctx->dc_bios,
2134 PIPE_GATING_CONTROL_DISABLE);
2135 }
2136
2137 if (dc->fbc_compressor)
2138 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2139
2140 dce110_setup_audio_dto(dc, context);
2141
2142 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2143 struct pipe_ctx *pipe_ctx_old =
2144 &dc->current_state->res_ctx.pipe_ctx[i];
2145 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2146
2147 if (pipe_ctx->stream == NULL)
2148 continue;
2149
2150 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2151 pipe_ctx->stream->link->link_state_valid) {
2152 continue;
2153 }
2154
2155 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2156 continue;
2157
2158 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2159 continue;
2160
2161 status = apply_single_controller_ctx_to_hw(
2162 pipe_ctx,
2163 context,
2164 dc);
2165
2166 if (DC_OK != status)
2167 return status;
2168 }
2169
2170 if (dc->fbc_compressor)
2171 enable_fbc(dc, dc->current_state);
2172
2173 dcb->funcs->set_scratch_critical_state(dcb, false);
2174
2175 return DC_OK;
2176 }
2177
2178 /*******************************************************************************
2179 * Front End programming
2180 ******************************************************************************/
set_default_colors(struct pipe_ctx * pipe_ctx)2181 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2182 {
2183 struct default_adjustment default_adjust = { 0 };
2184
2185 default_adjust.force_hw_default = false;
2186 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2187 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2188 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2189 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2190
2191 /* display color depth */
2192 default_adjust.color_depth =
2193 pipe_ctx->stream->timing.display_color_depth;
2194
2195 /* Lb color depth */
2196 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2197
2198 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2199 pipe_ctx->plane_res.xfm, &default_adjust);
2200 }
2201
2202
2203 /*******************************************************************************
2204 * In order to turn on/off specific surface we will program
2205 * Blender + CRTC
2206 *
2207 * In case that we have two surfaces and they have a different visibility
2208 * we can't turn off the CRTC since it will turn off the entire display
2209 *
2210 * |----------------------------------------------- |
2211 * |bottom pipe|curr pipe | | |
2212 * |Surface |Surface | Blender | CRCT |
2213 * |visibility |visibility | Configuration| |
2214 * |------------------------------------------------|
2215 * | off | off | CURRENT_PIPE | blank |
2216 * | off | on | CURRENT_PIPE | unblank |
2217 * | on | off | OTHER_PIPE | unblank |
2218 * | on | on | BLENDING | unblank |
2219 * -------------------------------------------------|
2220 *
2221 ******************************************************************************/
program_surface_visibility(const struct dc * dc,struct pipe_ctx * pipe_ctx)2222 static void program_surface_visibility(const struct dc *dc,
2223 struct pipe_ctx *pipe_ctx)
2224 {
2225 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2226 bool blank_target = false;
2227
2228 if (pipe_ctx->bottom_pipe) {
2229
2230 /* For now we are supporting only two pipes */
2231 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2232
2233 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2234 if (pipe_ctx->plane_state->visible)
2235 blender_mode = BLND_MODE_BLENDING;
2236 else
2237 blender_mode = BLND_MODE_OTHER_PIPE;
2238
2239 } else if (!pipe_ctx->plane_state->visible)
2240 blank_target = true;
2241
2242 } else if (!pipe_ctx->plane_state->visible)
2243 blank_target = true;
2244
2245 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2246 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2247
2248 }
2249
program_gamut_remap(struct pipe_ctx * pipe_ctx)2250 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2251 {
2252 int i = 0;
2253 struct xfm_grph_csc_adjustment adjust;
2254 memset(&adjust, 0, sizeof(adjust));
2255 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2256
2257
2258 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2259 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2260
2261 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2262 adjust.temperature_matrix[i] =
2263 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2264 }
2265
2266 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2267 }
update_plane_addr(const struct dc * dc,struct pipe_ctx * pipe_ctx)2268 static void update_plane_addr(const struct dc *dc,
2269 struct pipe_ctx *pipe_ctx)
2270 {
2271 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2272
2273 if (plane_state == NULL)
2274 return;
2275
2276 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2277 pipe_ctx->plane_res.mi,
2278 &plane_state->address,
2279 plane_state->flip_immediate);
2280
2281 plane_state->status.requested_address = plane_state->address;
2282 }
2283
dce110_update_pending_status(struct pipe_ctx * pipe_ctx)2284 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2285 {
2286 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2287
2288 if (plane_state == NULL)
2289 return;
2290
2291 plane_state->status.is_flip_pending =
2292 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2293 pipe_ctx->plane_res.mi);
2294
2295 if (plane_state->status.is_flip_pending && !plane_state->visible)
2296 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2297
2298 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2299 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2300 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2301 plane_state->status.is_right_eye =\
2302 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2303 }
2304 }
2305
dce110_power_down(struct dc * dc)2306 void dce110_power_down(struct dc *dc)
2307 {
2308 power_down_all_hw_blocks(dc);
2309 disable_vga_and_power_gate_all_controllers(dc);
2310 }
2311
wait_for_reset_trigger_to_occur(struct dc_context * dc_ctx,struct timing_generator * tg)2312 static bool wait_for_reset_trigger_to_occur(
2313 struct dc_context *dc_ctx,
2314 struct timing_generator *tg)
2315 {
2316 bool rc = false;
2317
2318 /* To avoid endless loop we wait at most
2319 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2320 const uint32_t frames_to_wait_on_triggered_reset = 10;
2321 uint32_t i;
2322
2323 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2324
2325 if (!tg->funcs->is_counter_moving(tg)) {
2326 DC_ERROR("TG counter is not moving!\n");
2327 break;
2328 }
2329
2330 if (tg->funcs->did_triggered_reset_occur(tg)) {
2331 rc = true;
2332 /* usually occurs at i=1 */
2333 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2334 i);
2335 break;
2336 }
2337
2338 /* Wait for one frame. */
2339 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2340 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2341 }
2342
2343 if (false == rc)
2344 DC_ERROR("GSL: Timeout on reset trigger!\n");
2345
2346 return rc;
2347 }
2348
2349 /* Enable timing synchronization for a group of Timing Generators. */
dce110_enable_timing_synchronization(struct dc * dc,int group_index,int group_size,struct pipe_ctx * grouped_pipes[])2350 static void dce110_enable_timing_synchronization(
2351 struct dc *dc,
2352 int group_index,
2353 int group_size,
2354 struct pipe_ctx *grouped_pipes[])
2355 {
2356 struct dc_context *dc_ctx = dc->ctx;
2357 struct dcp_gsl_params gsl_params = { 0 };
2358 int i;
2359
2360 DC_SYNC_INFO("GSL: Setting-up...\n");
2361
2362 /* Designate a single TG in the group as a master.
2363 * Since HW doesn't care which one, we always assign
2364 * the 1st one in the group. */
2365 gsl_params.gsl_group = 0;
2366 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2367
2368 for (i = 0; i < group_size; i++)
2369 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2370 grouped_pipes[i]->stream_res.tg, &gsl_params);
2371
2372 /* Reset slave controllers on master VSync */
2373 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2374
2375 for (i = 1 /* skip the master */; i < group_size; i++)
2376 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2377 grouped_pipes[i]->stream_res.tg,
2378 gsl_params.gsl_group);
2379
2380 for (i = 1 /* skip the master */; i < group_size; i++) {
2381 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2382 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2383 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2384 grouped_pipes[i]->stream_res.tg);
2385 }
2386
2387 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2388 * is that the sync'ed displays will not drift out of sync over time*/
2389 DC_SYNC_INFO("GSL: Restoring register states.\n");
2390 for (i = 0; i < group_size; i++)
2391 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2392
2393 DC_SYNC_INFO("GSL: Set-up complete.\n");
2394 }
2395
dce110_enable_per_frame_crtc_position_reset(struct dc * dc,int group_size,struct pipe_ctx * grouped_pipes[])2396 static void dce110_enable_per_frame_crtc_position_reset(
2397 struct dc *dc,
2398 int group_size,
2399 struct pipe_ctx *grouped_pipes[])
2400 {
2401 struct dc_context *dc_ctx = dc->ctx;
2402 struct dcp_gsl_params gsl_params = { 0 };
2403 int i;
2404
2405 gsl_params.gsl_group = 0;
2406 gsl_params.gsl_master = 0;
2407
2408 for (i = 0; i < group_size; i++)
2409 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2410 grouped_pipes[i]->stream_res.tg, &gsl_params);
2411
2412 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2413
2414 for (i = 1; i < group_size; i++)
2415 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2416 grouped_pipes[i]->stream_res.tg,
2417 gsl_params.gsl_master,
2418 &grouped_pipes[i]->stream->triggered_crtc_reset);
2419
2420 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2421 for (i = 1; i < group_size; i++)
2422 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2423
2424 for (i = 0; i < group_size; i++)
2425 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2426
2427 }
2428
init_pipes(struct dc * dc,struct dc_state * context)2429 static void init_pipes(struct dc *dc, struct dc_state *context)
2430 {
2431 // Do nothing
2432 }
2433
init_hw(struct dc * dc)2434 static void init_hw(struct dc *dc)
2435 {
2436 int i;
2437 struct dc_bios *bp;
2438 struct transform *xfm;
2439 struct abm *abm;
2440 struct dmcu *dmcu;
2441 struct dce_hwseq *hws = dc->hwseq;
2442 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2443
2444 bp = dc->ctx->dc_bios;
2445 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2446 xfm = dc->res_pool->transforms[i];
2447 xfm->funcs->transform_reset(xfm);
2448
2449 hws->funcs.enable_display_power_gating(
2450 dc, i, bp,
2451 PIPE_GATING_CONTROL_INIT);
2452 hws->funcs.enable_display_power_gating(
2453 dc, i, bp,
2454 PIPE_GATING_CONTROL_DISABLE);
2455 hws->funcs.enable_display_pipe_clock_gating(
2456 dc->ctx,
2457 true);
2458 }
2459
2460 dce_clock_gating_power_up(dc->hwseq, false);
2461 /***************************************/
2462
2463 for (i = 0; i < dc->link_count; i++) {
2464 /****************************************/
2465 /* Power up AND update implementation according to the
2466 * required signal (which may be different from the
2467 * default signal on connector). */
2468 struct dc_link *link = dc->links[i];
2469
2470 link->link_enc->funcs->hw_init(link->link_enc);
2471 }
2472
2473 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2474 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2475
2476 tg->funcs->disable_vga(tg);
2477
2478 /* Blank controller using driver code instead of
2479 * command table. */
2480 tg->funcs->set_blank(tg, true);
2481 hwss_wait_for_blank_complete(tg);
2482 }
2483
2484 for (i = 0; i < dc->res_pool->audio_count; i++) {
2485 struct audio *audio = dc->res_pool->audios[i];
2486 audio->funcs->hw_init(audio);
2487 }
2488
2489 for (i = 0; i < dc->link_count; i++) {
2490 struct dc_link *link = dc->links[i];
2491
2492 if (link->panel_cntl)
2493 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2494 }
2495
2496 abm = dc->res_pool->abm;
2497 if (abm != NULL)
2498 abm->funcs->abm_init(abm, backlight);
2499
2500 dmcu = dc->res_pool->dmcu;
2501 if (dmcu != NULL && abm != NULL)
2502 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2503
2504 if (dc->fbc_compressor)
2505 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2506
2507 }
2508
2509
dce110_prepare_bandwidth(struct dc * dc,struct dc_state * context)2510 void dce110_prepare_bandwidth(
2511 struct dc *dc,
2512 struct dc_state *context)
2513 {
2514 struct clk_mgr *dccg = dc->clk_mgr;
2515
2516 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2517
2518 dccg->funcs->update_clocks(
2519 dccg,
2520 context,
2521 false);
2522 }
2523
dce110_optimize_bandwidth(struct dc * dc,struct dc_state * context)2524 void dce110_optimize_bandwidth(
2525 struct dc *dc,
2526 struct dc_state *context)
2527 {
2528 struct clk_mgr *dccg = dc->clk_mgr;
2529
2530 dce110_set_displaymarks(dc, context);
2531
2532 dccg->funcs->update_clocks(
2533 dccg,
2534 context,
2535 true);
2536 }
2537
dce110_program_front_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx)2538 static void dce110_program_front_end_for_pipe(
2539 struct dc *dc, struct pipe_ctx *pipe_ctx)
2540 {
2541 struct mem_input *mi = pipe_ctx->plane_res.mi;
2542 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2543 struct xfm_grph_csc_adjustment adjust;
2544 struct out_csc_color_matrix tbl_entry;
2545 unsigned int i;
2546 struct dce_hwseq *hws = dc->hwseq;
2547
2548 DC_LOGGER_INIT();
2549 memset(&tbl_entry, 0, sizeof(tbl_entry));
2550
2551 memset(&adjust, 0, sizeof(adjust));
2552 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2553
2554 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2555
2556 set_default_colors(pipe_ctx);
2557 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2558 == true) {
2559 tbl_entry.color_space =
2560 pipe_ctx->stream->output_color_space;
2561
2562 for (i = 0; i < 12; i++)
2563 tbl_entry.regval[i] =
2564 pipe_ctx->stream->csc_color_matrix.matrix[i];
2565
2566 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2567 (pipe_ctx->plane_res.xfm, &tbl_entry);
2568 }
2569
2570 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2571 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2572
2573 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2574 adjust.temperature_matrix[i] =
2575 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2576 }
2577
2578 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2579
2580 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2581
2582 program_scaler(dc, pipe_ctx);
2583
2584 mi->funcs->mem_input_program_surface_config(
2585 mi,
2586 plane_state->format,
2587 &plane_state->tiling_info,
2588 &plane_state->plane_size,
2589 plane_state->rotation,
2590 NULL,
2591 false);
2592 if (mi->funcs->set_blank)
2593 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2594
2595 if (dc->config.gpu_vm_support)
2596 mi->funcs->mem_input_program_pte_vm(
2597 pipe_ctx->plane_res.mi,
2598 plane_state->format,
2599 &plane_state->tiling_info,
2600 plane_state->rotation);
2601
2602 /* Moved programming gamma from dc to hwss */
2603 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2604 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2605 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2606 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2607
2608 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2609 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2610
2611 DC_LOG_SURFACE(
2612 "Pipe:%d %p: addr hi:0x%x, "
2613 "addr low:0x%x, "
2614 "src: %d, %d, %d,"
2615 " %d; dst: %d, %d, %d, %d;"
2616 "clip: %d, %d, %d, %d\n",
2617 pipe_ctx->pipe_idx,
2618 (void *) pipe_ctx->plane_state,
2619 pipe_ctx->plane_state->address.grph.addr.high_part,
2620 pipe_ctx->plane_state->address.grph.addr.low_part,
2621 pipe_ctx->plane_state->src_rect.x,
2622 pipe_ctx->plane_state->src_rect.y,
2623 pipe_ctx->plane_state->src_rect.width,
2624 pipe_ctx->plane_state->src_rect.height,
2625 pipe_ctx->plane_state->dst_rect.x,
2626 pipe_ctx->plane_state->dst_rect.y,
2627 pipe_ctx->plane_state->dst_rect.width,
2628 pipe_ctx->plane_state->dst_rect.height,
2629 pipe_ctx->plane_state->clip_rect.x,
2630 pipe_ctx->plane_state->clip_rect.y,
2631 pipe_ctx->plane_state->clip_rect.width,
2632 pipe_ctx->plane_state->clip_rect.height);
2633
2634 DC_LOG_SURFACE(
2635 "Pipe %d: width, height, x, y\n"
2636 "viewport:%d, %d, %d, %d\n"
2637 "recout: %d, %d, %d, %d\n",
2638 pipe_ctx->pipe_idx,
2639 pipe_ctx->plane_res.scl_data.viewport.width,
2640 pipe_ctx->plane_res.scl_data.viewport.height,
2641 pipe_ctx->plane_res.scl_data.viewport.x,
2642 pipe_ctx->plane_res.scl_data.viewport.y,
2643 pipe_ctx->plane_res.scl_data.recout.width,
2644 pipe_ctx->plane_res.scl_data.recout.height,
2645 pipe_ctx->plane_res.scl_data.recout.x,
2646 pipe_ctx->plane_res.scl_data.recout.y);
2647 }
2648
dce110_apply_ctx_for_surface(struct dc * dc,const struct dc_stream_state * stream,int num_planes,struct dc_state * context)2649 static void dce110_apply_ctx_for_surface(
2650 struct dc *dc,
2651 const struct dc_stream_state *stream,
2652 int num_planes,
2653 struct dc_state *context)
2654 {
2655 int i;
2656
2657 if (num_planes == 0)
2658 return;
2659
2660 if (dc->fbc_compressor)
2661 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2662
2663 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2664 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2665
2666 if (pipe_ctx->stream != stream)
2667 continue;
2668
2669 /* Need to allocate mem before program front end for Fiji */
2670 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2671 pipe_ctx->plane_res.mi,
2672 pipe_ctx->stream->timing.h_total,
2673 pipe_ctx->stream->timing.v_total,
2674 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2675 context->stream_count);
2676
2677 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2678
2679 dc->hwss.update_plane_addr(dc, pipe_ctx);
2680
2681 program_surface_visibility(dc, pipe_ctx);
2682
2683 }
2684
2685 if (dc->fbc_compressor)
2686 enable_fbc(dc, context);
2687 }
2688
dce110_post_unlock_program_front_end(struct dc * dc,struct dc_state * context)2689 static void dce110_post_unlock_program_front_end(
2690 struct dc *dc,
2691 struct dc_state *context)
2692 {
2693 }
2694
dce110_power_down_fe(struct dc * dc,struct pipe_ctx * pipe_ctx)2695 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2696 {
2697 struct dce_hwseq *hws = dc->hwseq;
2698 int fe_idx = pipe_ctx->plane_res.mi ?
2699 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2700
2701 /* Do not power down fe when stream is active on dce*/
2702 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2703 return;
2704
2705 hws->funcs.enable_display_power_gating(
2706 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2707
2708 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2709 dc->res_pool->transforms[fe_idx]);
2710 }
2711
dce110_wait_for_mpcc_disconnect(struct dc * dc,struct resource_pool * res_pool,struct pipe_ctx * pipe_ctx)2712 static void dce110_wait_for_mpcc_disconnect(
2713 struct dc *dc,
2714 struct resource_pool *res_pool,
2715 struct pipe_ctx *pipe_ctx)
2716 {
2717 /* do nothing*/
2718 }
2719
program_output_csc(struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)2720 static void program_output_csc(struct dc *dc,
2721 struct pipe_ctx *pipe_ctx,
2722 enum dc_color_space colorspace,
2723 uint16_t *matrix,
2724 int opp_id)
2725 {
2726 int i;
2727 struct out_csc_color_matrix tbl_entry;
2728
2729 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2730 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2731
2732 for (i = 0; i < 12; i++)
2733 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2734
2735 tbl_entry.color_space = color_space;
2736
2737 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2738 pipe_ctx->plane_res.xfm, &tbl_entry);
2739 }
2740 }
2741
dce110_set_cursor_position(struct pipe_ctx * pipe_ctx)2742 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2743 {
2744 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2745 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2746 struct mem_input *mi = pipe_ctx->plane_res.mi;
2747 struct dc_cursor_mi_param param = {
2748 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2749 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2750 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2751 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2752 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2753 .rotation = pipe_ctx->plane_state->rotation,
2754 .mirror = pipe_ctx->plane_state->horizontal_mirror
2755 };
2756
2757 /**
2758 * If the cursor's source viewport is clipped then we need to
2759 * translate the cursor to appear in the correct position on
2760 * the screen.
2761 *
2762 * This translation isn't affected by scaling so it needs to be
2763 * done *after* we adjust the position for the scale factor.
2764 *
2765 * This is only done by opt-in for now since there are still
2766 * some usecases like tiled display that might enable the
2767 * cursor on both streams while expecting dc to clip it.
2768 */
2769 if (pos_cpy.translate_by_source) {
2770 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2771 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2772 }
2773
2774 if (pipe_ctx->plane_state->address.type
2775 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2776 pos_cpy.enable = false;
2777
2778 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2779 pos_cpy.enable = false;
2780
2781 if (ipp->funcs->ipp_cursor_set_position)
2782 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
2783 if (mi->funcs->set_cursor_position)
2784 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
2785 }
2786
dce110_set_cursor_attribute(struct pipe_ctx * pipe_ctx)2787 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2788 {
2789 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2790
2791 if (pipe_ctx->plane_res.ipp &&
2792 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2793 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2794 pipe_ctx->plane_res.ipp, attributes);
2795
2796 if (pipe_ctx->plane_res.mi &&
2797 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2798 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2799 pipe_ctx->plane_res.mi, attributes);
2800
2801 if (pipe_ctx->plane_res.xfm &&
2802 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2803 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2804 pipe_ctx->plane_res.xfm, attributes);
2805 }
2806
dce110_set_backlight_level(struct pipe_ctx * pipe_ctx,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp)2807 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2808 uint32_t backlight_pwm_u16_16,
2809 uint32_t frame_ramp)
2810 {
2811 struct dc_link *link = pipe_ctx->stream->link;
2812 struct dc *dc = link->ctx->dc;
2813 struct abm *abm = pipe_ctx->stream_res.abm;
2814 struct panel_cntl *panel_cntl = link->panel_cntl;
2815 struct dmcu *dmcu = dc->res_pool->dmcu;
2816 bool fw_set_brightness = true;
2817 /* DMCU -1 for all controller id values,
2818 * therefore +1 here
2819 */
2820 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2821
2822 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2823 return false;
2824
2825 if (dmcu)
2826 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2827
2828 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2829 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2830 else
2831 abm->funcs->set_backlight_level_pwm(
2832 abm,
2833 backlight_pwm_u16_16,
2834 frame_ramp,
2835 controller_id,
2836 link->panel_cntl->inst);
2837
2838 return true;
2839 }
2840
dce110_set_abm_immediate_disable(struct pipe_ctx * pipe_ctx)2841 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2842 {
2843 struct abm *abm = pipe_ctx->stream_res.abm;
2844 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2845
2846 if (abm)
2847 abm->funcs->set_abm_immediate_disable(abm,
2848 pipe_ctx->stream->link->panel_cntl->inst);
2849
2850 if (panel_cntl)
2851 panel_cntl->funcs->store_backlight_level(panel_cntl);
2852 }
2853
dce110_set_pipe(struct pipe_ctx * pipe_ctx)2854 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
2855 {
2856 struct abm *abm = pipe_ctx->stream_res.abm;
2857 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2858 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
2859
2860 if (abm && panel_cntl)
2861 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
2862 }
2863
2864 static const struct hw_sequencer_funcs dce110_funcs = {
2865 .program_gamut_remap = program_gamut_remap,
2866 .program_output_csc = program_output_csc,
2867 .init_hw = init_hw,
2868 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2869 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2870 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
2871 .update_plane_addr = update_plane_addr,
2872 .update_pending_status = dce110_update_pending_status,
2873 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2874 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2875 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2876 .update_info_frame = dce110_update_info_frame,
2877 .enable_stream = dce110_enable_stream,
2878 .disable_stream = dce110_disable_stream,
2879 .unblank_stream = dce110_unblank_stream,
2880 .blank_stream = dce110_blank_stream,
2881 .enable_audio_stream = dce110_enable_audio_stream,
2882 .disable_audio_stream = dce110_disable_audio_stream,
2883 .disable_plane = dce110_power_down_fe,
2884 .pipe_control_lock = dce_pipe_control_lock,
2885 .interdependent_update_lock = NULL,
2886 .cursor_lock = dce_pipe_control_lock,
2887 .prepare_bandwidth = dce110_prepare_bandwidth,
2888 .optimize_bandwidth = dce110_optimize_bandwidth,
2889 .set_drr = set_drr,
2890 .get_position = get_position,
2891 .set_static_screen_control = set_static_screen_control,
2892 .setup_stereo = NULL,
2893 .set_avmute = dce110_set_avmute,
2894 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2895 .edp_backlight_control = dce110_edp_backlight_control,
2896 .edp_power_control = dce110_edp_power_control,
2897 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
2898 .set_cursor_position = dce110_set_cursor_position,
2899 .set_cursor_attribute = dce110_set_cursor_attribute,
2900 .set_backlight_level = dce110_set_backlight_level,
2901 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
2902 .set_pipe = dce110_set_pipe,
2903 };
2904
2905 static const struct hwseq_private_funcs dce110_private_funcs = {
2906 .init_pipes = init_pipes,
2907 .update_plane_addr = update_plane_addr,
2908 .set_input_transfer_func = dce110_set_input_transfer_func,
2909 .set_output_transfer_func = dce110_set_output_transfer_func,
2910 .power_down = dce110_power_down,
2911 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2912 .enable_display_power_gating = dce110_enable_display_power_gating,
2913 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2914 .enable_stream_timing = dce110_enable_stream_timing,
2915 .disable_stream_gating = NULL,
2916 .enable_stream_gating = NULL,
2917 .edp_backlight_control = dce110_edp_backlight_control,
2918 };
2919
dce110_hw_sequencer_construct(struct dc * dc)2920 void dce110_hw_sequencer_construct(struct dc *dc)
2921 {
2922 dc->hwss = dce110_funcs;
2923 dc->hwseq->funcs = dce110_private_funcs;
2924 }
2925
2926