1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6 #include "dpu_encoder_phys.h"
7 #include "dpu_hw_interrupts.h"
8 #include "dpu_core_irq.h"
9 #include "dpu_formats.h"
10 #include "dpu_trace.h"
11
12 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
17
18 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
23
24 #define to_dpu_encoder_phys_vid(x) \
25 container_of(x, struct dpu_encoder_phys_vid, base)
26
dpu_encoder_phys_vid_is_master(struct dpu_encoder_phys * phys_enc)27 static bool dpu_encoder_phys_vid_is_master(
28 struct dpu_encoder_phys *phys_enc)
29 {
30 bool ret = false;
31
32 if (phys_enc->split_role != ENC_ROLE_SLAVE)
33 ret = true;
34
35 return ret;
36 }
37
drm_mode_to_intf_timing_params(const struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct intf_timing_params * timing)38 static void drm_mode_to_intf_timing_params(
39 const struct dpu_encoder_phys *phys_enc,
40 const struct drm_display_mode *mode,
41 struct intf_timing_params *timing)
42 {
43 memset(timing, 0, sizeof(*timing));
44
45 if ((mode->htotal < mode->hsync_end)
46 || (mode->hsync_start < mode->hdisplay)
47 || (mode->vtotal < mode->vsync_end)
48 || (mode->vsync_start < mode->vdisplay)
49 || (mode->hsync_end < mode->hsync_start)
50 || (mode->vsync_end < mode->vsync_start)) {
51 DPU_ERROR(
52 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
53 mode->hsync_start, mode->hsync_end,
54 mode->htotal, mode->hdisplay);
55 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
56 mode->vsync_start, mode->vsync_end,
57 mode->vtotal, mode->vdisplay);
58 return;
59 }
60
61 /*
62 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
63 * Active Region Front Porch Sync Back Porch
64 * <-----------------><------------><-----><----------->
65 * <- [hv]display --->
66 * <--------- [hv]sync_start ------>
67 * <----------------- [hv]sync_end ------->
68 * <---------------------------- [hv]total ------------->
69 */
70 timing->width = mode->hdisplay; /* active width */
71 timing->height = mode->vdisplay; /* active height */
72 timing->xres = timing->width;
73 timing->yres = timing->height;
74 timing->h_back_porch = mode->htotal - mode->hsync_end;
75 timing->h_front_porch = mode->hsync_start - mode->hdisplay;
76 timing->v_back_porch = mode->vtotal - mode->vsync_end;
77 timing->v_front_porch = mode->vsync_start - mode->vdisplay;
78 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
79 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
80 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
81 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
82 timing->border_clr = 0;
83 timing->underflow_clr = 0xff;
84 timing->hsync_skew = mode->hskew;
85
86 /* DSI controller cannot handle active-low sync signals. */
87 if (phys_enc->hw_intf->cap->type == INTF_DSI) {
88 timing->hsync_polarity = 0;
89 timing->vsync_polarity = 0;
90 }
91
92 /*
93 * For edp only:
94 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
95 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
96 */
97 /*
98 * if (vid_enc->hw->cap->type == INTF_EDP) {
99 * display_v_start += mode->htotal - mode->hsync_start;
100 * display_v_end -= mode->hsync_start - mode->hdisplay;
101 * }
102 */
103 /* for DP/EDP, Shift timings to align it to bottom right */
104 if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
105 (phys_enc->hw_intf->cap->type == INTF_EDP)) {
106 timing->h_back_porch += timing->h_front_porch;
107 timing->h_front_porch = 0;
108 timing->v_back_porch += timing->v_front_porch;
109 timing->v_front_porch = 0;
110 }
111 }
112
get_horizontal_total(const struct intf_timing_params * timing)113 static u32 get_horizontal_total(const struct intf_timing_params *timing)
114 {
115 u32 active = timing->xres;
116 u32 inactive =
117 timing->h_back_porch + timing->h_front_porch +
118 timing->hsync_pulse_width;
119 return active + inactive;
120 }
121
get_vertical_total(const struct intf_timing_params * timing)122 static u32 get_vertical_total(const struct intf_timing_params *timing)
123 {
124 u32 active = timing->yres;
125 u32 inactive =
126 timing->v_back_porch + timing->v_front_porch +
127 timing->vsync_pulse_width;
128 return active + inactive;
129 }
130
131 /*
132 * programmable_fetch_get_num_lines:
133 * Number of fetch lines in vertical front porch
134 * @timing: Pointer to the intf timing information for the requested mode
135 *
136 * Returns the number of fetch lines in vertical front porch at which mdp
137 * can start fetching the next frame.
138 *
139 * Number of needed prefetch lines is anything that cannot be absorbed in the
140 * start of frame time (back porch + vsync pulse width).
141 *
142 * Some panels have very large VFP, however we only need a total number of
143 * lines based on the chip worst case latencies.
144 */
programmable_fetch_get_num_lines(struct dpu_encoder_phys * phys_enc,const struct intf_timing_params * timing)145 static u32 programmable_fetch_get_num_lines(
146 struct dpu_encoder_phys *phys_enc,
147 const struct intf_timing_params *timing)
148 {
149 u32 worst_case_needed_lines =
150 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
151 u32 start_of_frame_lines =
152 timing->v_back_porch + timing->vsync_pulse_width;
153 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
154 u32 actual_vfp_lines = 0;
155
156 /* Fetch must be outside active lines, otherwise undefined. */
157 if (start_of_frame_lines >= worst_case_needed_lines) {
158 DPU_DEBUG_VIDENC(phys_enc,
159 "prog fetch is not needed, large vbp+vsw\n");
160 actual_vfp_lines = 0;
161 } else if (timing->v_front_porch < needed_vfp_lines) {
162 /* Warn fetch needed, but not enough porch in panel config */
163 pr_warn_once
164 ("low vbp+vfp may lead to perf issues in some cases\n");
165 DPU_DEBUG_VIDENC(phys_enc,
166 "less vfp than fetch req, using entire vfp\n");
167 actual_vfp_lines = timing->v_front_porch;
168 } else {
169 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
170 actual_vfp_lines = needed_vfp_lines;
171 }
172
173 DPU_DEBUG_VIDENC(phys_enc,
174 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
175 timing->v_front_porch, timing->v_back_porch,
176 timing->vsync_pulse_width);
177 DPU_DEBUG_VIDENC(phys_enc,
178 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
179 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
180
181 return actual_vfp_lines;
182 }
183
184 /*
185 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
186 * the start of fetch into the vertical front porch for cases where the
187 * vsync pulse width and vertical back porch time is insufficient
188 *
189 * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
190 * HW layer requires VSYNC counter of first pixel of tgt VFP line.
191 *
192 * @timing: Pointer to the intf timing information for the requested mode
193 */
programmable_fetch_config(struct dpu_encoder_phys * phys_enc,const struct intf_timing_params * timing)194 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
195 const struct intf_timing_params *timing)
196 {
197 struct intf_prog_fetch f = { 0 };
198 u32 vfp_fetch_lines = 0;
199 u32 horiz_total = 0;
200 u32 vert_total = 0;
201 u32 vfp_fetch_start_vsync_counter = 0;
202 unsigned long lock_flags;
203
204 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
205 return;
206
207 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
208 if (vfp_fetch_lines) {
209 vert_total = get_vertical_total(timing);
210 horiz_total = get_horizontal_total(timing);
211 vfp_fetch_start_vsync_counter =
212 (vert_total - vfp_fetch_lines) * horiz_total + 1;
213 f.enable = 1;
214 f.fetch_start = vfp_fetch_start_vsync_counter;
215 }
216
217 DPU_DEBUG_VIDENC(phys_enc,
218 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
219 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
220
221 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
222 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
223 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
224 }
225
dpu_encoder_phys_vid_mode_fixup(struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)226 static bool dpu_encoder_phys_vid_mode_fixup(
227 struct dpu_encoder_phys *phys_enc,
228 const struct drm_display_mode *mode,
229 struct drm_display_mode *adj_mode)
230 {
231 DPU_DEBUG_VIDENC(phys_enc, "\n");
232
233 /*
234 * Modifying mode has consequences when the mode comes back to us
235 */
236 return true;
237 }
238
dpu_encoder_phys_vid_setup_timing_engine(struct dpu_encoder_phys * phys_enc)239 static void dpu_encoder_phys_vid_setup_timing_engine(
240 struct dpu_encoder_phys *phys_enc)
241 {
242 struct drm_display_mode mode;
243 struct intf_timing_params timing_params = { 0 };
244 const struct dpu_format *fmt = NULL;
245 u32 fmt_fourcc = DRM_FORMAT_RGB888;
246 unsigned long lock_flags;
247 struct dpu_hw_intf_cfg intf_cfg = { 0 };
248
249 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
250 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
251 return;
252 }
253
254 mode = phys_enc->cached_mode;
255 if (!phys_enc->hw_intf->ops.setup_timing_gen) {
256 DPU_ERROR("timing engine setup is not supported\n");
257 return;
258 }
259
260 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
261 drm_mode_debug_printmodeline(&mode);
262
263 if (phys_enc->split_role != ENC_ROLE_SOLO) {
264 mode.hdisplay >>= 1;
265 mode.htotal >>= 1;
266 mode.hsync_start >>= 1;
267 mode.hsync_end >>= 1;
268
269 DPU_DEBUG_VIDENC(phys_enc,
270 "split_role %d, halve horizontal %d %d %d %d\n",
271 phys_enc->split_role,
272 mode.hdisplay, mode.htotal,
273 mode.hsync_start, mode.hsync_end);
274 }
275
276 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
277
278 fmt = dpu_get_dpu_format(fmt_fourcc);
279 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
280
281 intf_cfg.intf = phys_enc->hw_intf->idx;
282 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
283 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
284 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
285
286 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
287 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
288 &timing_params, fmt);
289 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
290
291 /* setup which pp blk will connect to this intf */
292 if (phys_enc->hw_intf->ops.bind_pingpong_blk)
293 phys_enc->hw_intf->ops.bind_pingpong_blk(
294 phys_enc->hw_intf,
295 true,
296 phys_enc->hw_pp->idx);
297
298 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
299
300 programmable_fetch_config(phys_enc, &timing_params);
301 }
302
dpu_encoder_phys_vid_vblank_irq(void * arg,int irq_idx)303 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
304 {
305 struct dpu_encoder_phys *phys_enc = arg;
306 struct dpu_hw_ctl *hw_ctl;
307 unsigned long lock_flags;
308 u32 flush_register = 0;
309
310 hw_ctl = phys_enc->hw_ctl;
311
312 DPU_ATRACE_BEGIN("vblank_irq");
313
314 if (phys_enc->parent_ops->handle_vblank_virt)
315 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
316 phys_enc);
317
318 atomic_read(&phys_enc->pending_kickoff_cnt);
319
320 /*
321 * only decrement the pending flush count if we've actually flushed
322 * hardware. due to sw irq latency, vblank may have already happened
323 * so we need to double-check with hw that it accepted the flush bits
324 */
325 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
326 if (hw_ctl->ops.get_flush_register)
327 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
328
329 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
330 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
331 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
332
333 /* Signal any waiting atomic commit thread */
334 wake_up_all(&phys_enc->pending_kickoff_wq);
335
336 phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc,
337 DPU_ENCODER_FRAME_EVENT_DONE);
338
339 DPU_ATRACE_END("vblank_irq");
340 }
341
dpu_encoder_phys_vid_underrun_irq(void * arg,int irq_idx)342 static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
343 {
344 struct dpu_encoder_phys *phys_enc = arg;
345
346 if (phys_enc->parent_ops->handle_underrun_virt)
347 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
348 phys_enc);
349 }
350
dpu_encoder_phys_vid_needs_single_flush(struct dpu_encoder_phys * phys_enc)351 static bool dpu_encoder_phys_vid_needs_single_flush(
352 struct dpu_encoder_phys *phys_enc)
353 {
354 return phys_enc->split_role != ENC_ROLE_SOLO;
355 }
356
_dpu_encoder_phys_vid_setup_irq_hw_idx(struct dpu_encoder_phys * phys_enc)357 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
358 struct dpu_encoder_phys *phys_enc)
359 {
360 struct dpu_encoder_irq *irq;
361
362 /*
363 * Initialize irq->hw_idx only when irq is not registered.
364 * Prevent invalidating irq->irq_idx as modeset may be
365 * called many times during dfps.
366 */
367
368 irq = &phys_enc->irq[INTR_IDX_VSYNC];
369 if (irq->irq_idx < 0)
370 irq->hw_idx = phys_enc->intf_idx;
371
372 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
373 if (irq->irq_idx < 0)
374 irq->hw_idx = phys_enc->intf_idx;
375 }
376
dpu_encoder_phys_vid_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)377 static void dpu_encoder_phys_vid_mode_set(
378 struct dpu_encoder_phys *phys_enc,
379 struct drm_display_mode *mode,
380 struct drm_display_mode *adj_mode)
381 {
382 if (adj_mode) {
383 phys_enc->cached_mode = *adj_mode;
384 drm_mode_debug_printmodeline(adj_mode);
385 DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
386 }
387
388 _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
389 }
390
dpu_encoder_phys_vid_control_vblank_irq(struct dpu_encoder_phys * phys_enc,bool enable)391 static int dpu_encoder_phys_vid_control_vblank_irq(
392 struct dpu_encoder_phys *phys_enc,
393 bool enable)
394 {
395 int ret = 0;
396 int refcount;
397
398 refcount = atomic_read(&phys_enc->vblank_refcount);
399
400 /* Slave encoders don't report vblank */
401 if (!dpu_encoder_phys_vid_is_master(phys_enc))
402 goto end;
403
404 /* protect against negative */
405 if (!enable && refcount == 0) {
406 ret = -EINVAL;
407 goto end;
408 }
409
410 DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
411 atomic_read(&phys_enc->vblank_refcount));
412
413 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
414 ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
415 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
416 ret = dpu_encoder_helper_unregister_irq(phys_enc,
417 INTR_IDX_VSYNC);
418
419 end:
420 if (ret) {
421 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
422 DRMID(phys_enc->parent),
423 phys_enc->hw_intf->idx - INTF_0, ret, enable,
424 refcount);
425 }
426 return ret;
427 }
428
dpu_encoder_phys_vid_enable(struct dpu_encoder_phys * phys_enc)429 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
430 {
431 struct dpu_hw_ctl *ctl;
432 u32 flush_mask = 0;
433 u32 intf_flush_mask = 0;
434
435 ctl = phys_enc->hw_ctl;
436
437 DPU_DEBUG_VIDENC(phys_enc, "\n");
438
439 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
440 return;
441
442 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
443
444 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
445
446 /*
447 * For single flush cases (dual-ctl or pp-split), skip setting the
448 * flush bit for the slave intf, since both intfs use same ctl
449 * and HW will only flush the master.
450 */
451 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
452 !dpu_encoder_phys_vid_is_master(phys_enc))
453 goto skip_flush;
454
455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
456 ctl->ops.update_pending_flush(ctl, flush_mask);
457
458 if (ctl->ops.get_bitmask_active_intf)
459 ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
460 phys_enc->hw_intf->idx);
461
462 if (ctl->ops.update_pending_intf_flush)
463 ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
464
465 skip_flush:
466 DPU_DEBUG_VIDENC(phys_enc,
467 "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
468 ctl->idx - CTL_0, flush_mask, intf_flush_mask);
469
470
471 /* ctl_flush & timing engine enable will be triggered by framework */
472 if (phys_enc->enable_state == DPU_ENC_DISABLED)
473 phys_enc->enable_state = DPU_ENC_ENABLING;
474 }
475
dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys * phys_enc)476 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
477 {
478 DPU_DEBUG_VIDENC(phys_enc, "\n");
479 kfree(phys_enc);
480 }
481
dpu_encoder_phys_vid_get_hw_resources(struct dpu_encoder_phys * phys_enc,struct dpu_encoder_hw_resources * hw_res)482 static void dpu_encoder_phys_vid_get_hw_resources(
483 struct dpu_encoder_phys *phys_enc,
484 struct dpu_encoder_hw_resources *hw_res)
485 {
486 hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
487 }
488
dpu_encoder_phys_vid_wait_for_vblank(struct dpu_encoder_phys * phys_enc)489 static int dpu_encoder_phys_vid_wait_for_vblank(
490 struct dpu_encoder_phys *phys_enc)
491 {
492 struct dpu_encoder_wait_info wait_info;
493 int ret;
494
495 wait_info.wq = &phys_enc->pending_kickoff_wq;
496 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
497 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
498
499 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
500 return 0;
501 }
502
503 /* Wait for kickoff to complete */
504 ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
505 &wait_info);
506
507 if (ret == -ETIMEDOUT) {
508 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
509 }
510
511 return ret;
512 }
513
dpu_encoder_phys_vid_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)514 static int dpu_encoder_phys_vid_wait_for_commit_done(
515 struct dpu_encoder_phys *phys_enc)
516 {
517 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
518 int ret;
519
520 if (!hw_ctl)
521 return 0;
522
523 ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
524 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
525 msecs_to_jiffies(50));
526 if (ret <= 0) {
527 DPU_ERROR("vblank timeout\n");
528 return -ETIMEDOUT;
529 }
530
531 return 0;
532 }
533
dpu_encoder_phys_vid_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)534 static void dpu_encoder_phys_vid_prepare_for_kickoff(
535 struct dpu_encoder_phys *phys_enc)
536 {
537 struct dpu_hw_ctl *ctl;
538 int rc;
539
540 ctl = phys_enc->hw_ctl;
541 if (!ctl->ops.wait_reset_status)
542 return;
543
544 /*
545 * hw supports hardware initiated ctl reset, so before we kickoff a new
546 * frame, need to check and wait for hw initiated ctl reset completion
547 */
548 rc = ctl->ops.wait_reset_status(ctl);
549 if (rc) {
550 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
551 ctl->idx, rc);
552 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
553 }
554 }
555
dpu_encoder_phys_vid_disable(struct dpu_encoder_phys * phys_enc)556 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
557 {
558 unsigned long lock_flags;
559 int ret;
560
561 if (!phys_enc->parent || !phys_enc->parent->dev) {
562 DPU_ERROR("invalid encoder/device\n");
563 return;
564 }
565
566 if (!phys_enc->hw_intf) {
567 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
568 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
569 return;
570 }
571
572 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
573 return;
574
575 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
576 DPU_ERROR("already disabled\n");
577 return;
578 }
579
580 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
581 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
582 if (dpu_encoder_phys_vid_is_master(phys_enc))
583 dpu_encoder_phys_inc_pending(phys_enc);
584 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
585
586 /*
587 * Wait for a vsync so we know the ENABLE=0 latched before
588 * the (connector) source of the vsync's gets disabled,
589 * otherwise we end up in a funny state if we re-enable
590 * before the disable latches, which results that some of
591 * the settings changes for the new modeset (like new
592 * scanout buffer) don't latch properly..
593 */
594 if (dpu_encoder_phys_vid_is_master(phys_enc)) {
595 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
596 if (ret) {
597 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
598 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
599 DRMID(phys_enc->parent),
600 phys_enc->hw_intf->idx - INTF_0, ret);
601 }
602 }
603
604 phys_enc->enable_state = DPU_ENC_DISABLED;
605 }
606
dpu_encoder_phys_vid_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)607 static void dpu_encoder_phys_vid_handle_post_kickoff(
608 struct dpu_encoder_phys *phys_enc)
609 {
610 unsigned long lock_flags;
611
612 /*
613 * Video mode must flush CTL before enabling timing engine
614 * Video encoders need to turn on their interfaces now
615 */
616 if (phys_enc->enable_state == DPU_ENC_ENABLING) {
617 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
618 phys_enc->hw_intf->idx - INTF_0);
619 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
620 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
621 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
622 phys_enc->enable_state = DPU_ENC_ENABLED;
623 }
624 }
625
dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys * phys_enc,bool enable)626 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
627 bool enable)
628 {
629 int ret;
630
631 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
632 phys_enc->hw_intf->idx - INTF_0,
633 enable,
634 atomic_read(&phys_enc->vblank_refcount));
635
636 if (enable) {
637 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
638 if (ret)
639 return;
640
641 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
642 } else {
643 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
644 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
645 }
646 }
647
dpu_encoder_phys_vid_get_line_count(struct dpu_encoder_phys * phys_enc)648 static int dpu_encoder_phys_vid_get_line_count(
649 struct dpu_encoder_phys *phys_enc)
650 {
651 if (!dpu_encoder_phys_vid_is_master(phys_enc))
652 return -EINVAL;
653
654 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
655 return -EINVAL;
656
657 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
658 }
659
dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops * ops)660 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
661 {
662 ops->is_master = dpu_encoder_phys_vid_is_master;
663 ops->mode_set = dpu_encoder_phys_vid_mode_set;
664 ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup;
665 ops->enable = dpu_encoder_phys_vid_enable;
666 ops->disable = dpu_encoder_phys_vid_disable;
667 ops->destroy = dpu_encoder_phys_vid_destroy;
668 ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;
669 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
670 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
671 ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
672 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
673 ops->irq_control = dpu_encoder_phys_vid_irq_control;
674 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
675 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
676 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
677 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
678 }
679
dpu_encoder_phys_vid_init(struct dpu_enc_phys_init_params * p)680 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
681 struct dpu_enc_phys_init_params *p)
682 {
683 struct dpu_encoder_phys *phys_enc = NULL;
684 struct dpu_encoder_irq *irq;
685 int i, ret = 0;
686
687 if (!p) {
688 ret = -EINVAL;
689 goto fail;
690 }
691
692 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
693 if (!phys_enc) {
694 ret = -ENOMEM;
695 goto fail;
696 }
697
698 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
699 phys_enc->intf_idx = p->intf_idx;
700
701 DPU_DEBUG_VIDENC(phys_enc, "\n");
702
703 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
704 phys_enc->parent = p->parent;
705 phys_enc->parent_ops = p->parent_ops;
706 phys_enc->dpu_kms = p->dpu_kms;
707 phys_enc->split_role = p->split_role;
708 phys_enc->intf_mode = INTF_MODE_VIDEO;
709 phys_enc->enc_spinlock = p->enc_spinlock;
710 for (i = 0; i < INTR_IDX_MAX; i++) {
711 irq = &phys_enc->irq[i];
712 INIT_LIST_HEAD(&irq->cb.list);
713 irq->irq_idx = -EINVAL;
714 irq->hw_idx = -EINVAL;
715 irq->cb.arg = phys_enc;
716 }
717
718 irq = &phys_enc->irq[INTR_IDX_VSYNC];
719 irq->name = "vsync_irq";
720 irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
721 irq->intr_idx = INTR_IDX_VSYNC;
722 irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
723
724 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
725 irq->name = "underrun";
726 irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
727 irq->intr_idx = INTR_IDX_UNDERRUN;
728 irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
729
730 atomic_set(&phys_enc->vblank_refcount, 0);
731 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
732 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
733 phys_enc->enable_state = DPU_ENC_DISABLED;
734
735 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
736
737 return phys_enc;
738
739 fail:
740 DPU_ERROR("failed to create encoder\n");
741 if (phys_enc)
742 dpu_encoder_phys_vid_destroy(phys_enc);
743
744 return ERR_PTR(ret);
745 }
746