1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
37
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
44
45 #include "drm_crtc_internal.h"
46
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
50
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
54
55 /*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 /* Force 8bpc */
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 /* Force 12bpc */
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 /* Force 6bpc */
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 /* Force 10bpc */
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95 };
96
97 #define LEVEL_DMT 0
98 #define LEVEL_GTF 1
99 #define LEVEL_GTF2 2
100 #define LEVEL_CVT 3
101
102 static const struct edid_quirk {
103 char vendor[4];
104 int product_id;
105 u32 quirks;
106 } edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
152
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
161
162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
170
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
193
194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
199
200 /* Windows Mixed Reality Headsets */
201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209
210 /* Sony PlayStation VR Headset */
211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212
213 /* Sensics VR Headsets */
214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215
216 /* OSVR HDK and HDK2 VR Headsets */
217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
218 };
219
220 /*
221 * Autogenerated from the DMT spec.
222 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 */
224 static const struct drm_display_mode drm_dmt_modes[] = {
225 /* 0x01 - 640x350@85Hz */
226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 350, 382, 385, 445, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 0x02 - 640x400@85Hz */
230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
231 736, 832, 0, 400, 401, 404, 445, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x03 - 720x400@85Hz */
234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
235 828, 936, 0, 400, 401, 404, 446, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x04 - 640x480@60Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
239 752, 800, 0, 480, 490, 492, 525, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x05 - 640x480@72Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
243 704, 832, 0, 480, 489, 492, 520, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x06 - 640x480@75Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
247 720, 840, 0, 480, 481, 484, 500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x07 - 640x480@85Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
251 752, 832, 0, 480, 481, 484, 509, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x08 - 800x600@56Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
255 896, 1024, 0, 600, 601, 603, 625, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x09 - 800x600@60Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
259 968, 1056, 0, 600, 601, 605, 628, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0a - 800x600@72Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
263 976, 1040, 0, 600, 637, 643, 666, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0b - 800x600@75Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
267 896, 1056, 0, 600, 601, 604, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0c - 800x600@85Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
271 896, 1048, 0, 600, 601, 604, 631, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0d - 800x600@120Hz RB */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
275 880, 960, 0, 600, 603, 607, 636, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
277 /* 0x0e - 848x480@60Hz */
278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
279 976, 1088, 0, 480, 486, 494, 517, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0f - 1024x768@43Hz, interlace */
282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
283 1208, 1264, 0, 768, 768, 776, 817, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
285 DRM_MODE_FLAG_INTERLACE) },
286 /* 0x10 - 1024x768@60Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
288 1184, 1344, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x11 - 1024x768@70Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
292 1184, 1328, 0, 768, 771, 777, 806, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x12 - 1024x768@75Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
296 1136, 1312, 0, 768, 769, 772, 800, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x13 - 1024x768@85Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
300 1168, 1376, 0, 768, 769, 772, 808, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x14 - 1024x768@120Hz RB */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
304 1104, 1184, 0, 768, 771, 775, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x15 - 1152x864@75Hz */
307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
308 1344, 1600, 0, 864, 865, 868, 900, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x55 - 1280x720@60Hz */
311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
312 1430, 1650, 0, 720, 725, 730, 750, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x16 - 1280x768@60Hz RB */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 790, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x17 - 1280x768@60Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
320 1472, 1664, 0, 768, 771, 778, 798, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x18 - 1280x768@75Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
324 1488, 1696, 0, 768, 771, 778, 805, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x19 - 1280x768@85Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
328 1496, 1712, 0, 768, 771, 778, 809, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x1a - 1280x768@120Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1b - 1280x800@60Hz RB */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 823, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x1c - 1280x800@60Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
340 1480, 1680, 0, 800, 803, 809, 831, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1d - 1280x800@75Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
344 1488, 1696, 0, 800, 803, 809, 838, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1e - 1280x800@85Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
348 1496, 1712, 0, 800, 803, 809, 843, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1f - 1280x800@120Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 847, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x20 - 1280x960@60Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
356 1488, 1800, 0, 960, 961, 964, 1000, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x21 - 1280x960@85Hz */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
360 1504, 1728, 0, 960, 961, 964, 1011, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x22 - 1280x960@120Hz RB */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
364 1360, 1440, 0, 960, 963, 967, 1017, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x23 - 1280x1024@60Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x24 - 1280x1024@75Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x25 - 1280x1024@85Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x26 - 1280x1024@120Hz RB */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x27 - 1360x768@60Hz */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
384 1536, 1792, 0, 768, 771, 777, 795, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x28 - 1360x768@120Hz RB */
387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
388 1440, 1520, 0, 768, 771, 776, 813, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x51 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
392 1579, 1792, 0, 768, 771, 774, 798, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x56 - 1366x768@60Hz */
395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
396 1436, 1500, 0, 768, 769, 772, 800, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x29 - 1400x1050@60Hz RB */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x2a - 1400x1050@60Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2b - 1400x1050@75Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2c - 1400x1050@85Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2d - 1400x1050@120Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2e - 1440x900@60Hz RB */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 926, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2f - 1440x900@60Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
424 1672, 1904, 0, 900, 903, 909, 934, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x30 - 1440x900@75Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
428 1688, 1936, 0, 900, 903, 909, 942, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x31 - 1440x900@85Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
432 1696, 1952, 0, 900, 903, 909, 948, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x32 - 1440x900@120Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 953, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x53 - 1600x900@60Hz */
439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
440 1704, 1800, 0, 900, 901, 904, 1000, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x33 - 1600x1200@60Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x34 - 1600x1200@65Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x35 - 1600x1200@70Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x36 - 1600x1200@75Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x37 - 1600x1200@85Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x38 - 1600x1200@120Hz RB */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x39 - 1680x1050@60Hz RB */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x3a - 1680x1050@60Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3b - 1680x1050@75Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3c - 1680x1050@85Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3d - 1680x1050@120Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3e - 1792x1344@60Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3f - 1792x1344@75Hz */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x40 - 1792x1344@120Hz RB */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x41 - 1856x1392@60Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x42 - 1856x1392@75Hz */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x43 - 1856x1392@120Hz RB */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x52 - 1920x1080@60Hz */
511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x44 - 1920x1200@60Hz RB */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x45 - 1920x1200@60Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x46 - 1920x1200@75Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x47 - 1920x1200@85Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x48 - 1920x1200@120Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x49 - 1920x1440@60Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4a - 1920x1440@75Hz */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x4b - 1920x1440@120Hz RB */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x54 - 2048x1152@60Hz */
547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4c - 2560x1600@60Hz RB */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x4d - 2560x1600@60Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4e - 2560x1600@75Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4f - 2560x1600@85Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x50 - 2560x1600@120Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x57 - 4096x2160@60Hz RB */
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x58 - 4096x2160@59.94Hz RB */
575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 };
579
580 /*
581 * These more or less come from the DMT spec. The 720x400 modes are
582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
585 * mode.
586 *
587 * The DMT modes have been fact-checked; the rest are mild guesses.
588 */
589 static const struct drm_display_mode edid_est_modes[] = {
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
591 968, 1056, 0, 600, 601, 605, 628, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
594 896, 1024, 0, 600, 601, 603, 625, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
597 720, 840, 0, 480, 481, 484, 500, 0,
598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
600 704, 832, 0, 480, 489, 492, 520, 0,
601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
603 768, 864, 0, 480, 483, 486, 525, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
609 846, 900, 0, 400, 421, 423, 449, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
612 846, 900, 0, 400, 412, 414, 449, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
618 1136, 1312, 0, 768, 769, 772, 800, 0,
619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
621 1184, 1328, 0, 768, 771, 777, 806, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
624 1184, 1344, 0, 768, 771, 777, 806, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
627 1208, 1264, 0, 768, 768, 776, 817, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
630 928, 1152, 0, 624, 625, 628, 667, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
633 896, 1056, 0, 600, 601, 604, 625, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
636 976, 1040, 0, 600, 637, 643, 666, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
639 1344, 1600, 0, 864, 865, 868, 900, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
641 };
642
643 struct minimode {
644 short w;
645 short h;
646 short r;
647 short rb;
648 };
649
650 static const struct minimode est3_modes[] = {
651 /* byte 6 */
652 { 640, 350, 85, 0 },
653 { 640, 400, 85, 0 },
654 { 720, 400, 85, 0 },
655 { 640, 480, 85, 0 },
656 { 848, 480, 60, 0 },
657 { 800, 600, 85, 0 },
658 { 1024, 768, 85, 0 },
659 { 1152, 864, 75, 0 },
660 /* byte 7 */
661 { 1280, 768, 60, 1 },
662 { 1280, 768, 60, 0 },
663 { 1280, 768, 75, 0 },
664 { 1280, 768, 85, 0 },
665 { 1280, 960, 60, 0 },
666 { 1280, 960, 85, 0 },
667 { 1280, 1024, 60, 0 },
668 { 1280, 1024, 85, 0 },
669 /* byte 8 */
670 { 1360, 768, 60, 0 },
671 { 1440, 900, 60, 1 },
672 { 1440, 900, 60, 0 },
673 { 1440, 900, 75, 0 },
674 { 1440, 900, 85, 0 },
675 { 1400, 1050, 60, 1 },
676 { 1400, 1050, 60, 0 },
677 { 1400, 1050, 75, 0 },
678 /* byte 9 */
679 { 1400, 1050, 85, 0 },
680 { 1680, 1050, 60, 1 },
681 { 1680, 1050, 60, 0 },
682 { 1680, 1050, 75, 0 },
683 { 1680, 1050, 85, 0 },
684 { 1600, 1200, 60, 0 },
685 { 1600, 1200, 65, 0 },
686 { 1600, 1200, 70, 0 },
687 /* byte 10 */
688 { 1600, 1200, 75, 0 },
689 { 1600, 1200, 85, 0 },
690 { 1792, 1344, 60, 0 },
691 { 1792, 1344, 75, 0 },
692 { 1856, 1392, 60, 0 },
693 { 1856, 1392, 75, 0 },
694 { 1920, 1200, 60, 1 },
695 { 1920, 1200, 60, 0 },
696 /* byte 11 */
697 { 1920, 1200, 75, 0 },
698 { 1920, 1200, 85, 0 },
699 { 1920, 1440, 60, 0 },
700 { 1920, 1440, 75, 0 },
701 };
702
703 static const struct minimode extra_modes[] = {
704 { 1024, 576, 60, 0 },
705 { 1366, 768, 60, 0 },
706 { 1600, 900, 60, 0 },
707 { 1680, 945, 60, 0 },
708 { 1920, 1080, 60, 0 },
709 { 2048, 1152, 60, 0 },
710 { 2048, 1536, 60, 0 },
711 };
712
713 /*
714 * From CEA/CTA-861 spec.
715 *
716 * Do not access directly, instead always use cea_mode_for_vic().
717 */
718 static const struct drm_display_mode edid_cea_modes_1[] = {
719 /* 1 - 640x480@60Hz 4:3 */
720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
721 752, 800, 0, 480, 490, 492, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 2 - 720x480@60Hz 4:3 */
725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
726 798, 858, 0, 480, 489, 495, 525, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729 /* 3 - 720x480@60Hz 16:9 */
730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
731 798, 858, 0, 480, 489, 495, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 4 - 1280x720@60Hz 16:9 */
735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
736 1430, 1650, 0, 720, 725, 730, 750, 0,
737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739 /* 5 - 1920x1080i@60Hz 16:9 */
740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
743 DRM_MODE_FLAG_INTERLACE),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 6 - 720(1440)x480i@60Hz 4:3 */
746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
747 801, 858, 0, 480, 488, 494, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 7 - 720(1440)x480i@60Hz 16:9 */
752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
753 801, 858, 0, 480, 488, 494, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 8 - 720(1440)x240@60Hz 4:3 */
758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 240, 244, 247, 262, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_DBLCLK),
762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 9 - 720(1440)x240@60Hz 16:9 */
764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 240, 244, 247, 262, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_DBLCLK),
768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 10 - 2880x480i@60Hz 4:3 */
770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
771 3204, 3432, 0, 480, 488, 494, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_INTERLACE),
774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 11 - 2880x480i@60Hz 16:9 */
776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
777 3204, 3432, 0, 480, 488, 494, 525, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_INTERLACE),
780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 12 - 2880x240@60Hz 4:3 */
782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 240, 244, 247, 262, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 13 - 2880x240@60Hz 16:9 */
787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 240, 244, 247, 262, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 14 - 1440x480@60Hz 4:3 */
792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
793 1596, 1716, 0, 480, 489, 495, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 15 - 1440x480@60Hz 16:9 */
797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
798 1596, 1716, 0, 480, 489, 495, 525, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 16 - 1920x1080@60Hz 16:9 */
802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806 /* 17 - 720x576@50Hz 4:3 */
807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
808 796, 864, 0, 576, 581, 586, 625, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 18 - 720x576@50Hz 16:9 */
812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
813 796, 864, 0, 576, 581, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 19 - 1280x720@50Hz 16:9 */
817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
818 1760, 1980, 0, 720, 725, 730, 750, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 20 - 1920x1080i@50Hz 16:9 */
822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
825 DRM_MODE_FLAG_INTERLACE),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 21 - 720(1440)x576i@50Hz 4:3 */
828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
829 795, 864, 0, 576, 580, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 22 - 720(1440)x576i@50Hz 16:9 */
834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
835 795, 864, 0, 576, 580, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 23 - 720(1440)x288@50Hz 4:3 */
840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 288, 290, 293, 312, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
843 DRM_MODE_FLAG_DBLCLK),
844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
845 /* 24 - 720(1440)x288@50Hz 16:9 */
846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 288, 290, 293, 312, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
849 DRM_MODE_FLAG_DBLCLK),
850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 25 - 2880x576i@50Hz 4:3 */
852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
853 3180, 3456, 0, 576, 580, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_INTERLACE),
856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 26 - 2880x576i@50Hz 16:9 */
858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
859 3180, 3456, 0, 576, 580, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 27 - 2880x288@50Hz 4:3 */
864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 288, 290, 293, 312, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 28 - 2880x288@50Hz 16:9 */
869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 288, 290, 293, 312, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 29 - 1440x576@50Hz 4:3 */
874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
875 1592, 1728, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 30 - 1440x576@50Hz 16:9 */
879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
880 1592, 1728, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 31 - 1920x1080@50Hz 16:9 */
884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 32 - 1920x1080@24Hz 16:9 */
889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 33 - 1920x1080@25Hz 16:9 */
894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 34 - 1920x1080@30Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 35 - 2880x480@60Hz 4:3 */
904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
905 3192, 3432, 0, 480, 489, 495, 525, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
908 /* 36 - 2880x480@60Hz 16:9 */
909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
910 3192, 3432, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 37 - 2880x576@50Hz 4:3 */
914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
915 3184, 3456, 0, 576, 581, 586, 625, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 38 - 2880x576@50Hz 16:9 */
919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
920 3184, 3456, 0, 576, 581, 586, 625, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 39 - 1920x1080i@50Hz 16:9 */
924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 40 - 1920x1080i@100Hz 16:9 */
930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
933 DRM_MODE_FLAG_INTERLACE),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 41 - 1280x720@100Hz 16:9 */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
937 1760, 1980, 0, 720, 725, 730, 750, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 42 - 720x576@100Hz 4:3 */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
945 /* 43 - 720x576@100Hz 16:9 */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 44 - 720(1440)x576i@100Hz 4:3 */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 45 - 720(1440)x576i@100Hz 16:9 */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 46 - 1920x1080i@120Hz 16:9 */
963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
966 DRM_MODE_FLAG_INTERLACE),
967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
968 /* 47 - 1280x720@120Hz 16:9 */
969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
970 1430, 1650, 0, 720, 725, 730, 750, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 48 - 720x480@120Hz 4:3 */
974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
975 798, 858, 0, 480, 489, 495, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 49 - 720x480@120Hz 16:9 */
979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
980 798, 858, 0, 480, 489, 495, 525, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 50 - 720(1440)x480i@120Hz 4:3 */
984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
989 /* 51 - 720(1440)x480i@120Hz 16:9 */
990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
991 801, 858, 0, 480, 488, 494, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 52 - 720x576@200Hz 4:3 */
996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
997 796, 864, 0, 576, 581, 586, 625, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 53 - 720x576@200Hz 16:9 */
1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002 796, 864, 0, 576, 581, 586, 625, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 54 - 720(1440)x576i@200Hz 4:3 */
1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007 795, 864, 0, 576, 580, 586, 625, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 55 - 720(1440)x576i@200Hz 16:9 */
1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013 795, 864, 0, 576, 580, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 56 - 720x480@240Hz 4:3 */
1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019 798, 858, 0, 480, 489, 495, 525, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 57 - 720x480@240Hz 16:9 */
1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024 798, 858, 0, 480, 489, 495, 525, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 58 - 720(1440)x480i@240Hz 4:3 */
1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029 801, 858, 0, 480, 488, 494, 525, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 59 - 720(1440)x480i@240Hz 16:9 */
1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035 801, 858, 0, 480, 488, 494, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 60 - 1280x720@24Hz 16:9 */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 61 - 1280x720@25Hz 16:9 */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 62 - 1280x720@30Hz 16:9 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054 /* 63 - 1920x1080@120Hz 16:9 */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 64 - 1920x1080@100Hz 16:9 */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 65 - 1280x720@24Hz 64:27 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 66 - 1280x720@25Hz 64:27 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071 3740, 3960, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 67 - 1280x720@30Hz 64:27 */
1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 68 - 1280x720@50Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081 1760, 1980, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 69 - 1280x720@60Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086 1430, 1650, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 70 - 1280x720@100Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 71 - 1280x720@120Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 72 - 1920x1080@24Hz 64:27 */
1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 73 - 1920x1080@25Hz 64:27 */
1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 74 - 1920x1080@30Hz 64:27 */
1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 75 - 1920x1080@50Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 76 - 1920x1080@60Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 77 - 1920x1080@100Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 78 - 1920x1080@120Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 79 - 1680x720@24Hz 64:27 */
1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136 3080, 3300, 0, 720, 725, 730, 750, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 80 - 1680x720@25Hz 64:27 */
1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141 2948, 3168, 0, 720, 725, 730, 750, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 81 - 1680x720@30Hz 64:27 */
1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146 2420, 2640, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 82 - 1680x720@50Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151 1980, 2200, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 83 - 1680x720@60Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156 1980, 2200, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 84 - 1680x720@100Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161 1780, 2000, 0, 720, 725, 730, 825, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 85 - 1680x720@120Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166 1780, 2000, 0, 720, 725, 730, 825, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 86 - 2560x1080@24Hz 64:27 */
1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 87 - 2560x1080@25Hz 64:27 */
1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 88 - 2560x1080@30Hz 64:27 */
1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 89 - 2560x1080@50Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 90 - 2560x1080@60Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 91 - 2560x1080@100Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 92 - 2560x1080@120Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 93 - 3840x2160@24Hz 16:9 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1209 /* 94 - 3840x2160@25Hz 16:9 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1214 /* 95 - 3840x2160@30Hz 16:9 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1219 /* 96 - 3840x2160@50Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224 /* 97 - 3840x2160@60Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 98 - 4096x2160@24Hz 256:135 */
1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1234 /* 99 - 4096x2160@25Hz 256:135 */
1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1239 /* 100 - 4096x2160@30Hz 256:135 */
1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1244 /* 101 - 4096x2160@50Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249 /* 102 - 4096x2160@60Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 103 - 3840x2160@24Hz 64:27 */
1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1259 /* 104 - 3840x2160@25Hz 64:27 */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1264 /* 105 - 3840x2160@30Hz 64:27 */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269 /* 106 - 3840x2160@50Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274 /* 107 - 3840x2160@60Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 108 - 1280x720@48Hz 16:9 */
1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281 2280, 2500, 0, 720, 725, 730, 750, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1284 /* 109 - 1280x720@48Hz 64:27 */
1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286 2280, 2500, 0, 720, 725, 730, 750, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 110 - 1680x720@48Hz 64:27 */
1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291 2530, 2750, 0, 720, 725, 730, 750, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 111 - 1920x1080@48Hz 16:9 */
1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299 /* 112 - 1920x1080@48Hz 64:27 */
1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304 /* 113 - 2560x1080@48Hz 64:27 */
1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 114 - 3840x2160@48Hz 16:9 */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314 /* 115 - 4096x2160@48Hz 256:135 */
1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1319 /* 116 - 3840x2160@48Hz 64:27 */
1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 117 - 3840x2160@100Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329 /* 118 - 3840x2160@120Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 119 - 3840x2160@100Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339 /* 120 - 3840x2160@120Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 121 - 5120x2160@24Hz 64:27 */
1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1349 /* 122 - 5120x2160@25Hz 64:27 */
1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354 /* 123 - 5120x2160@30Hz 64:27 */
1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 124 - 5120x2160@48Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 125 - 5120x2160@50Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 126 - 5120x2160@60Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 127 - 5120x2160@100Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 };
1380
1381 /*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386 static const struct drm_display_mode edid_cea_modes_193[] = {
1387 /* 193 - 5120x2160@120Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1392 /* 194 - 7680x4320@24Hz 16:9 */
1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1397 /* 195 - 7680x4320@25Hz 16:9 */
1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1402 /* 196 - 7680x4320@30Hz 16:9 */
1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1407 /* 197 - 7680x4320@48Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412 /* 198 - 7680x4320@50Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 199 - 7680x4320@60Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 200 - 7680x4320@100Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 201 - 7680x4320@120Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 202 - 7680x4320@24Hz 64:27 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1437 /* 203 - 7680x4320@25Hz 64:27 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1442 /* 204 - 7680x4320@30Hz 64:27 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1447 /* 205 - 7680x4320@48Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452 /* 206 - 7680x4320@50Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 207 - 7680x4320@60Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 208 - 7680x4320@100Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 209 - 7680x4320@120Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 210 - 10240x4320@24Hz 64:27 */
1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 211 - 10240x4320@25Hz 64:27 */
1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 212 - 10240x4320@30Hz 64:27 */
1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 213 - 10240x4320@48Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 214 - 10240x4320@50Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 215 - 10240x4320@60Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 216 - 10240x4320@100Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 217 - 10240x4320@120Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 218 - 4096x2160@100Hz 256:135 */
1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1517 /* 219 - 4096x2160@120Hz 256:135 */
1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1522 };
1523
1524 /*
1525 * HDMI 1.4 4k modes. Index using the VIC.
1526 */
1527 static const struct drm_display_mode edid_4k_modes[] = {
1528 /* 0 - dummy, VICs start at 1 */
1529 { },
1530 /* 1 - 3840x2160@30Hz */
1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532 3840, 4016, 4104, 4400, 0,
1533 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1536 /* 2 - 3840x2160@25Hz */
1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538 3840, 4896, 4984, 5280, 0,
1539 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1542 /* 3 - 3840x2160@24Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 5116, 5204, 5500, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548 /* 4 - 4096x2160@24Hz (SMPTE) */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 4096, 5116, 5204, 5500, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1554 };
1555
1556 /*** DDC fetch and block validation ***/
1557
1558 static const u8 edid_header[] = {
1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560 };
1561
1562 /**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 */
drm_edid_header_is_valid(const u8 * raw_edid)1570 int drm_edid_header_is_valid(const u8 *raw_edid)
1571 {
1572 int i, score = 0;
1573
1574 for (i = 0; i < sizeof(edid_header); i++)
1575 if (raw_edid[i] == edid_header[i])
1576 score++;
1577
1578 return score;
1579 }
1580 EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
1582 static int edid_fixup __read_mostly = 6;
1583 module_param_named(edid_fixup, edid_fixup, int, 0400);
1584 MODULE_PARM_DESC(edid_fixup,
1585 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586
1587 static int validate_displayid(u8 *displayid, int length, int idx);
1588
drm_edid_block_checksum(const u8 * raw_edid)1589 static int drm_edid_block_checksum(const u8 *raw_edid)
1590 {
1591 int i;
1592 u8 csum = 0, crc = 0;
1593
1594 for (i = 0; i < EDID_LENGTH - 1; i++)
1595 csum += raw_edid[i];
1596
1597 crc = 0x100 - csum;
1598
1599 return crc;
1600 }
1601
drm_edid_block_checksum_diff(const u8 * raw_edid,u8 real_checksum)1602 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603 {
1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1605 return true;
1606 else
1607 return false;
1608 }
1609
drm_edid_is_zero(const u8 * in_edid,int length)1610 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611 {
1612 if (memchr_inv(in_edid, 0, length))
1613 return false;
1614
1615 return true;
1616 }
1617
1618 /**
1619 * drm_edid_are_equal - compare two edid blobs.
1620 * @edid1: pointer to first blob
1621 * @edid2: pointer to second blob
1622 * This helper can be used during probing to determine if
1623 * edid had changed.
1624 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1625 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1626 {
1627 int edid1_len, edid2_len;
1628 bool edid1_present = edid1 != NULL;
1629 bool edid2_present = edid2 != NULL;
1630
1631 if (edid1_present != edid2_present)
1632 return false;
1633
1634 if (edid1) {
1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1637
1638 if (edid1_len != edid2_len)
1639 return false;
1640
1641 if (memcmp(edid1, edid2, edid1_len))
1642 return false;
1643 }
1644
1645 return true;
1646 }
1647 EXPORT_SYMBOL(drm_edid_are_equal);
1648
1649 /**
1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1651 * @raw_edid: pointer to raw EDID block
1652 * @block: type of block to validate (0 for base, extension otherwise)
1653 * @print_bad_edid: if true, dump bad EDID blocks to the console
1654 * @edid_corrupt: if true, the header or checksum is invalid
1655 *
1656 * Validate a base or extension EDID block and optionally dump bad blocks to
1657 * the console.
1658 *
1659 * Return: True if the block is valid, false otherwise.
1660 */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)1661 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1662 bool *edid_corrupt)
1663 {
1664 u8 csum;
1665 struct edid *edid = (struct edid *)raw_edid;
1666
1667 if (WARN_ON(!raw_edid))
1668 return false;
1669
1670 if (edid_fixup > 8 || edid_fixup < 0)
1671 edid_fixup = 6;
1672
1673 if (block == 0) {
1674 int score = drm_edid_header_is_valid(raw_edid);
1675
1676 if (score == 8) {
1677 if (edid_corrupt)
1678 *edid_corrupt = false;
1679 } else if (score >= edid_fixup) {
1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1681 * The corrupt flag needs to be set here otherwise, the
1682 * fix-up code here will correct the problem, the
1683 * checksum is correct and the test fails
1684 */
1685 if (edid_corrupt)
1686 *edid_corrupt = true;
1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1688 memcpy(raw_edid, edid_header, sizeof(edid_header));
1689 } else {
1690 if (edid_corrupt)
1691 *edid_corrupt = true;
1692 goto bad;
1693 }
1694 }
1695
1696 csum = drm_edid_block_checksum(raw_edid);
1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1698 if (edid_corrupt)
1699 *edid_corrupt = true;
1700
1701 /* allow CEA to slide through, switches mangle this */
1702 if (raw_edid[0] == CEA_EXT) {
1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1705 } else {
1706 if (print_bad_edid)
1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1708
1709 goto bad;
1710 }
1711 }
1712
1713 /* per-block-type checks */
1714 switch (raw_edid[0]) {
1715 case 0: /* base */
1716 if (edid->version != 1) {
1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1718 goto bad;
1719 }
1720
1721 if (edid->revision > 4)
1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 return true;
1730
1731 bad:
1732 if (print_bad_edid) {
1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1734 pr_notice("EDID block is all zeroes\n");
1735 } else {
1736 pr_notice("Raw EDID:\n");
1737 print_hex_dump(KERN_NOTICE,
1738 " \t", DUMP_PREFIX_NONE, 16, 1,
1739 raw_edid, EDID_LENGTH, false);
1740 }
1741 }
1742 return false;
1743 }
1744 EXPORT_SYMBOL(drm_edid_block_valid);
1745
1746 /**
1747 * drm_edid_is_valid - sanity check EDID data
1748 * @edid: EDID data
1749 *
1750 * Sanity-check an entire EDID record (including extensions)
1751 *
1752 * Return: True if the EDID data is valid, false otherwise.
1753 */
drm_edid_is_valid(struct edid * edid)1754 bool drm_edid_is_valid(struct edid *edid)
1755 {
1756 int i;
1757 u8 *raw = (u8 *)edid;
1758
1759 if (!edid)
1760 return false;
1761
1762 for (i = 0; i <= edid->extensions; i++)
1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1764 return false;
1765
1766 return true;
1767 }
1768 EXPORT_SYMBOL(drm_edid_is_valid);
1769
1770 #define DDC_SEGMENT_ADDR 0x30
1771 /**
1772 * drm_do_probe_ddc_edid() - get EDID information via I2C
1773 * @data: I2C device adapter
1774 * @buf: EDID data buffer to be filled
1775 * @block: 128 byte EDID block to start fetching from
1776 * @len: EDID data buffer length to fetch
1777 *
1778 * Try to fetch EDID information by calling I2C driver functions.
1779 *
1780 * Return: 0 on success or -1 on failure.
1781 */
1782 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)1783 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1784 {
1785 struct i2c_adapter *adapter = data;
1786 unsigned char start = block * EDID_LENGTH;
1787 unsigned char segment = block >> 1;
1788 unsigned char xfers = segment ? 3 : 2;
1789 int ret, retries = 5;
1790
1791 /*
1792 * The core I2C driver will automatically retry the transfer if the
1793 * adapter reports EAGAIN. However, we find that bit-banging transfers
1794 * are susceptible to errors under a heavily loaded machine and
1795 * generate spurious NAKs and timeouts. Retrying the transfer
1796 * of the individual block a few times seems to overcome this.
1797 */
1798 do {
1799 struct i2c_msg msgs[] = {
1800 {
1801 .addr = DDC_SEGMENT_ADDR,
1802 .flags = 0,
1803 .len = 1,
1804 .buf = &segment,
1805 }, {
1806 .addr = DDC_ADDR,
1807 .flags = 0,
1808 .len = 1,
1809 .buf = &start,
1810 }, {
1811 .addr = DDC_ADDR,
1812 .flags = I2C_M_RD,
1813 .len = len,
1814 .buf = buf,
1815 }
1816 };
1817
1818 /*
1819 * Avoid sending the segment addr to not upset non-compliant
1820 * DDC monitors.
1821 */
1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1823
1824 if (ret == -ENXIO) {
1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1826 adapter->name);
1827 break;
1828 }
1829 } while (ret != xfers && --retries);
1830
1831 return ret == xfers ? 0 : -1;
1832 }
1833
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1834 static void connector_bad_edid(struct drm_connector *connector,
1835 u8 *edid, int num_blocks)
1836 {
1837 int i;
1838 u8 last_block;
1839
1840 /*
1841 * 0x7e in the EDID is the number of extension blocks. The EDID
1842 * is 1 (base block) + num_ext_blocks big. That means we can think
1843 * of 0x7e in the EDID of the _index_ of the last block in the
1844 * combined chunk of memory.
1845 */
1846 last_block = edid[0x7e];
1847
1848 /* Calculate real checksum for the last edid extension block data */
1849 if (last_block < num_blocks)
1850 connector->real_edid_checksum =
1851 drm_edid_block_checksum(edid + last_block * EDID_LENGTH);
1852
1853 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1854 return;
1855
1856 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
1857 for (i = 0; i < num_blocks; i++) {
1858 u8 *block = edid + i * EDID_LENGTH;
1859 char prefix[20];
1860
1861 if (drm_edid_is_zero(block, EDID_LENGTH))
1862 sprintf(prefix, "\t[%02x] ZERO ", i);
1863 else if (!drm_edid_block_valid(block, i, false, NULL))
1864 sprintf(prefix, "\t[%02x] BAD ", i);
1865 else
1866 sprintf(prefix, "\t[%02x] GOOD ", i);
1867
1868 print_hex_dump(KERN_WARNING,
1869 prefix, DUMP_PREFIX_NONE, 16, 1,
1870 block, EDID_LENGTH, false);
1871 }
1872 }
1873
1874 /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector)1875 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1876 {
1877 struct edid *override = NULL;
1878
1879 if (connector->override_edid)
1880 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1881
1882 if (!override)
1883 override = drm_load_edid_firmware(connector);
1884
1885 return IS_ERR(override) ? NULL : override;
1886 }
1887
1888 /**
1889 * drm_add_override_edid_modes - add modes from override/firmware EDID
1890 * @connector: connector we're probing
1891 *
1892 * Add modes from the override/firmware EDID, if available. Only to be used from
1893 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1894 * failed during drm_get_edid() and caused the override/firmware EDID to be
1895 * skipped.
1896 *
1897 * Return: The number of modes added or 0 if we couldn't find any.
1898 */
drm_add_override_edid_modes(struct drm_connector * connector)1899 int drm_add_override_edid_modes(struct drm_connector *connector)
1900 {
1901 struct edid *override;
1902 int num_modes = 0;
1903
1904 override = drm_get_override_edid(connector);
1905 if (override) {
1906 drm_connector_update_edid_property(connector, override);
1907 num_modes = drm_add_edid_modes(connector, override);
1908 kfree(override);
1909
1910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1911 connector->base.id, connector->name, num_modes);
1912 }
1913
1914 return num_modes;
1915 }
1916 EXPORT_SYMBOL(drm_add_override_edid_modes);
1917
1918 /**
1919 * drm_do_get_edid - get EDID data using a custom EDID block read function
1920 * @connector: connector we're probing
1921 * @get_edid_block: EDID block read function
1922 * @data: private data passed to the block read function
1923 *
1924 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1925 * exposes a different interface to read EDID blocks this function can be used
1926 * to get EDID data using a custom block read function.
1927 *
1928 * As in the general case the DDC bus is accessible by the kernel at the I2C
1929 * level, drivers must make all reasonable efforts to expose it as an I2C
1930 * adapter and use drm_get_edid() instead of abusing this function.
1931 *
1932 * The EDID may be overridden using debugfs override_edid or firmare EDID
1933 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1934 * order. Having either of them bypasses actual EDID reads.
1935 *
1936 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1937 */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)1938 struct edid *drm_do_get_edid(struct drm_connector *connector,
1939 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1940 size_t len),
1941 void *data)
1942 {
1943 int i, j = 0, valid_extensions = 0;
1944 u8 *edid, *new;
1945 struct edid *override;
1946
1947 override = drm_get_override_edid(connector);
1948 if (override)
1949 return override;
1950
1951 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1952 return NULL;
1953
1954 /* base block fetch */
1955 for (i = 0; i < 4; i++) {
1956 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1957 goto out;
1958 if (drm_edid_block_valid(edid, 0, false,
1959 &connector->edid_corrupt))
1960 break;
1961 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1962 connector->null_edid_counter++;
1963 goto carp;
1964 }
1965 }
1966 if (i == 4)
1967 goto carp;
1968
1969 /* if there's no extensions, we're done */
1970 valid_extensions = edid[0x7e];
1971 if (valid_extensions == 0)
1972 return (struct edid *)edid;
1973
1974 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1975 if (!new)
1976 goto out;
1977 edid = new;
1978
1979 for (j = 1; j <= edid[0x7e]; j++) {
1980 u8 *block = edid + j * EDID_LENGTH;
1981
1982 for (i = 0; i < 4; i++) {
1983 if (get_edid_block(data, block, j, EDID_LENGTH))
1984 goto out;
1985 if (drm_edid_block_valid(block, j, false, NULL))
1986 break;
1987 }
1988
1989 if (i == 4)
1990 valid_extensions--;
1991 }
1992
1993 if (valid_extensions != edid[0x7e]) {
1994 u8 *base;
1995
1996 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1997
1998 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1999 GFP_KERNEL);
2000 if (!new)
2001 goto out;
2002
2003 base = new;
2004 for (i = 0; i <= edid[0x7e]; i++) {
2005 u8 *block = edid + i * EDID_LENGTH;
2006
2007 if (!drm_edid_block_valid(block, i, false, NULL))
2008 continue;
2009
2010 memcpy(base, block, EDID_LENGTH);
2011 base += EDID_LENGTH;
2012 }
2013
2014 new[EDID_LENGTH - 1] += new[0x7e] - valid_extensions;
2015 new[0x7e] = valid_extensions;
2016
2017 kfree(edid);
2018 edid = new;
2019 }
2020
2021 return (struct edid *)edid;
2022
2023 carp:
2024 connector_bad_edid(connector, edid, 1);
2025 out:
2026 kfree(edid);
2027 return NULL;
2028 }
2029 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2030
2031 /**
2032 * drm_probe_ddc() - probe DDC presence
2033 * @adapter: I2C adapter to probe
2034 *
2035 * Return: True on success, false on failure.
2036 */
2037 bool
drm_probe_ddc(struct i2c_adapter * adapter)2038 drm_probe_ddc(struct i2c_adapter *adapter)
2039 {
2040 unsigned char out;
2041
2042 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2043 }
2044 EXPORT_SYMBOL(drm_probe_ddc);
2045
2046 /**
2047 * drm_get_edid - get EDID data, if available
2048 * @connector: connector we're probing
2049 * @adapter: I2C adapter to use for DDC
2050 *
2051 * Poke the given I2C channel to grab EDID data if possible. If found,
2052 * attach it to the connector.
2053 *
2054 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2055 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2056 struct edid *drm_get_edid(struct drm_connector *connector,
2057 struct i2c_adapter *adapter)
2058 {
2059 struct edid *edid;
2060
2061 if (connector->force == DRM_FORCE_OFF)
2062 return NULL;
2063
2064 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2065 return NULL;
2066
2067 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2068 drm_connector_update_edid_property(connector, edid);
2069 return edid;
2070 }
2071 EXPORT_SYMBOL(drm_get_edid);
2072
2073 /**
2074 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2075 * @connector: connector we're probing
2076 * @adapter: I2C adapter to use for DDC
2077 *
2078 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2079 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2080 * switch DDC to the GPU which is retrieving EDID.
2081 *
2082 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2083 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2084 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2085 struct i2c_adapter *adapter)
2086 {
2087 struct pci_dev *pdev = connector->dev->pdev;
2088 struct edid *edid;
2089
2090 vga_switcheroo_lock_ddc(pdev);
2091 edid = drm_get_edid(connector, adapter);
2092 vga_switcheroo_unlock_ddc(pdev);
2093
2094 return edid;
2095 }
2096 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2097
2098 /**
2099 * drm_edid_duplicate - duplicate an EDID and the extensions
2100 * @edid: EDID to duplicate
2101 *
2102 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2103 */
drm_edid_duplicate(const struct edid * edid)2104 struct edid *drm_edid_duplicate(const struct edid *edid)
2105 {
2106 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2107 }
2108 EXPORT_SYMBOL(drm_edid_duplicate);
2109
2110 /*** EDID parsing ***/
2111
2112 /**
2113 * edid_vendor - match a string against EDID's obfuscated vendor field
2114 * @edid: EDID to match
2115 * @vendor: vendor string
2116 *
2117 * Returns true if @vendor is in @edid, false otherwise
2118 */
edid_vendor(const struct edid * edid,const char * vendor)2119 static bool edid_vendor(const struct edid *edid, const char *vendor)
2120 {
2121 char edid_vendor[3];
2122
2123 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2124 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2125 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2126 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2127
2128 return !strncmp(edid_vendor, vendor, 3);
2129 }
2130
2131 /**
2132 * edid_get_quirks - return quirk flags for a given EDID
2133 * @edid: EDID to process
2134 *
2135 * This tells subsequent routines what fixes they need to apply.
2136 */
edid_get_quirks(const struct edid * edid)2137 static u32 edid_get_quirks(const struct edid *edid)
2138 {
2139 const struct edid_quirk *quirk;
2140 int i;
2141
2142 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2143 quirk = &edid_quirk_list[i];
2144
2145 if (edid_vendor(edid, quirk->vendor) &&
2146 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2147 return quirk->quirks;
2148 }
2149
2150 return 0;
2151 }
2152
2153 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2154 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2155
2156 /**
2157 * edid_fixup_preferred - set preferred modes based on quirk list
2158 * @connector: has mode list to fix up
2159 * @quirks: quirks list
2160 *
2161 * Walk the mode list for @connector, clearing the preferred status
2162 * on existing modes and setting it anew for the right mode ala @quirks.
2163 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)2164 static void edid_fixup_preferred(struct drm_connector *connector,
2165 u32 quirks)
2166 {
2167 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2168 int target_refresh = 0;
2169 int cur_vrefresh, preferred_vrefresh;
2170
2171 if (list_empty(&connector->probed_modes))
2172 return;
2173
2174 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2175 target_refresh = 60;
2176 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2177 target_refresh = 75;
2178
2179 preferred_mode = list_first_entry(&connector->probed_modes,
2180 struct drm_display_mode, head);
2181
2182 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2183 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2184
2185 if (cur_mode == preferred_mode)
2186 continue;
2187
2188 /* Largest mode is preferred */
2189 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2190 preferred_mode = cur_mode;
2191
2192 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2193 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2194 /* At a given size, try to get closest to target refresh */
2195 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2196 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2197 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2198 preferred_mode = cur_mode;
2199 }
2200 }
2201
2202 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2203 }
2204
2205 static bool
mode_is_rb(const struct drm_display_mode * mode)2206 mode_is_rb(const struct drm_display_mode *mode)
2207 {
2208 return (mode->htotal - mode->hdisplay == 160) &&
2209 (mode->hsync_end - mode->hdisplay == 80) &&
2210 (mode->hsync_end - mode->hsync_start == 32) &&
2211 (mode->vsync_start - mode->vdisplay == 3);
2212 }
2213
2214 /*
2215 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2216 * @dev: Device to duplicate against
2217 * @hsize: Mode width
2218 * @vsize: Mode height
2219 * @fresh: Mode refresh rate
2220 * @rb: Mode reduced-blanking-ness
2221 *
2222 * Walk the DMT mode list looking for a match for the given parameters.
2223 *
2224 * Return: A newly allocated copy of the mode, or NULL if not found.
2225 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)2226 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2227 int hsize, int vsize, int fresh,
2228 bool rb)
2229 {
2230 int i;
2231
2232 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2233 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2234
2235 if (hsize != ptr->hdisplay)
2236 continue;
2237 if (vsize != ptr->vdisplay)
2238 continue;
2239 if (fresh != drm_mode_vrefresh(ptr))
2240 continue;
2241 if (rb != mode_is_rb(ptr))
2242 continue;
2243
2244 return drm_mode_duplicate(dev, ptr);
2245 }
2246
2247 return NULL;
2248 }
2249 EXPORT_SYMBOL(drm_mode_find_dmt);
2250
is_display_descriptor(const u8 d[18],u8 tag)2251 static bool is_display_descriptor(const u8 d[18], u8 tag)
2252 {
2253 return d[0] == 0x00 && d[1] == 0x00 &&
2254 d[2] == 0x00 && d[3] == tag;
2255 }
2256
is_detailed_timing_descriptor(const u8 d[18])2257 static bool is_detailed_timing_descriptor(const u8 d[18])
2258 {
2259 return d[0] != 0x00 || d[1] != 0x00;
2260 }
2261
2262 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2263
2264 static void
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2265 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2266 {
2267 int i, n;
2268 u8 d = ext[0x02];
2269 u8 *det_base = ext + d;
2270
2271 if (d < 4 || d > 127)
2272 return;
2273
2274 n = (127 - d) / 18;
2275 for (i = 0; i < n; i++)
2276 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2277 }
2278
2279 static void
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)2280 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2281 {
2282 unsigned int i, n = min((int)ext[0x02], 6);
2283 u8 *det_base = ext + 5;
2284
2285 if (ext[0x01] != 1)
2286 return; /* unknown version */
2287
2288 for (i = 0; i < n; i++)
2289 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2290 }
2291
2292 static void
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)2293 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2294 {
2295 int i;
2296 struct edid *edid = (struct edid *)raw_edid;
2297
2298 if (edid == NULL)
2299 return;
2300
2301 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2302 cb(&(edid->detailed_timings[i]), closure);
2303
2304 for (i = 1; i <= raw_edid[0x7e]; i++) {
2305 u8 *ext = raw_edid + (i * EDID_LENGTH);
2306
2307 switch (*ext) {
2308 case CEA_EXT:
2309 cea_for_each_detailed_block(ext, cb, closure);
2310 break;
2311 case VTB_EXT:
2312 vtb_for_each_detailed_block(ext, cb, closure);
2313 break;
2314 default:
2315 break;
2316 }
2317 }
2318 }
2319
2320 static void
is_rb(struct detailed_timing * t,void * data)2321 is_rb(struct detailed_timing *t, void *data)
2322 {
2323 u8 *r = (u8 *)t;
2324
2325 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2326 return;
2327
2328 if (r[15] & 0x10)
2329 *(bool *)data = true;
2330 }
2331
2332 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2333 static bool
drm_monitor_supports_rb(struct edid * edid)2334 drm_monitor_supports_rb(struct edid *edid)
2335 {
2336 if (edid->revision >= 4) {
2337 bool ret = false;
2338
2339 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2340 return ret;
2341 }
2342
2343 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2344 }
2345
2346 static void
find_gtf2(struct detailed_timing * t,void * data)2347 find_gtf2(struct detailed_timing *t, void *data)
2348 {
2349 u8 *r = (u8 *)t;
2350
2351 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2352 return;
2353
2354 if (r[10] == 0x02)
2355 *(u8 **)data = r;
2356 }
2357
2358 /* Secondary GTF curve kicks in above some break frequency */
2359 static int
drm_gtf2_hbreak(struct edid * edid)2360 drm_gtf2_hbreak(struct edid *edid)
2361 {
2362 u8 *r = NULL;
2363
2364 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2365 return r ? (r[12] * 2) : 0;
2366 }
2367
2368 static int
drm_gtf2_2c(struct edid * edid)2369 drm_gtf2_2c(struct edid *edid)
2370 {
2371 u8 *r = NULL;
2372
2373 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2374 return r ? r[13] : 0;
2375 }
2376
2377 static int
drm_gtf2_m(struct edid * edid)2378 drm_gtf2_m(struct edid *edid)
2379 {
2380 u8 *r = NULL;
2381
2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2383 return r ? (r[15] << 8) + r[14] : 0;
2384 }
2385
2386 static int
drm_gtf2_k(struct edid * edid)2387 drm_gtf2_k(struct edid *edid)
2388 {
2389 u8 *r = NULL;
2390
2391 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2392 return r ? r[16] : 0;
2393 }
2394
2395 static int
drm_gtf2_2j(struct edid * edid)2396 drm_gtf2_2j(struct edid *edid)
2397 {
2398 u8 *r = NULL;
2399
2400 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2401 return r ? r[17] : 0;
2402 }
2403
2404 /**
2405 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2406 * @edid: EDID block to scan
2407 */
standard_timing_level(struct edid * edid)2408 static int standard_timing_level(struct edid *edid)
2409 {
2410 if (edid->revision >= 2) {
2411 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2412 return LEVEL_CVT;
2413 if (drm_gtf2_hbreak(edid))
2414 return LEVEL_GTF2;
2415 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2416 return LEVEL_GTF;
2417 }
2418 return LEVEL_DMT;
2419 }
2420
2421 /*
2422 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2423 * monitors fill with ascii space (0x20) instead.
2424 */
2425 static int
bad_std_timing(u8 a,u8 b)2426 bad_std_timing(u8 a, u8 b)
2427 {
2428 return (a == 0x00 && b == 0x00) ||
2429 (a == 0x01 && b == 0x01) ||
2430 (a == 0x20 && b == 0x20);
2431 }
2432
drm_mode_hsync(const struct drm_display_mode * mode)2433 static int drm_mode_hsync(const struct drm_display_mode *mode)
2434 {
2435 if (mode->htotal <= 0)
2436 return 0;
2437
2438 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2439 }
2440
2441 /**
2442 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2443 * @connector: connector of for the EDID block
2444 * @edid: EDID block to scan
2445 * @t: standard timing params
2446 *
2447 * Take the standard timing params (in this case width, aspect, and refresh)
2448 * and convert them into a real mode using CVT/GTF/DMT.
2449 */
2450 static struct drm_display_mode *
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)2451 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2452 struct std_timing *t)
2453 {
2454 struct drm_device *dev = connector->dev;
2455 struct drm_display_mode *m, *mode = NULL;
2456 int hsize, vsize;
2457 int vrefresh_rate;
2458 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2459 >> EDID_TIMING_ASPECT_SHIFT;
2460 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2461 >> EDID_TIMING_VFREQ_SHIFT;
2462 int timing_level = standard_timing_level(edid);
2463
2464 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2465 return NULL;
2466
2467 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2468 hsize = t->hsize * 8 + 248;
2469 /* vrefresh_rate = vfreq + 60 */
2470 vrefresh_rate = vfreq + 60;
2471 /* the vdisplay is calculated based on the aspect ratio */
2472 if (aspect_ratio == 0) {
2473 if (edid->revision < 3)
2474 vsize = hsize;
2475 else
2476 vsize = (hsize * 10) / 16;
2477 } else if (aspect_ratio == 1)
2478 vsize = (hsize * 3) / 4;
2479 else if (aspect_ratio == 2)
2480 vsize = (hsize * 4) / 5;
2481 else
2482 vsize = (hsize * 9) / 16;
2483
2484 /* HDTV hack, part 1 */
2485 if (vrefresh_rate == 60 &&
2486 ((hsize == 1360 && vsize == 765) ||
2487 (hsize == 1368 && vsize == 769))) {
2488 hsize = 1366;
2489 vsize = 768;
2490 }
2491
2492 /*
2493 * If this connector already has a mode for this size and refresh
2494 * rate (because it came from detailed or CVT info), use that
2495 * instead. This way we don't have to guess at interlace or
2496 * reduced blanking.
2497 */
2498 list_for_each_entry(m, &connector->probed_modes, head)
2499 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2500 drm_mode_vrefresh(m) == vrefresh_rate)
2501 return NULL;
2502
2503 /* HDTV hack, part 2 */
2504 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2505 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2506 false);
2507 if (!mode)
2508 return NULL;
2509 mode->hdisplay = 1366;
2510 mode->hsync_start = mode->hsync_start - 1;
2511 mode->hsync_end = mode->hsync_end - 1;
2512 return mode;
2513 }
2514
2515 /* check whether it can be found in default mode table */
2516 if (drm_monitor_supports_rb(edid)) {
2517 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2518 true);
2519 if (mode)
2520 return mode;
2521 }
2522 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2523 if (mode)
2524 return mode;
2525
2526 /* okay, generate it */
2527 switch (timing_level) {
2528 case LEVEL_DMT:
2529 break;
2530 case LEVEL_GTF:
2531 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2532 break;
2533 case LEVEL_GTF2:
2534 /*
2535 * This is potentially wrong if there's ever a monitor with
2536 * more than one ranges section, each claiming a different
2537 * secondary GTF curve. Please don't do that.
2538 */
2539 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2540 if (!mode)
2541 return NULL;
2542 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2543 drm_mode_destroy(dev, mode);
2544 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2545 vrefresh_rate, 0, 0,
2546 drm_gtf2_m(edid),
2547 drm_gtf2_2c(edid),
2548 drm_gtf2_k(edid),
2549 drm_gtf2_2j(edid));
2550 }
2551 break;
2552 case LEVEL_CVT:
2553 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2554 false);
2555 break;
2556 }
2557 return mode;
2558 }
2559
2560 /*
2561 * EDID is delightfully ambiguous about how interlaced modes are to be
2562 * encoded. Our internal representation is of frame height, but some
2563 * HDTV detailed timings are encoded as field height.
2564 *
2565 * The format list here is from CEA, in frame size. Technically we
2566 * should be checking refresh rate too. Whatever.
2567 */
2568 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)2569 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2570 struct detailed_pixel_timing *pt)
2571 {
2572 int i;
2573 static const struct {
2574 int w, h;
2575 } cea_interlaced[] = {
2576 { 1920, 1080 },
2577 { 720, 480 },
2578 { 1440, 480 },
2579 { 2880, 480 },
2580 { 720, 576 },
2581 { 1440, 576 },
2582 { 2880, 576 },
2583 };
2584
2585 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2586 return;
2587
2588 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2589 if ((mode->hdisplay == cea_interlaced[i].w) &&
2590 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2591 mode->vdisplay *= 2;
2592 mode->vsync_start *= 2;
2593 mode->vsync_end *= 2;
2594 mode->vtotal *= 2;
2595 mode->vtotal |= 1;
2596 }
2597 }
2598
2599 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2600 }
2601
2602 /**
2603 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2604 * @dev: DRM device (needed to create new mode)
2605 * @edid: EDID block
2606 * @timing: EDID detailed timing info
2607 * @quirks: quirks to apply
2608 *
2609 * An EDID detailed timing block contains enough info for us to create and
2610 * return a new struct drm_display_mode.
2611 */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)2612 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2613 struct edid *edid,
2614 struct detailed_timing *timing,
2615 u32 quirks)
2616 {
2617 struct drm_display_mode *mode;
2618 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2619 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2620 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2621 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2622 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2623 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2624 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2625 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2626 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2627
2628 /* ignore tiny modes */
2629 if (hactive < 64 || vactive < 64)
2630 return NULL;
2631
2632 if (pt->misc & DRM_EDID_PT_STEREO) {
2633 DRM_DEBUG_KMS("stereo mode not supported\n");
2634 return NULL;
2635 }
2636 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2637 DRM_DEBUG_KMS("composite sync not supported\n");
2638 }
2639
2640 /* it is incorrect if hsync/vsync width is zero */
2641 if (!hsync_pulse_width || !vsync_pulse_width) {
2642 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2643 "Wrong Hsync/Vsync pulse width\n");
2644 return NULL;
2645 }
2646
2647 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2648 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2649 if (!mode)
2650 return NULL;
2651
2652 goto set_size;
2653 }
2654
2655 mode = drm_mode_create(dev);
2656 if (!mode)
2657 return NULL;
2658
2659 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2660 timing->pixel_clock = cpu_to_le16(1088);
2661
2662 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2663
2664 mode->hdisplay = hactive;
2665 mode->hsync_start = mode->hdisplay + hsync_offset;
2666 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2667 mode->htotal = mode->hdisplay + hblank;
2668
2669 mode->vdisplay = vactive;
2670 mode->vsync_start = mode->vdisplay + vsync_offset;
2671 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2672 mode->vtotal = mode->vdisplay + vblank;
2673
2674 /* Some EDIDs have bogus h/vtotal values */
2675 if (mode->hsync_end > mode->htotal)
2676 mode->htotal = mode->hsync_end + 1;
2677 if (mode->vsync_end > mode->vtotal)
2678 mode->vtotal = mode->vsync_end + 1;
2679
2680 drm_mode_do_interlace_quirk(mode, pt);
2681
2682 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2683 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2684 }
2685
2686 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2687 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2688 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2689 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2690
2691 set_size:
2692 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2693 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2694
2695 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2696 mode->width_mm *= 10;
2697 mode->height_mm *= 10;
2698 }
2699
2700 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2701 mode->width_mm = edid->width_cm * 10;
2702 mode->height_mm = edid->height_cm * 10;
2703 }
2704
2705 mode->type = DRM_MODE_TYPE_DRIVER;
2706 drm_mode_set_name(mode);
2707
2708 return mode;
2709 }
2710
2711 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2712 mode_in_hsync_range(const struct drm_display_mode *mode,
2713 struct edid *edid, u8 *t)
2714 {
2715 int hsync, hmin, hmax;
2716
2717 hmin = t[7];
2718 if (edid->revision >= 4)
2719 hmin += ((t[4] & 0x04) ? 255 : 0);
2720 hmax = t[8];
2721 if (edid->revision >= 4)
2722 hmax += ((t[4] & 0x08) ? 255 : 0);
2723 hsync = drm_mode_hsync(mode);
2724
2725 return (hsync <= hmax && hsync >= hmin);
2726 }
2727
2728 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2729 mode_in_vsync_range(const struct drm_display_mode *mode,
2730 struct edid *edid, u8 *t)
2731 {
2732 int vsync, vmin, vmax;
2733
2734 vmin = t[5];
2735 if (edid->revision >= 4)
2736 vmin += ((t[4] & 0x01) ? 255 : 0);
2737 vmax = t[6];
2738 if (edid->revision >= 4)
2739 vmax += ((t[4] & 0x02) ? 255 : 0);
2740 vsync = drm_mode_vrefresh(mode);
2741
2742 return (vsync <= vmax && vsync >= vmin);
2743 }
2744
2745 static u32
range_pixel_clock(struct edid * edid,u8 * t)2746 range_pixel_clock(struct edid *edid, u8 *t)
2747 {
2748 /* unspecified */
2749 if (t[9] == 0 || t[9] == 255)
2750 return 0;
2751
2752 /* 1.4 with CVT support gives us real precision, yay */
2753 if (edid->revision >= 4 && t[10] == 0x04)
2754 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2755
2756 /* 1.3 is pathetic, so fuzz up a bit */
2757 return t[9] * 10000 + 5001;
2758 }
2759
2760 static bool
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)2761 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2762 struct detailed_timing *timing)
2763 {
2764 u32 max_clock;
2765 u8 *t = (u8 *)timing;
2766
2767 if (!mode_in_hsync_range(mode, edid, t))
2768 return false;
2769
2770 if (!mode_in_vsync_range(mode, edid, t))
2771 return false;
2772
2773 if ((max_clock = range_pixel_clock(edid, t)))
2774 if (mode->clock > max_clock)
2775 return false;
2776
2777 /* 1.4 max horizontal check */
2778 if (edid->revision >= 4 && t[10] == 0x04)
2779 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2780 return false;
2781
2782 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2783 return false;
2784
2785 return true;
2786 }
2787
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)2788 static bool valid_inferred_mode(const struct drm_connector *connector,
2789 const struct drm_display_mode *mode)
2790 {
2791 const struct drm_display_mode *m;
2792 bool ok = false;
2793
2794 list_for_each_entry(m, &connector->probed_modes, head) {
2795 if (mode->hdisplay == m->hdisplay &&
2796 mode->vdisplay == m->vdisplay &&
2797 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2798 return false; /* duplicated */
2799 if (mode->hdisplay <= m->hdisplay &&
2800 mode->vdisplay <= m->vdisplay)
2801 ok = true;
2802 }
2803 return ok;
2804 }
2805
2806 static int
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2807 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2808 struct detailed_timing *timing)
2809 {
2810 int i, modes = 0;
2811 struct drm_display_mode *newmode;
2812 struct drm_device *dev = connector->dev;
2813
2814 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2815 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2816 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2817 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2818 if (newmode) {
2819 drm_mode_probed_add(connector, newmode);
2820 modes++;
2821 }
2822 }
2823 }
2824
2825 return modes;
2826 }
2827
2828 /* fix up 1366x768 mode from 1368x768;
2829 * GFT/CVT can't express 1366 width which isn't dividable by 8
2830 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)2831 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2832 {
2833 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2834 mode->hdisplay = 1366;
2835 mode->hsync_start--;
2836 mode->hsync_end--;
2837 drm_mode_set_name(mode);
2838 }
2839 }
2840
2841 static int
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2842 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2843 struct detailed_timing *timing)
2844 {
2845 int i, modes = 0;
2846 struct drm_display_mode *newmode;
2847 struct drm_device *dev = connector->dev;
2848
2849 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2850 const struct minimode *m = &extra_modes[i];
2851
2852 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2853 if (!newmode)
2854 return modes;
2855
2856 drm_mode_fixup_1366x768(newmode);
2857 if (!mode_in_range(newmode, edid, timing) ||
2858 !valid_inferred_mode(connector, newmode)) {
2859 drm_mode_destroy(dev, newmode);
2860 continue;
2861 }
2862
2863 drm_mode_probed_add(connector, newmode);
2864 modes++;
2865 }
2866
2867 return modes;
2868 }
2869
2870 static int
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2871 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2872 struct detailed_timing *timing)
2873 {
2874 int i, modes = 0;
2875 struct drm_display_mode *newmode;
2876 struct drm_device *dev = connector->dev;
2877 bool rb = drm_monitor_supports_rb(edid);
2878
2879 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2880 const struct minimode *m = &extra_modes[i];
2881
2882 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2883 if (!newmode)
2884 return modes;
2885
2886 drm_mode_fixup_1366x768(newmode);
2887 if (!mode_in_range(newmode, edid, timing) ||
2888 !valid_inferred_mode(connector, newmode)) {
2889 drm_mode_destroy(dev, newmode);
2890 continue;
2891 }
2892
2893 drm_mode_probed_add(connector, newmode);
2894 modes++;
2895 }
2896
2897 return modes;
2898 }
2899
2900 static void
do_inferred_modes(struct detailed_timing * timing,void * c)2901 do_inferred_modes(struct detailed_timing *timing, void *c)
2902 {
2903 struct detailed_mode_closure *closure = c;
2904 struct detailed_non_pixel *data = &timing->data.other_data;
2905 struct detailed_data_monitor_range *range = &data->data.range;
2906
2907 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2908 return;
2909
2910 closure->modes += drm_dmt_modes_for_range(closure->connector,
2911 closure->edid,
2912 timing);
2913
2914 if (!version_greater(closure->edid, 1, 1))
2915 return; /* GTF not defined yet */
2916
2917 switch (range->flags) {
2918 case 0x02: /* secondary gtf, XXX could do more */
2919 case 0x00: /* default gtf */
2920 closure->modes += drm_gtf_modes_for_range(closure->connector,
2921 closure->edid,
2922 timing);
2923 break;
2924 case 0x04: /* cvt, only in 1.4+ */
2925 if (!version_greater(closure->edid, 1, 3))
2926 break;
2927
2928 closure->modes += drm_cvt_modes_for_range(closure->connector,
2929 closure->edid,
2930 timing);
2931 break;
2932 case 0x01: /* just the ranges, no formula */
2933 default:
2934 break;
2935 }
2936 }
2937
2938 static int
add_inferred_modes(struct drm_connector * connector,struct edid * edid)2939 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2940 {
2941 struct detailed_mode_closure closure = {
2942 .connector = connector,
2943 .edid = edid,
2944 };
2945
2946 if (version_greater(edid, 1, 0))
2947 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2948 &closure);
2949
2950 return closure.modes;
2951 }
2952
2953 static int
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)2954 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2955 {
2956 int i, j, m, modes = 0;
2957 struct drm_display_mode *mode;
2958 u8 *est = ((u8 *)timing) + 6;
2959
2960 for (i = 0; i < 6; i++) {
2961 for (j = 7; j >= 0; j--) {
2962 m = (i * 8) + (7 - j);
2963 if (m >= ARRAY_SIZE(est3_modes))
2964 break;
2965 if (est[i] & (1 << j)) {
2966 mode = drm_mode_find_dmt(connector->dev,
2967 est3_modes[m].w,
2968 est3_modes[m].h,
2969 est3_modes[m].r,
2970 est3_modes[m].rb);
2971 if (mode) {
2972 drm_mode_probed_add(connector, mode);
2973 modes++;
2974 }
2975 }
2976 }
2977 }
2978
2979 return modes;
2980 }
2981
2982 static void
do_established_modes(struct detailed_timing * timing,void * c)2983 do_established_modes(struct detailed_timing *timing, void *c)
2984 {
2985 struct detailed_mode_closure *closure = c;
2986
2987 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2988 return;
2989
2990 closure->modes += drm_est3_modes(closure->connector, timing);
2991 }
2992
2993 /**
2994 * add_established_modes - get est. modes from EDID and add them
2995 * @connector: connector to add mode(s) to
2996 * @edid: EDID block to scan
2997 *
2998 * Each EDID block contains a bitmap of the supported "established modes" list
2999 * (defined above). Tease them out and add them to the global modes list.
3000 */
3001 static int
add_established_modes(struct drm_connector * connector,struct edid * edid)3002 add_established_modes(struct drm_connector *connector, struct edid *edid)
3003 {
3004 struct drm_device *dev = connector->dev;
3005 unsigned long est_bits = edid->established_timings.t1 |
3006 (edid->established_timings.t2 << 8) |
3007 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3008 int i, modes = 0;
3009 struct detailed_mode_closure closure = {
3010 .connector = connector,
3011 .edid = edid,
3012 };
3013
3014 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3015 if (est_bits & (1<<i)) {
3016 struct drm_display_mode *newmode;
3017
3018 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3019 if (newmode) {
3020 drm_mode_probed_add(connector, newmode);
3021 modes++;
3022 }
3023 }
3024 }
3025
3026 if (version_greater(edid, 1, 0))
3027 drm_for_each_detailed_block((u8 *)edid,
3028 do_established_modes, &closure);
3029
3030 return modes + closure.modes;
3031 }
3032
3033 static void
do_standard_modes(struct detailed_timing * timing,void * c)3034 do_standard_modes(struct detailed_timing *timing, void *c)
3035 {
3036 struct detailed_mode_closure *closure = c;
3037 struct detailed_non_pixel *data = &timing->data.other_data;
3038 struct drm_connector *connector = closure->connector;
3039 struct edid *edid = closure->edid;
3040 int i;
3041
3042 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3043 return;
3044
3045 for (i = 0; i < 6; i++) {
3046 struct std_timing *std = &data->data.timings[i];
3047 struct drm_display_mode *newmode;
3048
3049 newmode = drm_mode_std(connector, edid, std);
3050 if (newmode) {
3051 drm_mode_probed_add(connector, newmode);
3052 closure->modes++;
3053 }
3054 }
3055 }
3056
3057 /**
3058 * add_standard_modes - get std. modes from EDID and add them
3059 * @connector: connector to add mode(s) to
3060 * @edid: EDID block to scan
3061 *
3062 * Standard modes can be calculated using the appropriate standard (DMT,
3063 * GTF or CVT. Grab them from @edid and add them to the list.
3064 */
3065 static int
add_standard_modes(struct drm_connector * connector,struct edid * edid)3066 add_standard_modes(struct drm_connector *connector, struct edid *edid)
3067 {
3068 int i, modes = 0;
3069 struct detailed_mode_closure closure = {
3070 .connector = connector,
3071 .edid = edid,
3072 };
3073
3074 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3075 struct drm_display_mode *newmode;
3076
3077 newmode = drm_mode_std(connector, edid,
3078 &edid->standard_timings[i]);
3079 if (newmode) {
3080 drm_mode_probed_add(connector, newmode);
3081 modes++;
3082 }
3083 }
3084
3085 if (version_greater(edid, 1, 0))
3086 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3087 &closure);
3088
3089 /* XXX should also look for standard codes in VTB blocks */
3090
3091 return modes + closure.modes;
3092 }
3093
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)3094 static int drm_cvt_modes(struct drm_connector *connector,
3095 struct detailed_timing *timing)
3096 {
3097 int i, j, modes = 0;
3098 struct drm_display_mode *newmode;
3099 struct drm_device *dev = connector->dev;
3100 struct cvt_timing *cvt;
3101 const int rates[] = { 60, 85, 75, 60, 50 };
3102 const u8 empty[3] = { 0, 0, 0 };
3103
3104 for (i = 0; i < 4; i++) {
3105 int width, height;
3106
3107 cvt = &(timing->data.other_data.data.cvt[i]);
3108
3109 if (!memcmp(cvt->code, empty, 3))
3110 continue;
3111
3112 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3113 switch (cvt->code[1] & 0x0c) {
3114 /* default - because compiler doesn't see that we've enumerated all cases */
3115 default:
3116 case 0x00:
3117 width = height * 4 / 3;
3118 break;
3119 case 0x04:
3120 width = height * 16 / 9;
3121 break;
3122 case 0x08:
3123 width = height * 16 / 10;
3124 break;
3125 case 0x0c:
3126 width = height * 15 / 9;
3127 break;
3128 }
3129
3130 for (j = 1; j < 5; j++) {
3131 if (cvt->code[2] & (1 << j)) {
3132 newmode = drm_cvt_mode(dev, width, height,
3133 rates[j], j == 0,
3134 false, false);
3135 if (newmode) {
3136 drm_mode_probed_add(connector, newmode);
3137 modes++;
3138 }
3139 }
3140 }
3141 }
3142
3143 return modes;
3144 }
3145
3146 static void
do_cvt_mode(struct detailed_timing * timing,void * c)3147 do_cvt_mode(struct detailed_timing *timing, void *c)
3148 {
3149 struct detailed_mode_closure *closure = c;
3150
3151 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3152 return;
3153
3154 closure->modes += drm_cvt_modes(closure->connector, timing);
3155 }
3156
3157 static int
add_cvt_modes(struct drm_connector * connector,struct edid * edid)3158 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3159 {
3160 struct detailed_mode_closure closure = {
3161 .connector = connector,
3162 .edid = edid,
3163 };
3164
3165 if (version_greater(edid, 1, 2))
3166 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3167
3168 /* XXX should also look for CVT codes in VTB blocks */
3169
3170 return closure.modes;
3171 }
3172
3173 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3174
3175 static void
do_detailed_mode(struct detailed_timing * timing,void * c)3176 do_detailed_mode(struct detailed_timing *timing, void *c)
3177 {
3178 struct detailed_mode_closure *closure = c;
3179 struct drm_display_mode *newmode;
3180
3181 if (!is_detailed_timing_descriptor((const u8 *)timing))
3182 return;
3183
3184 newmode = drm_mode_detailed(closure->connector->dev,
3185 closure->edid, timing,
3186 closure->quirks);
3187 if (!newmode)
3188 return;
3189
3190 if (closure->preferred)
3191 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3192
3193 /*
3194 * Detailed modes are limited to 10kHz pixel clock resolution,
3195 * so fix up anything that looks like CEA/HDMI mode, but the clock
3196 * is just slightly off.
3197 */
3198 fixup_detailed_cea_mode_clock(newmode);
3199
3200 drm_mode_probed_add(closure->connector, newmode);
3201 closure->modes++;
3202 closure->preferred = false;
3203 }
3204
3205 /*
3206 * add_detailed_modes - Add modes from detailed timings
3207 * @connector: attached connector
3208 * @edid: EDID block to scan
3209 * @quirks: quirks to apply
3210 */
3211 static int
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)3212 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3213 u32 quirks)
3214 {
3215 struct detailed_mode_closure closure = {
3216 .connector = connector,
3217 .edid = edid,
3218 .preferred = true,
3219 .quirks = quirks,
3220 };
3221
3222 if (closure.preferred && !version_greater(edid, 1, 3))
3223 closure.preferred =
3224 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3225
3226 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3227
3228 return closure.modes;
3229 }
3230
3231 #define AUDIO_BLOCK 0x01
3232 #define VIDEO_BLOCK 0x02
3233 #define VENDOR_BLOCK 0x03
3234 #define SPEAKER_BLOCK 0x04
3235 #define HDR_STATIC_METADATA_BLOCK 0x6
3236 #define USE_EXTENDED_TAG 0x07
3237 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3238 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3239 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3240 #define EDID_BASIC_AUDIO (1 << 6)
3241 #define EDID_CEA_YCRCB444 (1 << 5)
3242 #define EDID_CEA_YCRCB422 (1 << 4)
3243 #define EDID_CEA_VCDB_QS (1 << 6)
3244
3245 /*
3246 * Search EDID for CEA extension block.
3247 */
drm_find_edid_extension(const struct edid * edid,int ext_id,int * ext_index)3248 static u8 *drm_find_edid_extension(const struct edid *edid,
3249 int ext_id, int *ext_index)
3250 {
3251 u8 *edid_ext = NULL;
3252 int i;
3253
3254 /* No EDID or EDID extensions */
3255 if (edid == NULL || edid->extensions == 0)
3256 return NULL;
3257
3258 /* Find CEA extension */
3259 for (i = *ext_index; i < edid->extensions; i++) {
3260 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3261 if (edid_ext[0] == ext_id)
3262 break;
3263 }
3264
3265 if (i >= edid->extensions)
3266 return NULL;
3267
3268 *ext_index = i + 1;
3269
3270 return edid_ext;
3271 }
3272
3273
drm_find_displayid_extension(const struct edid * edid,int * length,int * idx,int * ext_index)3274 static u8 *drm_find_displayid_extension(const struct edid *edid,
3275 int *length, int *idx,
3276 int *ext_index)
3277 {
3278 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
3279 struct displayid_hdr *base;
3280 int ret;
3281
3282 if (!displayid)
3283 return NULL;
3284
3285 /* EDID extensions block checksum isn't for us */
3286 *length = EDID_LENGTH - 1;
3287 *idx = 1;
3288
3289 ret = validate_displayid(displayid, *length, *idx);
3290 if (ret)
3291 return NULL;
3292
3293 base = (struct displayid_hdr *)&displayid[*idx];
3294 *length = *idx + sizeof(*base) + base->bytes;
3295
3296 return displayid;
3297 }
3298
drm_find_cea_extension(const struct edid * edid)3299 static u8 *drm_find_cea_extension(const struct edid *edid)
3300 {
3301 int length, idx;
3302 struct displayid_block *block;
3303 u8 *cea;
3304 u8 *displayid;
3305 int ext_index;
3306
3307 /* Look for a top level CEA extension block */
3308 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3309 ext_index = 0;
3310 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3311 if (cea)
3312 return cea;
3313
3314 /* CEA blocks can also be found embedded in a DisplayID block */
3315 ext_index = 0;
3316 for (;;) {
3317 displayid = drm_find_displayid_extension(edid, &length, &idx,
3318 &ext_index);
3319 if (!displayid)
3320 return NULL;
3321
3322 idx += sizeof(struct displayid_hdr);
3323 for_each_displayid_db(displayid, block, idx, length) {
3324 if (block->tag == DATA_BLOCK_CTA)
3325 return (u8 *)block;
3326 }
3327 }
3328
3329 return NULL;
3330 }
3331
cea_mode_for_vic(u8 vic)3332 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3333 {
3334 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3335 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3336
3337 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3338 return &edid_cea_modes_1[vic - 1];
3339 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3340 return &edid_cea_modes_193[vic - 193];
3341 return NULL;
3342 }
3343
cea_num_vics(void)3344 static u8 cea_num_vics(void)
3345 {
3346 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3347 }
3348
cea_next_vic(u8 vic)3349 static u8 cea_next_vic(u8 vic)
3350 {
3351 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3352 vic = 193;
3353 return vic;
3354 }
3355
3356 /*
3357 * Calculate the alternate clock for the CEA mode
3358 * (60Hz vs. 59.94Hz etc.)
3359 */
3360 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)3361 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3362 {
3363 unsigned int clock = cea_mode->clock;
3364
3365 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3366 return clock;
3367
3368 /*
3369 * edid_cea_modes contains the 59.94Hz
3370 * variant for 240 and 480 line modes,
3371 * and the 60Hz variant otherwise.
3372 */
3373 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3374 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3375 else
3376 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3377
3378 return clock;
3379 }
3380
3381 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)3382 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3383 {
3384 /*
3385 * For certain VICs the spec allows the vertical
3386 * front porch to vary by one or two lines.
3387 *
3388 * cea_modes[] stores the variant with the shortest
3389 * vertical front porch. We can adjust the mode to
3390 * get the other variants by simply increasing the
3391 * vertical front porch length.
3392 */
3393 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3394 cea_mode_for_vic(9)->vtotal != 262 ||
3395 cea_mode_for_vic(12)->vtotal != 262 ||
3396 cea_mode_for_vic(13)->vtotal != 262 ||
3397 cea_mode_for_vic(23)->vtotal != 312 ||
3398 cea_mode_for_vic(24)->vtotal != 312 ||
3399 cea_mode_for_vic(27)->vtotal != 312 ||
3400 cea_mode_for_vic(28)->vtotal != 312);
3401
3402 if (((vic == 8 || vic == 9 ||
3403 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3404 ((vic == 23 || vic == 24 ||
3405 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3406 mode->vsync_start++;
3407 mode->vsync_end++;
3408 mode->vtotal++;
3409
3410 return true;
3411 }
3412
3413 return false;
3414 }
3415
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3416 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3417 unsigned int clock_tolerance)
3418 {
3419 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3420 u8 vic;
3421
3422 if (!to_match->clock)
3423 return 0;
3424
3425 if (to_match->picture_aspect_ratio)
3426 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3427
3428 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3429 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3430 unsigned int clock1, clock2;
3431
3432 /* Check both 60Hz and 59.94Hz */
3433 clock1 = cea_mode.clock;
3434 clock2 = cea_mode_alternate_clock(&cea_mode);
3435
3436 if (abs(to_match->clock - clock1) > clock_tolerance &&
3437 abs(to_match->clock - clock2) > clock_tolerance)
3438 continue;
3439
3440 do {
3441 if (drm_mode_match(to_match, &cea_mode, match_flags))
3442 return vic;
3443 } while (cea_mode_alternate_timings(vic, &cea_mode));
3444 }
3445
3446 return 0;
3447 }
3448
3449 /**
3450 * drm_match_cea_mode - look for a CEA mode matching given mode
3451 * @to_match: display mode
3452 *
3453 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3454 * mode.
3455 */
drm_match_cea_mode(const struct drm_display_mode * to_match)3456 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3457 {
3458 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3459 u8 vic;
3460
3461 if (!to_match->clock)
3462 return 0;
3463
3464 if (to_match->picture_aspect_ratio)
3465 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3466
3467 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3468 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3469 unsigned int clock1, clock2;
3470
3471 /* Check both 60Hz and 59.94Hz */
3472 clock1 = cea_mode.clock;
3473 clock2 = cea_mode_alternate_clock(&cea_mode);
3474
3475 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3476 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3477 continue;
3478
3479 do {
3480 if (drm_mode_match(to_match, &cea_mode, match_flags))
3481 return vic;
3482 } while (cea_mode_alternate_timings(vic, &cea_mode));
3483 }
3484
3485 return 0;
3486 }
3487 EXPORT_SYMBOL(drm_match_cea_mode);
3488
drm_valid_cea_vic(u8 vic)3489 static bool drm_valid_cea_vic(u8 vic)
3490 {
3491 return cea_mode_for_vic(vic) != NULL;
3492 }
3493
drm_get_cea_aspect_ratio(const u8 video_code)3494 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3495 {
3496 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3497
3498 if (mode)
3499 return mode->picture_aspect_ratio;
3500
3501 return HDMI_PICTURE_ASPECT_NONE;
3502 }
3503
drm_get_hdmi_aspect_ratio(const u8 video_code)3504 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3505 {
3506 return edid_4k_modes[video_code].picture_aspect_ratio;
3507 }
3508
3509 /*
3510 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3511 * specific block).
3512 */
3513 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3514 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3515 {
3516 return cea_mode_alternate_clock(hdmi_mode);
3517 }
3518
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3519 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3520 unsigned int clock_tolerance)
3521 {
3522 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3523 u8 vic;
3524
3525 if (!to_match->clock)
3526 return 0;
3527
3528 if (to_match->picture_aspect_ratio)
3529 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3530
3531 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3532 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3533 unsigned int clock1, clock2;
3534
3535 /* Make sure to also match alternate clocks */
3536 clock1 = hdmi_mode->clock;
3537 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3538
3539 if (abs(to_match->clock - clock1) > clock_tolerance &&
3540 abs(to_match->clock - clock2) > clock_tolerance)
3541 continue;
3542
3543 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3544 return vic;
3545 }
3546
3547 return 0;
3548 }
3549
3550 /*
3551 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3552 * @to_match: display mode
3553 *
3554 * An HDMI mode is one defined in the HDMI vendor specific block.
3555 *
3556 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3557 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3558 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3559 {
3560 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3561 u8 vic;
3562
3563 if (!to_match->clock)
3564 return 0;
3565
3566 if (to_match->picture_aspect_ratio)
3567 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3568
3569 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3570 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3571 unsigned int clock1, clock2;
3572
3573 /* Make sure to also match alternate clocks */
3574 clock1 = hdmi_mode->clock;
3575 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3576
3577 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3578 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3579 drm_mode_match(to_match, hdmi_mode, match_flags))
3580 return vic;
3581 }
3582 return 0;
3583 }
3584
drm_valid_hdmi_vic(u8 vic)3585 static bool drm_valid_hdmi_vic(u8 vic)
3586 {
3587 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3588 }
3589
3590 static int
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3591 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3592 {
3593 struct drm_device *dev = connector->dev;
3594 struct drm_display_mode *mode, *tmp;
3595 LIST_HEAD(list);
3596 int modes = 0;
3597
3598 /* Don't add CEA modes if the CEA extension block is missing */
3599 if (!drm_find_cea_extension(edid))
3600 return 0;
3601
3602 /*
3603 * Go through all probed modes and create a new mode
3604 * with the alternate clock for certain CEA modes.
3605 */
3606 list_for_each_entry(mode, &connector->probed_modes, head) {
3607 const struct drm_display_mode *cea_mode = NULL;
3608 struct drm_display_mode *newmode;
3609 u8 vic = drm_match_cea_mode(mode);
3610 unsigned int clock1, clock2;
3611
3612 if (drm_valid_cea_vic(vic)) {
3613 cea_mode = cea_mode_for_vic(vic);
3614 clock2 = cea_mode_alternate_clock(cea_mode);
3615 } else {
3616 vic = drm_match_hdmi_mode(mode);
3617 if (drm_valid_hdmi_vic(vic)) {
3618 cea_mode = &edid_4k_modes[vic];
3619 clock2 = hdmi_mode_alternate_clock(cea_mode);
3620 }
3621 }
3622
3623 if (!cea_mode)
3624 continue;
3625
3626 clock1 = cea_mode->clock;
3627
3628 if (clock1 == clock2)
3629 continue;
3630
3631 if (mode->clock != clock1 && mode->clock != clock2)
3632 continue;
3633
3634 newmode = drm_mode_duplicate(dev, cea_mode);
3635 if (!newmode)
3636 continue;
3637
3638 /* Carry over the stereo flags */
3639 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3640
3641 /*
3642 * The current mode could be either variant. Make
3643 * sure to pick the "other" clock for the new mode.
3644 */
3645 if (mode->clock != clock1)
3646 newmode->clock = clock1;
3647 else
3648 newmode->clock = clock2;
3649
3650 list_add_tail(&newmode->head, &list);
3651 }
3652
3653 list_for_each_entry_safe(mode, tmp, &list, head) {
3654 list_del(&mode->head);
3655 drm_mode_probed_add(connector, mode);
3656 modes++;
3657 }
3658
3659 return modes;
3660 }
3661
svd_to_vic(u8 svd)3662 static u8 svd_to_vic(u8 svd)
3663 {
3664 /* 0-6 bit vic, 7th bit native mode indicator */
3665 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3666 return svd & 127;
3667
3668 return svd;
3669 }
3670
3671 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3672 drm_display_mode_from_vic_index(struct drm_connector *connector,
3673 const u8 *video_db, u8 video_len,
3674 u8 video_index)
3675 {
3676 struct drm_device *dev = connector->dev;
3677 struct drm_display_mode *newmode;
3678 u8 vic;
3679
3680 if (video_db == NULL || video_index >= video_len)
3681 return NULL;
3682
3683 /* CEA modes are numbered 1..127 */
3684 vic = svd_to_vic(video_db[video_index]);
3685 if (!drm_valid_cea_vic(vic))
3686 return NULL;
3687
3688 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3689 if (!newmode)
3690 return NULL;
3691
3692 return newmode;
3693 }
3694
3695 /*
3696 * do_y420vdb_modes - Parse YCBCR 420 only modes
3697 * @connector: connector corresponding to the HDMI sink
3698 * @svds: start of the data block of CEA YCBCR 420 VDB
3699 * @len: length of the CEA YCBCR 420 VDB
3700 *
3701 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3702 * which contains modes which can be supported in YCBCR 420
3703 * output format only.
3704 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3705 static int do_y420vdb_modes(struct drm_connector *connector,
3706 const u8 *svds, u8 svds_len)
3707 {
3708 int modes = 0, i;
3709 struct drm_device *dev = connector->dev;
3710 struct drm_display_info *info = &connector->display_info;
3711 struct drm_hdmi_info *hdmi = &info->hdmi;
3712
3713 for (i = 0; i < svds_len; i++) {
3714 u8 vic = svd_to_vic(svds[i]);
3715 struct drm_display_mode *newmode;
3716
3717 if (!drm_valid_cea_vic(vic))
3718 continue;
3719
3720 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3721 if (!newmode)
3722 break;
3723 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3724 drm_mode_probed_add(connector, newmode);
3725 modes++;
3726 }
3727
3728 if (modes > 0)
3729 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3730 return modes;
3731 }
3732
3733 /*
3734 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3735 * @connector: connector corresponding to the HDMI sink
3736 * @vic: CEA vic for the video mode to be added in the map
3737 *
3738 * Makes an entry for a videomode in the YCBCR 420 bitmap
3739 */
3740 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3741 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3742 {
3743 u8 vic = svd_to_vic(svd);
3744 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3745
3746 if (!drm_valid_cea_vic(vic))
3747 return;
3748
3749 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3750 }
3751
3752 /**
3753 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3754 * @dev: DRM device
3755 * @video_code: CEA VIC of the mode
3756 *
3757 * Creates a new mode matching the specified CEA VIC.
3758 *
3759 * Returns: A new drm_display_mode on success or NULL on failure
3760 */
3761 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)3762 drm_display_mode_from_cea_vic(struct drm_device *dev,
3763 u8 video_code)
3764 {
3765 const struct drm_display_mode *cea_mode;
3766 struct drm_display_mode *newmode;
3767
3768 cea_mode = cea_mode_for_vic(video_code);
3769 if (!cea_mode)
3770 return NULL;
3771
3772 newmode = drm_mode_duplicate(dev, cea_mode);
3773 if (!newmode)
3774 return NULL;
3775
3776 return newmode;
3777 }
3778 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3779
3780 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3781 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3782 {
3783 int i, modes = 0;
3784 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3785
3786 for (i = 0; i < len; i++) {
3787 struct drm_display_mode *mode;
3788
3789 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3790 if (mode) {
3791 /*
3792 * YCBCR420 capability block contains a bitmap which
3793 * gives the index of CEA modes from CEA VDB, which
3794 * can support YCBCR 420 sampling output also (apart
3795 * from RGB/YCBCR444 etc).
3796 * For example, if the bit 0 in bitmap is set,
3797 * first mode in VDB can support YCBCR420 output too.
3798 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3799 */
3800 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3801 drm_add_cmdb_modes(connector, db[i]);
3802
3803 drm_mode_probed_add(connector, mode);
3804 modes++;
3805 }
3806 }
3807
3808 return modes;
3809 }
3810
3811 struct stereo_mandatory_mode {
3812 int width, height, vrefresh;
3813 unsigned int flags;
3814 };
3815
3816 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3817 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3818 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3819 { 1920, 1080, 50,
3820 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3821 { 1920, 1080, 60,
3822 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3823 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3824 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3825 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3826 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3827 };
3828
3829 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)3830 stereo_match_mandatory(const struct drm_display_mode *mode,
3831 const struct stereo_mandatory_mode *stereo_mode)
3832 {
3833 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3834
3835 return mode->hdisplay == stereo_mode->width &&
3836 mode->vdisplay == stereo_mode->height &&
3837 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3838 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3839 }
3840
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)3841 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3842 {
3843 struct drm_device *dev = connector->dev;
3844 const struct drm_display_mode *mode;
3845 struct list_head stereo_modes;
3846 int modes = 0, i;
3847
3848 INIT_LIST_HEAD(&stereo_modes);
3849
3850 list_for_each_entry(mode, &connector->probed_modes, head) {
3851 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3852 const struct stereo_mandatory_mode *mandatory;
3853 struct drm_display_mode *new_mode;
3854
3855 if (!stereo_match_mandatory(mode,
3856 &stereo_mandatory_modes[i]))
3857 continue;
3858
3859 mandatory = &stereo_mandatory_modes[i];
3860 new_mode = drm_mode_duplicate(dev, mode);
3861 if (!new_mode)
3862 continue;
3863
3864 new_mode->flags |= mandatory->flags;
3865 list_add_tail(&new_mode->head, &stereo_modes);
3866 modes++;
3867 }
3868 }
3869
3870 list_splice_tail(&stereo_modes, &connector->probed_modes);
3871
3872 return modes;
3873 }
3874
add_hdmi_mode(struct drm_connector * connector,u8 vic)3875 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3876 {
3877 struct drm_device *dev = connector->dev;
3878 struct drm_display_mode *newmode;
3879
3880 if (!drm_valid_hdmi_vic(vic)) {
3881 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3882 return 0;
3883 }
3884
3885 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3886 if (!newmode)
3887 return 0;
3888
3889 drm_mode_probed_add(connector, newmode);
3890
3891 return 1;
3892 }
3893
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)3894 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3895 const u8 *video_db, u8 video_len, u8 video_index)
3896 {
3897 struct drm_display_mode *newmode;
3898 int modes = 0;
3899
3900 if (structure & (1 << 0)) {
3901 newmode = drm_display_mode_from_vic_index(connector, video_db,
3902 video_len,
3903 video_index);
3904 if (newmode) {
3905 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3906 drm_mode_probed_add(connector, newmode);
3907 modes++;
3908 }
3909 }
3910 if (structure & (1 << 6)) {
3911 newmode = drm_display_mode_from_vic_index(connector, video_db,
3912 video_len,
3913 video_index);
3914 if (newmode) {
3915 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3916 drm_mode_probed_add(connector, newmode);
3917 modes++;
3918 }
3919 }
3920 if (structure & (1 << 8)) {
3921 newmode = drm_display_mode_from_vic_index(connector, video_db,
3922 video_len,
3923 video_index);
3924 if (newmode) {
3925 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3926 drm_mode_probed_add(connector, newmode);
3927 modes++;
3928 }
3929 }
3930
3931 return modes;
3932 }
3933
3934 /*
3935 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3936 * @connector: connector corresponding to the HDMI sink
3937 * @db: start of the CEA vendor specific block
3938 * @len: length of the CEA block payload, ie. one can access up to db[len]
3939 *
3940 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3941 * also adds the stereo 3d modes when applicable.
3942 */
3943 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)3944 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3945 const u8 *video_db, u8 video_len)
3946 {
3947 struct drm_display_info *info = &connector->display_info;
3948 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3949 u8 vic_len, hdmi_3d_len = 0;
3950 u16 mask;
3951 u16 structure_all;
3952
3953 if (len < 8)
3954 goto out;
3955
3956 /* no HDMI_Video_Present */
3957 if (!(db[8] & (1 << 5)))
3958 goto out;
3959
3960 /* Latency_Fields_Present */
3961 if (db[8] & (1 << 7))
3962 offset += 2;
3963
3964 /* I_Latency_Fields_Present */
3965 if (db[8] & (1 << 6))
3966 offset += 2;
3967
3968 /* the declared length is not long enough for the 2 first bytes
3969 * of additional video format capabilities */
3970 if (len < (8 + offset + 2))
3971 goto out;
3972
3973 /* 3D_Present */
3974 offset++;
3975 if (db[8 + offset] & (1 << 7)) {
3976 modes += add_hdmi_mandatory_stereo_modes(connector);
3977
3978 /* 3D_Multi_present */
3979 multi_present = (db[8 + offset] & 0x60) >> 5;
3980 }
3981
3982 offset++;
3983 vic_len = db[8 + offset] >> 5;
3984 hdmi_3d_len = db[8 + offset] & 0x1f;
3985
3986 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3987 u8 vic;
3988
3989 vic = db[9 + offset + i];
3990 modes += add_hdmi_mode(connector, vic);
3991 }
3992 offset += 1 + vic_len;
3993
3994 if (multi_present == 1)
3995 multi_len = 2;
3996 else if (multi_present == 2)
3997 multi_len = 4;
3998 else
3999 multi_len = 0;
4000
4001 if (len < (8 + offset + hdmi_3d_len - 1))
4002 goto out;
4003
4004 if (hdmi_3d_len < multi_len)
4005 goto out;
4006
4007 if (multi_present == 1 || multi_present == 2) {
4008 /* 3D_Structure_ALL */
4009 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4010
4011 /* check if 3D_MASK is present */
4012 if (multi_present == 2)
4013 mask = (db[10 + offset] << 8) | db[11 + offset];
4014 else
4015 mask = 0xffff;
4016
4017 for (i = 0; i < 16; i++) {
4018 if (mask & (1 << i))
4019 modes += add_3d_struct_modes(connector,
4020 structure_all,
4021 video_db,
4022 video_len, i);
4023 }
4024 }
4025
4026 offset += multi_len;
4027
4028 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4029 int vic_index;
4030 struct drm_display_mode *newmode = NULL;
4031 unsigned int newflag = 0;
4032 bool detail_present;
4033
4034 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4035
4036 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4037 break;
4038
4039 /* 2D_VIC_order_X */
4040 vic_index = db[8 + offset + i] >> 4;
4041
4042 /* 3D_Structure_X */
4043 switch (db[8 + offset + i] & 0x0f) {
4044 case 0:
4045 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4046 break;
4047 case 6:
4048 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4049 break;
4050 case 8:
4051 /* 3D_Detail_X */
4052 if ((db[9 + offset + i] >> 4) == 1)
4053 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4054 break;
4055 }
4056
4057 if (newflag != 0) {
4058 newmode = drm_display_mode_from_vic_index(connector,
4059 video_db,
4060 video_len,
4061 vic_index);
4062
4063 if (newmode) {
4064 newmode->flags |= newflag;
4065 drm_mode_probed_add(connector, newmode);
4066 modes++;
4067 }
4068 }
4069
4070 if (detail_present)
4071 i++;
4072 }
4073
4074 out:
4075 if (modes > 0)
4076 info->has_hdmi_infoframe = true;
4077 return modes;
4078 }
4079
4080 static int
cea_db_payload_len(const u8 * db)4081 cea_db_payload_len(const u8 *db)
4082 {
4083 return db[0] & 0x1f;
4084 }
4085
4086 static int
cea_db_extended_tag(const u8 * db)4087 cea_db_extended_tag(const u8 *db)
4088 {
4089 return db[1];
4090 }
4091
4092 static int
cea_db_tag(const u8 * db)4093 cea_db_tag(const u8 *db)
4094 {
4095 return db[0] >> 5;
4096 }
4097
4098 static int
cea_revision(const u8 * cea)4099 cea_revision(const u8 *cea)
4100 {
4101 /*
4102 * FIXME is this correct for the DispID variant?
4103 * The DispID spec doesn't really specify whether
4104 * this is the revision of the CEA extension or
4105 * the DispID CEA data block. And the only value
4106 * given as an example is 0.
4107 */
4108 return cea[1];
4109 }
4110
4111 static int
cea_db_offsets(const u8 * cea,int * start,int * end)4112 cea_db_offsets(const u8 *cea, int *start, int *end)
4113 {
4114 /* DisplayID CTA extension blocks and top-level CEA EDID
4115 * block header definitions differ in the following bytes:
4116 * 1) Byte 2 of the header specifies length differently,
4117 * 2) Byte 3 is only present in the CEA top level block.
4118 *
4119 * The different definitions for byte 2 follow.
4120 *
4121 * DisplayID CTA extension block defines byte 2 as:
4122 * Number of payload bytes
4123 *
4124 * CEA EDID block defines byte 2 as:
4125 * Byte number (decimal) within this block where the 18-byte
4126 * DTDs begin. If no non-DTD data is present in this extension
4127 * block, the value should be set to 04h (the byte after next).
4128 * If set to 00h, there are no DTDs present in this block and
4129 * no non-DTD data.
4130 */
4131 if (cea[0] == DATA_BLOCK_CTA) {
4132 /*
4133 * for_each_displayid_db() has already verified
4134 * that these stay within expected bounds.
4135 */
4136 *start = 3;
4137 *end = *start + cea[2];
4138 } else if (cea[0] == CEA_EXT) {
4139 /* Data block offset in CEA extension block */
4140 *start = 4;
4141 *end = cea[2];
4142 if (*end == 0)
4143 *end = 127;
4144 if (*end < 4 || *end > 127)
4145 return -ERANGE;
4146 } else {
4147 return -EOPNOTSUPP;
4148 }
4149
4150 return 0;
4151 }
4152
cea_db_is_hdmi_vsdb(const u8 * db)4153 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4154 {
4155 int hdmi_id;
4156
4157 if (cea_db_tag(db) != VENDOR_BLOCK)
4158 return false;
4159
4160 if (cea_db_payload_len(db) < 5)
4161 return false;
4162
4163 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4164
4165 return hdmi_id == HDMI_IEEE_OUI;
4166 }
4167
cea_db_is_hdmi_forum_vsdb(const u8 * db)4168 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4169 {
4170 unsigned int oui;
4171
4172 if (cea_db_tag(db) != VENDOR_BLOCK)
4173 return false;
4174
4175 if (cea_db_payload_len(db) < 7)
4176 return false;
4177
4178 oui = db[3] << 16 | db[2] << 8 | db[1];
4179
4180 return oui == HDMI_FORUM_IEEE_OUI;
4181 }
4182
cea_db_is_vcdb(const u8 * db)4183 static bool cea_db_is_vcdb(const u8 *db)
4184 {
4185 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4186 return false;
4187
4188 if (cea_db_payload_len(db) != 2)
4189 return false;
4190
4191 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4192 return false;
4193
4194 return true;
4195 }
4196
cea_db_is_y420cmdb(const u8 * db)4197 static bool cea_db_is_y420cmdb(const u8 *db)
4198 {
4199 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4200 return false;
4201
4202 if (!cea_db_payload_len(db))
4203 return false;
4204
4205 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4206 return false;
4207
4208 return true;
4209 }
4210
cea_db_is_y420vdb(const u8 * db)4211 static bool cea_db_is_y420vdb(const u8 *db)
4212 {
4213 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4214 return false;
4215
4216 if (!cea_db_payload_len(db))
4217 return false;
4218
4219 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4220 return false;
4221
4222 return true;
4223 }
4224
4225 #define for_each_cea_db(cea, i, start, end) \
4226 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4227
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)4228 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4229 const u8 *db)
4230 {
4231 struct drm_display_info *info = &connector->display_info;
4232 struct drm_hdmi_info *hdmi = &info->hdmi;
4233 u8 map_len = cea_db_payload_len(db) - 1;
4234 u8 count;
4235 u64 map = 0;
4236
4237 if (map_len == 0) {
4238 /* All CEA modes support ycbcr420 sampling also.*/
4239 hdmi->y420_cmdb_map = U64_MAX;
4240 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4241 return;
4242 }
4243
4244 /*
4245 * This map indicates which of the existing CEA block modes
4246 * from VDB can support YCBCR420 output too. So if bit=0 is
4247 * set, first mode from VDB can support YCBCR420 output too.
4248 * We will parse and keep this map, before parsing VDB itself
4249 * to avoid going through the same block again and again.
4250 *
4251 * Spec is not clear about max possible size of this block.
4252 * Clamping max bitmap block size at 8 bytes. Every byte can
4253 * address 8 CEA modes, in this way this map can address
4254 * 8*8 = first 64 SVDs.
4255 */
4256 if (WARN_ON_ONCE(map_len > 8))
4257 map_len = 8;
4258
4259 for (count = 0; count < map_len; count++)
4260 map |= (u64)db[2 + count] << (8 * count);
4261
4262 if (map)
4263 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4264
4265 hdmi->y420_cmdb_map = map;
4266 }
4267
4268 static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)4269 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4270 {
4271 const u8 *cea = drm_find_cea_extension(edid);
4272 const u8 *db, *hdmi = NULL, *video = NULL;
4273 u8 dbl, hdmi_len, video_len = 0;
4274 int modes = 0;
4275
4276 if (cea && cea_revision(cea) >= 3) {
4277 int i, start, end;
4278
4279 if (cea_db_offsets(cea, &start, &end))
4280 return 0;
4281
4282 for_each_cea_db(cea, i, start, end) {
4283 db = &cea[i];
4284 dbl = cea_db_payload_len(db);
4285
4286 if (cea_db_tag(db) == VIDEO_BLOCK) {
4287 video = db + 1;
4288 video_len = dbl;
4289 modes += do_cea_modes(connector, video, dbl);
4290 } else if (cea_db_is_hdmi_vsdb(db)) {
4291 hdmi = db;
4292 hdmi_len = dbl;
4293 } else if (cea_db_is_y420vdb(db)) {
4294 const u8 *vdb420 = &db[2];
4295
4296 /* Add 4:2:0(only) modes present in EDID */
4297 modes += do_y420vdb_modes(connector,
4298 vdb420,
4299 dbl - 1);
4300 }
4301 }
4302 }
4303
4304 /*
4305 * We parse the HDMI VSDB after having added the cea modes as we will
4306 * be patching their flags when the sink supports stereo 3D.
4307 */
4308 if (hdmi)
4309 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4310 video_len);
4311
4312 return modes;
4313 }
4314
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)4315 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4316 {
4317 const struct drm_display_mode *cea_mode;
4318 int clock1, clock2, clock;
4319 u8 vic;
4320 const char *type;
4321
4322 /*
4323 * allow 5kHz clock difference either way to account for
4324 * the 10kHz clock resolution limit of detailed timings.
4325 */
4326 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4327 if (drm_valid_cea_vic(vic)) {
4328 type = "CEA";
4329 cea_mode = cea_mode_for_vic(vic);
4330 clock1 = cea_mode->clock;
4331 clock2 = cea_mode_alternate_clock(cea_mode);
4332 } else {
4333 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4334 if (drm_valid_hdmi_vic(vic)) {
4335 type = "HDMI";
4336 cea_mode = &edid_4k_modes[vic];
4337 clock1 = cea_mode->clock;
4338 clock2 = hdmi_mode_alternate_clock(cea_mode);
4339 } else {
4340 return;
4341 }
4342 }
4343
4344 /* pick whichever is closest */
4345 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4346 clock = clock1;
4347 else
4348 clock = clock2;
4349
4350 if (mode->clock == clock)
4351 return;
4352
4353 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4354 type, vic, mode->clock, clock);
4355 mode->clock = clock;
4356 }
4357
cea_db_is_hdmi_hdr_metadata_block(const u8 * db)4358 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4359 {
4360 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4361 return false;
4362
4363 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4364 return false;
4365
4366 if (cea_db_payload_len(db) < 3)
4367 return false;
4368
4369 return true;
4370 }
4371
eotf_supported(const u8 * edid_ext)4372 static uint8_t eotf_supported(const u8 *edid_ext)
4373 {
4374 return edid_ext[2] &
4375 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4376 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4377 BIT(HDMI_EOTF_SMPTE_ST2084) |
4378 BIT(HDMI_EOTF_BT_2100_HLG));
4379 }
4380
hdr_metadata_type(const u8 * edid_ext)4381 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4382 {
4383 return edid_ext[3] &
4384 BIT(HDMI_STATIC_METADATA_TYPE1);
4385 }
4386
4387 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)4388 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4389 {
4390 u16 len;
4391
4392 len = cea_db_payload_len(db);
4393
4394 connector->hdr_sink_metadata.hdmi_type1.eotf =
4395 eotf_supported(db);
4396 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4397 hdr_metadata_type(db);
4398
4399 if (len >= 4)
4400 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4401 if (len >= 5)
4402 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4403 if (len >= 6)
4404 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4405 }
4406
4407 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)4408 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4409 {
4410 u8 len = cea_db_payload_len(db);
4411
4412 if (len >= 6 && (db[6] & (1 << 7)))
4413 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4414 if (len >= 8) {
4415 connector->latency_present[0] = db[8] >> 7;
4416 connector->latency_present[1] = (db[8] >> 6) & 1;
4417 }
4418 if (len >= 9)
4419 connector->video_latency[0] = db[9];
4420 if (len >= 10)
4421 connector->audio_latency[0] = db[10];
4422 if (len >= 11)
4423 connector->video_latency[1] = db[11];
4424 if (len >= 12)
4425 connector->audio_latency[1] = db[12];
4426
4427 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4428 "video latency %d %d, "
4429 "audio latency %d %d\n",
4430 connector->latency_present[0],
4431 connector->latency_present[1],
4432 connector->video_latency[0],
4433 connector->video_latency[1],
4434 connector->audio_latency[0],
4435 connector->audio_latency[1]);
4436 }
4437
4438 static void
monitor_name(struct detailed_timing * t,void * data)4439 monitor_name(struct detailed_timing *t, void *data)
4440 {
4441 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4442 return;
4443
4444 *(u8 **)data = t->data.other_data.data.str.str;
4445 }
4446
get_monitor_name(struct edid * edid,char name[13])4447 static int get_monitor_name(struct edid *edid, char name[13])
4448 {
4449 char *edid_name = NULL;
4450 int mnl;
4451
4452 if (!edid || !name)
4453 return 0;
4454
4455 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4456 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4457 if (edid_name[mnl] == 0x0a)
4458 break;
4459
4460 name[mnl] = edid_name[mnl];
4461 }
4462
4463 return mnl;
4464 }
4465
4466 /**
4467 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4468 * @edid: monitor EDID information
4469 * @name: pointer to a character array to hold the name of the monitor
4470 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4471 *
4472 */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)4473 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4474 {
4475 int name_length;
4476 char buf[13];
4477
4478 if (bufsize <= 0)
4479 return;
4480
4481 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4482 memcpy(name, buf, name_length);
4483 name[name_length] = '\0';
4484 }
4485 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4486
clear_eld(struct drm_connector * connector)4487 static void clear_eld(struct drm_connector *connector)
4488 {
4489 memset(connector->eld, 0, sizeof(connector->eld));
4490
4491 connector->latency_present[0] = false;
4492 connector->latency_present[1] = false;
4493 connector->video_latency[0] = 0;
4494 connector->audio_latency[0] = 0;
4495 connector->video_latency[1] = 0;
4496 connector->audio_latency[1] = 0;
4497 }
4498
4499 /*
4500 * drm_edid_to_eld - build ELD from EDID
4501 * @connector: connector corresponding to the HDMI/DP sink
4502 * @edid: EDID to parse
4503 *
4504 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4505 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4506 */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)4507 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4508 {
4509 uint8_t *eld = connector->eld;
4510 u8 *cea;
4511 u8 *db;
4512 int total_sad_count = 0;
4513 int mnl;
4514 int dbl;
4515
4516 clear_eld(connector);
4517
4518 if (!edid)
4519 return;
4520
4521 cea = drm_find_cea_extension(edid);
4522 if (!cea) {
4523 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4524 return;
4525 }
4526
4527 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4528 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4529
4530 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4531 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4532
4533 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4534
4535 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4536 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4537 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4538 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4539
4540 if (cea_revision(cea) >= 3) {
4541 int i, start, end;
4542 int sad_count;
4543
4544 if (cea_db_offsets(cea, &start, &end)) {
4545 start = 0;
4546 end = 0;
4547 }
4548
4549 for_each_cea_db(cea, i, start, end) {
4550 db = &cea[i];
4551 dbl = cea_db_payload_len(db);
4552
4553 switch (cea_db_tag(db)) {
4554 case AUDIO_BLOCK:
4555 /* Audio Data Block, contains SADs */
4556 sad_count = min(dbl / 3, 15 - total_sad_count);
4557 if (sad_count >= 1)
4558 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4559 &db[1], sad_count * 3);
4560 total_sad_count += sad_count;
4561 break;
4562 case SPEAKER_BLOCK:
4563 /* Speaker Allocation Data Block */
4564 if (dbl >= 1)
4565 eld[DRM_ELD_SPEAKER] = db[1];
4566 break;
4567 case VENDOR_BLOCK:
4568 /* HDMI Vendor-Specific Data Block */
4569 if (cea_db_is_hdmi_vsdb(db))
4570 drm_parse_hdmi_vsdb_audio(connector, db);
4571 break;
4572 default:
4573 break;
4574 }
4575 }
4576 }
4577 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4578
4579 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4580 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4581 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4582 else
4583 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4584
4585 eld[DRM_ELD_BASELINE_ELD_LEN] =
4586 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4587
4588 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4589 drm_eld_size(eld), total_sad_count);
4590 }
4591
4592 /**
4593 * drm_edid_to_sad - extracts SADs from EDID
4594 * @edid: EDID to parse
4595 * @sads: pointer that will be set to the extracted SADs
4596 *
4597 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4598 *
4599 * Note: The returned pointer needs to be freed using kfree().
4600 *
4601 * Return: The number of found SADs or negative number on error.
4602 */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)4603 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4604 {
4605 int count = 0;
4606 int i, start, end, dbl;
4607 u8 *cea;
4608
4609 cea = drm_find_cea_extension(edid);
4610 if (!cea) {
4611 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4612 return 0;
4613 }
4614
4615 if (cea_revision(cea) < 3) {
4616 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4617 return 0;
4618 }
4619
4620 if (cea_db_offsets(cea, &start, &end)) {
4621 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4622 return -EPROTO;
4623 }
4624
4625 for_each_cea_db(cea, i, start, end) {
4626 u8 *db = &cea[i];
4627
4628 if (cea_db_tag(db) == AUDIO_BLOCK) {
4629 int j;
4630
4631 dbl = cea_db_payload_len(db);
4632
4633 count = dbl / 3; /* SAD is 3B */
4634 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4635 if (!*sads)
4636 return -ENOMEM;
4637 for (j = 0; j < count; j++) {
4638 u8 *sad = &db[1 + j * 3];
4639
4640 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4641 (*sads)[j].channels = sad[0] & 0x7;
4642 (*sads)[j].freq = sad[1] & 0x7F;
4643 (*sads)[j].byte2 = sad[2];
4644 }
4645 break;
4646 }
4647 }
4648
4649 return count;
4650 }
4651 EXPORT_SYMBOL(drm_edid_to_sad);
4652
4653 /**
4654 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4655 * @edid: EDID to parse
4656 * @sadb: pointer to the speaker block
4657 *
4658 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4659 *
4660 * Note: The returned pointer needs to be freed using kfree().
4661 *
4662 * Return: The number of found Speaker Allocation Blocks or negative number on
4663 * error.
4664 */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4665 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4666 {
4667 int count = 0;
4668 int i, start, end, dbl;
4669 const u8 *cea;
4670
4671 cea = drm_find_cea_extension(edid);
4672 if (!cea) {
4673 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4674 return 0;
4675 }
4676
4677 if (cea_revision(cea) < 3) {
4678 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4679 return 0;
4680 }
4681
4682 if (cea_db_offsets(cea, &start, &end)) {
4683 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4684 return -EPROTO;
4685 }
4686
4687 for_each_cea_db(cea, i, start, end) {
4688 const u8 *db = &cea[i];
4689
4690 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4691 dbl = cea_db_payload_len(db);
4692
4693 /* Speaker Allocation Data Block */
4694 if (dbl == 3) {
4695 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4696 if (!*sadb)
4697 return -ENOMEM;
4698 count = dbl;
4699 break;
4700 }
4701 }
4702 }
4703
4704 return count;
4705 }
4706 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4707
4708 /**
4709 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4710 * @connector: connector associated with the HDMI/DP sink
4711 * @mode: the display mode
4712 *
4713 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4714 * the sink doesn't support audio or video.
4715 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)4716 int drm_av_sync_delay(struct drm_connector *connector,
4717 const struct drm_display_mode *mode)
4718 {
4719 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4720 int a, v;
4721
4722 if (!connector->latency_present[0])
4723 return 0;
4724 if (!connector->latency_present[1])
4725 i = 0;
4726
4727 a = connector->audio_latency[i];
4728 v = connector->video_latency[i];
4729
4730 /*
4731 * HDMI/DP sink doesn't support audio or video?
4732 */
4733 if (a == 255 || v == 255)
4734 return 0;
4735
4736 /*
4737 * Convert raw EDID values to millisecond.
4738 * Treat unknown latency as 0ms.
4739 */
4740 if (a)
4741 a = min(2 * (a - 1), 500);
4742 if (v)
4743 v = min(2 * (v - 1), 500);
4744
4745 return max(v - a, 0);
4746 }
4747 EXPORT_SYMBOL(drm_av_sync_delay);
4748
4749 /**
4750 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4751 * @edid: monitor EDID information
4752 *
4753 * Parse the CEA extension according to CEA-861-B.
4754 *
4755 * Drivers that have added the modes parsed from EDID to drm_display_info
4756 * should use &drm_display_info.is_hdmi instead of calling this function.
4757 *
4758 * Return: True if the monitor is HDMI, false if not or unknown.
4759 */
drm_detect_hdmi_monitor(struct edid * edid)4760 bool drm_detect_hdmi_monitor(struct edid *edid)
4761 {
4762 u8 *edid_ext;
4763 int i;
4764 int start_offset, end_offset;
4765
4766 edid_ext = drm_find_cea_extension(edid);
4767 if (!edid_ext)
4768 return false;
4769
4770 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4771 return false;
4772
4773 /*
4774 * Because HDMI identifier is in Vendor Specific Block,
4775 * search it from all data blocks of CEA extension.
4776 */
4777 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4778 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4779 return true;
4780 }
4781
4782 return false;
4783 }
4784 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4785
4786 /**
4787 * drm_detect_monitor_audio - check monitor audio capability
4788 * @edid: EDID block to scan
4789 *
4790 * Monitor should have CEA extension block.
4791 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4792 * audio' only. If there is any audio extension block and supported
4793 * audio format, assume at least 'basic audio' support, even if 'basic
4794 * audio' is not defined in EDID.
4795 *
4796 * Return: True if the monitor supports audio, false otherwise.
4797 */
drm_detect_monitor_audio(struct edid * edid)4798 bool drm_detect_monitor_audio(struct edid *edid)
4799 {
4800 u8 *edid_ext;
4801 int i, j;
4802 bool has_audio = false;
4803 int start_offset, end_offset;
4804
4805 edid_ext = drm_find_cea_extension(edid);
4806 if (!edid_ext)
4807 goto end;
4808
4809 has_audio = (edid_ext[0] == CEA_EXT &&
4810 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4811
4812 if (has_audio) {
4813 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4814 goto end;
4815 }
4816
4817 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4818 goto end;
4819
4820 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4821 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4822 has_audio = true;
4823 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4824 DRM_DEBUG_KMS("CEA audio format %d\n",
4825 (edid_ext[i + j] >> 3) & 0xf);
4826 goto end;
4827 }
4828 }
4829 end:
4830 return has_audio;
4831 }
4832 EXPORT_SYMBOL(drm_detect_monitor_audio);
4833
4834
4835 /**
4836 * drm_default_rgb_quant_range - default RGB quantization range
4837 * @mode: display mode
4838 *
4839 * Determine the default RGB quantization range for the mode,
4840 * as specified in CEA-861.
4841 *
4842 * Return: The default RGB quantization range for the mode
4843 */
4844 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)4845 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4846 {
4847 /* All CEA modes other than VIC 1 use limited quantization range. */
4848 return drm_match_cea_mode(mode) > 1 ?
4849 HDMI_QUANTIZATION_RANGE_LIMITED :
4850 HDMI_QUANTIZATION_RANGE_FULL;
4851 }
4852 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4853
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)4854 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4855 {
4856 struct drm_display_info *info = &connector->display_info;
4857
4858 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4859
4860 if (db[2] & EDID_CEA_VCDB_QS)
4861 info->rgb_quant_range_selectable = true;
4862 }
4863
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)4864 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4865 const u8 *db)
4866 {
4867 u8 dc_mask;
4868 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4869
4870 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4871 hdmi->y420_dc_modes = dc_mask;
4872 }
4873
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)4874 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4875 const u8 *hf_vsdb)
4876 {
4877 struct drm_display_info *display = &connector->display_info;
4878 struct drm_hdmi_info *hdmi = &display->hdmi;
4879
4880 display->has_hdmi_infoframe = true;
4881
4882 if (hf_vsdb[6] & 0x80) {
4883 hdmi->scdc.supported = true;
4884 if (hf_vsdb[6] & 0x40)
4885 hdmi->scdc.read_request = true;
4886 }
4887
4888 /*
4889 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4890 * And as per the spec, three factors confirm this:
4891 * * Availability of a HF-VSDB block in EDID (check)
4892 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4893 * * SCDC support available (let's check)
4894 * Lets check it out.
4895 */
4896
4897 if (hf_vsdb[5]) {
4898 /* max clock is 5000 KHz times block value */
4899 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4900 struct drm_scdc *scdc = &hdmi->scdc;
4901
4902 if (max_tmds_clock > 340000) {
4903 display->max_tmds_clock = max_tmds_clock;
4904 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4905 display->max_tmds_clock);
4906 }
4907
4908 if (scdc->supported) {
4909 scdc->scrambling.supported = true;
4910
4911 /* Few sinks support scrambling for clocks < 340M */
4912 if ((hf_vsdb[6] & 0x8))
4913 scdc->scrambling.low_rates = true;
4914 }
4915 }
4916
4917 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4918 }
4919
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)4920 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4921 const u8 *hdmi)
4922 {
4923 struct drm_display_info *info = &connector->display_info;
4924 unsigned int dc_bpc = 0;
4925
4926 /* HDMI supports at least 8 bpc */
4927 info->bpc = 8;
4928
4929 if (cea_db_payload_len(hdmi) < 6)
4930 return;
4931
4932 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4933 dc_bpc = 10;
4934 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4935 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4936 connector->name);
4937 }
4938
4939 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4940 dc_bpc = 12;
4941 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4942 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4943 connector->name);
4944 }
4945
4946 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4947 dc_bpc = 16;
4948 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4949 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4950 connector->name);
4951 }
4952
4953 if (dc_bpc == 0) {
4954 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4955 connector->name);
4956 return;
4957 }
4958
4959 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4960 connector->name, dc_bpc);
4961 info->bpc = dc_bpc;
4962
4963 /* YCRCB444 is optional according to spec. */
4964 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4965 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4966 connector->name);
4967 }
4968
4969 /*
4970 * Spec says that if any deep color mode is supported at all,
4971 * then deep color 36 bit must be supported.
4972 */
4973 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4974 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4975 connector->name);
4976 }
4977 }
4978
4979 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)4980 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4981 {
4982 struct drm_display_info *info = &connector->display_info;
4983 u8 len = cea_db_payload_len(db);
4984
4985 info->is_hdmi = true;
4986
4987 if (len >= 6)
4988 info->dvi_dual = db[6] & 1;
4989 if (len >= 7)
4990 info->max_tmds_clock = db[7] * 5000;
4991
4992 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4993 "max TMDS clock %d kHz\n",
4994 info->dvi_dual,
4995 info->max_tmds_clock);
4996
4997 drm_parse_hdmi_deep_color_info(connector, db);
4998 }
4999
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)5000 static void drm_parse_cea_ext(struct drm_connector *connector,
5001 const struct edid *edid)
5002 {
5003 struct drm_display_info *info = &connector->display_info;
5004 const u8 *edid_ext;
5005 int i, start, end;
5006
5007 edid_ext = drm_find_cea_extension(edid);
5008 if (!edid_ext)
5009 return;
5010
5011 info->cea_rev = edid_ext[1];
5012
5013 /* The existence of a CEA block should imply RGB support */
5014 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5015 if (edid_ext[3] & EDID_CEA_YCRCB444)
5016 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5017 if (edid_ext[3] & EDID_CEA_YCRCB422)
5018 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5019
5020 if (cea_db_offsets(edid_ext, &start, &end))
5021 return;
5022
5023 for_each_cea_db(edid_ext, i, start, end) {
5024 const u8 *db = &edid_ext[i];
5025
5026 if (cea_db_is_hdmi_vsdb(db))
5027 drm_parse_hdmi_vsdb_video(connector, db);
5028 if (cea_db_is_hdmi_forum_vsdb(db))
5029 drm_parse_hdmi_forum_vsdb(connector, db);
5030 if (cea_db_is_y420cmdb(db))
5031 drm_parse_y420cmdb_bitmap(connector, db);
5032 if (cea_db_is_vcdb(db))
5033 drm_parse_vcdb(connector, db);
5034 if (cea_db_is_hdmi_hdr_metadata_block(db))
5035 drm_parse_hdr_metadata_block(connector, db);
5036 }
5037 }
5038
5039 static
get_monitor_range(struct detailed_timing * timing,void * info_monitor_range)5040 void get_monitor_range(struct detailed_timing *timing,
5041 void *info_monitor_range)
5042 {
5043 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5044 const struct detailed_non_pixel *data = &timing->data.other_data;
5045 const struct detailed_data_monitor_range *range = &data->data.range;
5046
5047 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5048 return;
5049
5050 /*
5051 * Check for flag range limits only. If flag == 1 then
5052 * no additional timing information provided.
5053 * Default GTF, GTF Secondary curve and CVT are not
5054 * supported
5055 */
5056 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5057 return;
5058
5059 monitor_range->min_vfreq = range->min_vfreq;
5060 monitor_range->max_vfreq = range->max_vfreq;
5061 }
5062
5063 static
drm_get_monitor_range(struct drm_connector * connector,const struct edid * edid)5064 void drm_get_monitor_range(struct drm_connector *connector,
5065 const struct edid *edid)
5066 {
5067 struct drm_display_info *info = &connector->display_info;
5068
5069 if (!version_greater(edid, 1, 1))
5070 return;
5071
5072 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5073 &info->monitor_range);
5074
5075 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5076 info->monitor_range.min_vfreq,
5077 info->monitor_range.max_vfreq);
5078 }
5079
5080 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5081 * all of the values which would have been set from EDID
5082 */
5083 void
drm_reset_display_info(struct drm_connector * connector)5084 drm_reset_display_info(struct drm_connector *connector)
5085 {
5086 struct drm_display_info *info = &connector->display_info;
5087
5088 info->width_mm = 0;
5089 info->height_mm = 0;
5090
5091 info->bpc = 0;
5092 info->color_formats = 0;
5093 info->cea_rev = 0;
5094 info->max_tmds_clock = 0;
5095 info->dvi_dual = false;
5096 info->is_hdmi = false;
5097 info->has_hdmi_infoframe = false;
5098 info->rgb_quant_range_selectable = false;
5099 memset(&info->hdmi, 0, sizeof(info->hdmi));
5100
5101 info->non_desktop = 0;
5102 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5103 }
5104
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)5105 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5106 {
5107 struct drm_display_info *info = &connector->display_info;
5108
5109 u32 quirks = edid_get_quirks(edid);
5110
5111 drm_reset_display_info(connector);
5112
5113 info->width_mm = edid->width_cm * 10;
5114 info->height_mm = edid->height_cm * 10;
5115
5116 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5117
5118 drm_get_monitor_range(connector, edid);
5119
5120 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5121
5122 if (edid->revision < 3)
5123 return quirks;
5124
5125 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5126 return quirks;
5127
5128 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5129 drm_parse_cea_ext(connector, edid);
5130
5131 /*
5132 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5133 *
5134 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5135 * tells us to assume 8 bpc color depth if the EDID doesn't have
5136 * extensions which tell otherwise.
5137 */
5138 if (info->bpc == 0 && edid->revision == 3 &&
5139 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5140 info->bpc = 8;
5141 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5142 connector->name, info->bpc);
5143 }
5144
5145 /* Only defined for 1.4 with digital displays */
5146 if (edid->revision < 4)
5147 return quirks;
5148
5149 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5150 case DRM_EDID_DIGITAL_DEPTH_6:
5151 info->bpc = 6;
5152 break;
5153 case DRM_EDID_DIGITAL_DEPTH_8:
5154 info->bpc = 8;
5155 break;
5156 case DRM_EDID_DIGITAL_DEPTH_10:
5157 info->bpc = 10;
5158 break;
5159 case DRM_EDID_DIGITAL_DEPTH_12:
5160 info->bpc = 12;
5161 break;
5162 case DRM_EDID_DIGITAL_DEPTH_14:
5163 info->bpc = 14;
5164 break;
5165 case DRM_EDID_DIGITAL_DEPTH_16:
5166 info->bpc = 16;
5167 break;
5168 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5169 default:
5170 info->bpc = 0;
5171 break;
5172 }
5173
5174 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5175 connector->name, info->bpc);
5176
5177 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5178 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5179 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5180 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5181 return quirks;
5182 }
5183
validate_displayid(u8 * displayid,int length,int idx)5184 static int validate_displayid(u8 *displayid, int length, int idx)
5185 {
5186 int i, dispid_length;
5187 u8 csum = 0;
5188 struct displayid_hdr *base;
5189
5190 base = (struct displayid_hdr *)&displayid[idx];
5191
5192 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5193 base->rev, base->bytes, base->prod_id, base->ext_count);
5194
5195 /* +1 for DispID checksum */
5196 dispid_length = sizeof(*base) + base->bytes + 1;
5197 if (dispid_length > length - idx)
5198 return -EINVAL;
5199
5200 for (i = 0; i < dispid_length; i++)
5201 csum += displayid[idx + i];
5202 if (csum) {
5203 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5204 return -EINVAL;
5205 }
5206
5207 return 0;
5208 }
5209
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings)5210 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5211 struct displayid_detailed_timings_1 *timings)
5212 {
5213 struct drm_display_mode *mode;
5214 unsigned pixel_clock = (timings->pixel_clock[0] |
5215 (timings->pixel_clock[1] << 8) |
5216 (timings->pixel_clock[2] << 16)) + 1;
5217 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5218 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5219 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5220 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5221 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5222 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5223 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5224 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5225 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5226 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5227
5228 mode = drm_mode_create(dev);
5229 if (!mode)
5230 return NULL;
5231
5232 mode->clock = pixel_clock * 10;
5233 mode->hdisplay = hactive;
5234 mode->hsync_start = mode->hdisplay + hsync;
5235 mode->hsync_end = mode->hsync_start + hsync_width;
5236 mode->htotal = mode->hdisplay + hblank;
5237
5238 mode->vdisplay = vactive;
5239 mode->vsync_start = mode->vdisplay + vsync;
5240 mode->vsync_end = mode->vsync_start + vsync_width;
5241 mode->vtotal = mode->vdisplay + vblank;
5242
5243 mode->flags = 0;
5244 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5245 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5246 mode->type = DRM_MODE_TYPE_DRIVER;
5247
5248 if (timings->flags & 0x80)
5249 mode->type |= DRM_MODE_TYPE_PREFERRED;
5250 drm_mode_set_name(mode);
5251
5252 return mode;
5253 }
5254
add_displayid_detailed_1_modes(struct drm_connector * connector,struct displayid_block * block)5255 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5256 struct displayid_block *block)
5257 {
5258 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5259 int i;
5260 int num_timings;
5261 struct drm_display_mode *newmode;
5262 int num_modes = 0;
5263 /* blocks must be multiple of 20 bytes length */
5264 if (block->num_bytes % 20)
5265 return 0;
5266
5267 num_timings = block->num_bytes / 20;
5268 for (i = 0; i < num_timings; i++) {
5269 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5270
5271 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5272 if (!newmode)
5273 continue;
5274
5275 drm_mode_probed_add(connector, newmode);
5276 num_modes++;
5277 }
5278 return num_modes;
5279 }
5280
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)5281 static int add_displayid_detailed_modes(struct drm_connector *connector,
5282 struct edid *edid)
5283 {
5284 u8 *displayid;
5285 int length, idx;
5286 struct displayid_block *block;
5287 int num_modes = 0;
5288 int ext_index = 0;
5289
5290 for (;;) {
5291 displayid = drm_find_displayid_extension(edid, &length, &idx,
5292 &ext_index);
5293 if (!displayid)
5294 break;
5295
5296 idx += sizeof(struct displayid_hdr);
5297 for_each_displayid_db(displayid, block, idx, length) {
5298 switch (block->tag) {
5299 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5300 num_modes += add_displayid_detailed_1_modes(connector, block);
5301 break;
5302 }
5303 }
5304 }
5305
5306 return num_modes;
5307 }
5308
5309 /**
5310 * drm_add_edid_modes - add modes from EDID data, if available
5311 * @connector: connector we're probing
5312 * @edid: EDID data
5313 *
5314 * Add the specified modes to the connector's mode list. Also fills out the
5315 * &drm_display_info structure and ELD in @connector with any information which
5316 * can be derived from the edid.
5317 *
5318 * Return: The number of modes added or 0 if we couldn't find any.
5319 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)5320 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5321 {
5322 int num_modes = 0;
5323 u32 quirks;
5324
5325 if (edid == NULL) {
5326 clear_eld(connector);
5327 return 0;
5328 }
5329 if (!drm_edid_is_valid(edid)) {
5330 clear_eld(connector);
5331 drm_warn(connector->dev, "%s: EDID invalid.\n",
5332 connector->name);
5333 return 0;
5334 }
5335
5336 drm_edid_to_eld(connector, edid);
5337
5338 /*
5339 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5340 * To avoid multiple parsing of same block, lets parse that map
5341 * from sink info, before parsing CEA modes.
5342 */
5343 quirks = drm_add_display_info(connector, edid);
5344
5345 /*
5346 * EDID spec says modes should be preferred in this order:
5347 * - preferred detailed mode
5348 * - other detailed modes from base block
5349 * - detailed modes from extension blocks
5350 * - CVT 3-byte code modes
5351 * - standard timing codes
5352 * - established timing codes
5353 * - modes inferred from GTF or CVT range information
5354 *
5355 * We get this pretty much right.
5356 *
5357 * XXX order for additional mode types in extension blocks?
5358 */
5359 num_modes += add_detailed_modes(connector, edid, quirks);
5360 num_modes += add_cvt_modes(connector, edid);
5361 num_modes += add_standard_modes(connector, edid);
5362 num_modes += add_established_modes(connector, edid);
5363 num_modes += add_cea_modes(connector, edid);
5364 num_modes += add_alternate_cea_modes(connector, edid);
5365 num_modes += add_displayid_detailed_modes(connector, edid);
5366 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5367 num_modes += add_inferred_modes(connector, edid);
5368
5369 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5370 edid_fixup_preferred(connector, quirks);
5371
5372 if (quirks & EDID_QUIRK_FORCE_6BPC)
5373 connector->display_info.bpc = 6;
5374
5375 if (quirks & EDID_QUIRK_FORCE_8BPC)
5376 connector->display_info.bpc = 8;
5377
5378 if (quirks & EDID_QUIRK_FORCE_10BPC)
5379 connector->display_info.bpc = 10;
5380
5381 if (quirks & EDID_QUIRK_FORCE_12BPC)
5382 connector->display_info.bpc = 12;
5383
5384 return num_modes;
5385 }
5386 EXPORT_SYMBOL(drm_add_edid_modes);
5387
5388 /**
5389 * drm_add_modes_noedid - add modes for the connectors without EDID
5390 * @connector: connector we're probing
5391 * @hdisplay: the horizontal display limit
5392 * @vdisplay: the vertical display limit
5393 *
5394 * Add the specified modes to the connector's mode list. Only when the
5395 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5396 *
5397 * Return: The number of modes added or 0 if we couldn't find any.
5398 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)5399 int drm_add_modes_noedid(struct drm_connector *connector,
5400 int hdisplay, int vdisplay)
5401 {
5402 int i, count, num_modes = 0;
5403 struct drm_display_mode *mode;
5404 struct drm_device *dev = connector->dev;
5405
5406 count = ARRAY_SIZE(drm_dmt_modes);
5407 if (hdisplay < 0)
5408 hdisplay = 0;
5409 if (vdisplay < 0)
5410 vdisplay = 0;
5411
5412 for (i = 0; i < count; i++) {
5413 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5414
5415 if (hdisplay && vdisplay) {
5416 /*
5417 * Only when two are valid, they will be used to check
5418 * whether the mode should be added to the mode list of
5419 * the connector.
5420 */
5421 if (ptr->hdisplay > hdisplay ||
5422 ptr->vdisplay > vdisplay)
5423 continue;
5424 }
5425 if (drm_mode_vrefresh(ptr) > 61)
5426 continue;
5427 mode = drm_mode_duplicate(dev, ptr);
5428 if (mode) {
5429 drm_mode_probed_add(connector, mode);
5430 num_modes++;
5431 }
5432 }
5433 return num_modes;
5434 }
5435 EXPORT_SYMBOL(drm_add_modes_noedid);
5436
5437 /**
5438 * drm_set_preferred_mode - Sets the preferred mode of a connector
5439 * @connector: connector whose mode list should be processed
5440 * @hpref: horizontal resolution of preferred mode
5441 * @vpref: vertical resolution of preferred mode
5442 *
5443 * Marks a mode as preferred if it matches the resolution specified by @hpref
5444 * and @vpref.
5445 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)5446 void drm_set_preferred_mode(struct drm_connector *connector,
5447 int hpref, int vpref)
5448 {
5449 struct drm_display_mode *mode;
5450
5451 list_for_each_entry(mode, &connector->probed_modes, head) {
5452 if (mode->hdisplay == hpref &&
5453 mode->vdisplay == vpref)
5454 mode->type |= DRM_MODE_TYPE_PREFERRED;
5455 }
5456 }
5457 EXPORT_SYMBOL(drm_set_preferred_mode);
5458
is_hdmi2_sink(const struct drm_connector * connector)5459 static bool is_hdmi2_sink(const struct drm_connector *connector)
5460 {
5461 /*
5462 * FIXME: sil-sii8620 doesn't have a connector around when
5463 * we need one, so we have to be prepared for a NULL connector.
5464 */
5465 if (!connector)
5466 return true;
5467
5468 return connector->display_info.hdmi.scdc.supported ||
5469 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5470 }
5471
is_eotf_supported(u8 output_eotf,u8 sink_eotf)5472 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5473 {
5474 return sink_eotf & BIT(output_eotf);
5475 }
5476
5477 /**
5478 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5479 * HDR metadata from userspace
5480 * @frame: HDMI DRM infoframe
5481 * @conn_state: Connector state containing HDR metadata
5482 *
5483 * Return: 0 on success or a negative error code on failure.
5484 */
5485 int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe * frame,const struct drm_connector_state * conn_state)5486 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5487 const struct drm_connector_state *conn_state)
5488 {
5489 struct drm_connector *connector;
5490 struct hdr_output_metadata *hdr_metadata;
5491 int err;
5492
5493 if (!frame || !conn_state)
5494 return -EINVAL;
5495
5496 connector = conn_state->connector;
5497
5498 if (!conn_state->hdr_output_metadata)
5499 return -EINVAL;
5500
5501 hdr_metadata = conn_state->hdr_output_metadata->data;
5502
5503 if (!hdr_metadata || !connector)
5504 return -EINVAL;
5505
5506 /* Sink EOTF is Bit map while infoframe is absolute values */
5507 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5508 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5509 DRM_DEBUG_KMS("EOTF Not Supported\n");
5510 return -EINVAL;
5511 }
5512
5513 err = hdmi_drm_infoframe_init(frame);
5514 if (err < 0)
5515 return err;
5516
5517 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5518 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5519
5520 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5521 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5522 BUILD_BUG_ON(sizeof(frame->white_point) !=
5523 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5524
5525 memcpy(&frame->display_primaries,
5526 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5527 sizeof(frame->display_primaries));
5528
5529 memcpy(&frame->white_point,
5530 &hdr_metadata->hdmi_metadata_type1.white_point,
5531 sizeof(frame->white_point));
5532
5533 frame->max_display_mastering_luminance =
5534 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5535 frame->min_display_mastering_luminance =
5536 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5537 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5538 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5539
5540 return 0;
5541 }
5542 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5543
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5544 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5545 const struct drm_display_mode *mode)
5546 {
5547 bool has_hdmi_infoframe = connector ?
5548 connector->display_info.has_hdmi_infoframe : false;
5549
5550 if (!has_hdmi_infoframe)
5551 return 0;
5552
5553 /* No HDMI VIC when signalling 3D video format */
5554 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5555 return 0;
5556
5557 return drm_match_hdmi_mode(mode);
5558 }
5559
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)5560 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5561 const struct drm_display_mode *mode)
5562 {
5563 u8 vic;
5564
5565 /*
5566 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5567 * we should send its VIC in vendor infoframes, else send the
5568 * VIC in AVI infoframes. Lets check if this mode is present in
5569 * HDMI 1.4b 4K modes
5570 */
5571 if (drm_mode_hdmi_vic(connector, mode))
5572 return 0;
5573
5574 vic = drm_match_cea_mode(mode);
5575
5576 /*
5577 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5578 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5579 * have to make sure we dont break HDMI 1.4 sinks.
5580 */
5581 if (!is_hdmi2_sink(connector) && vic > 64)
5582 return 0;
5583
5584 return vic;
5585 }
5586
5587 /**
5588 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5589 * data from a DRM display mode
5590 * @frame: HDMI AVI infoframe
5591 * @connector: the connector
5592 * @mode: DRM display mode
5593 *
5594 * Return: 0 on success or a negative error code on failure.
5595 */
5596 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5597 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5598 const struct drm_connector *connector,
5599 const struct drm_display_mode *mode)
5600 {
5601 enum hdmi_picture_aspect picture_aspect;
5602 u8 vic, hdmi_vic;
5603
5604 if (!frame || !mode)
5605 return -EINVAL;
5606
5607 hdmi_avi_infoframe_init(frame);
5608
5609 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5610 frame->pixel_repeat = 1;
5611
5612 vic = drm_mode_cea_vic(connector, mode);
5613 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5614
5615 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5616
5617 /*
5618 * As some drivers don't support atomic, we can't use connector state.
5619 * So just initialize the frame with default values, just the same way
5620 * as it's done with other properties here.
5621 */
5622 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5623 frame->itc = 0;
5624
5625 /*
5626 * Populate picture aspect ratio from either
5627 * user input (if specified) or from the CEA/HDMI mode lists.
5628 */
5629 picture_aspect = mode->picture_aspect_ratio;
5630 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5631 if (vic)
5632 picture_aspect = drm_get_cea_aspect_ratio(vic);
5633 else if (hdmi_vic)
5634 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5635 }
5636
5637 /*
5638 * The infoframe can't convey anything but none, 4:3
5639 * and 16:9, so if the user has asked for anything else
5640 * we can only satisfy it by specifying the right VIC.
5641 */
5642 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5643 if (vic) {
5644 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5645 return -EINVAL;
5646 } else if (hdmi_vic) {
5647 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5648 return -EINVAL;
5649 } else {
5650 return -EINVAL;
5651 }
5652
5653 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5654 }
5655
5656 frame->video_code = vic;
5657 frame->picture_aspect = picture_aspect;
5658 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5659 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5660
5661 return 0;
5662 }
5663 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5664
5665 /* HDMI Colorspace Spec Definitions */
5666 #define FULL_COLORIMETRY_MASK 0x1FF
5667 #define NORMAL_COLORIMETRY_MASK 0x3
5668 #define EXTENDED_COLORIMETRY_MASK 0x7
5669 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5670
5671 #define C(x) ((x) << 0)
5672 #define EC(x) ((x) << 2)
5673 #define ACE(x) ((x) << 5)
5674
5675 #define HDMI_COLORIMETRY_NO_DATA 0x0
5676 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5677 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5678 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5679 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5680 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5681 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5682 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5683 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5684 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5685 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5686 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5687 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5688
5689 static const u32 hdmi_colorimetry_val[] = {
5690 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5691 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5692 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5693 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5694 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5695 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5696 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5697 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5698 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5699 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5700 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5701 };
5702
5703 #undef C
5704 #undef EC
5705 #undef ACE
5706
5707 /**
5708 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5709 * colorspace information
5710 * @frame: HDMI AVI infoframe
5711 * @conn_state: connector state
5712 */
5713 void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5714 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5715 const struct drm_connector_state *conn_state)
5716 {
5717 u32 colorimetry_val;
5718 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5719
5720 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5721 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5722 else
5723 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5724
5725 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5726 /*
5727 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5728 * structure and extend it in drivers/video/hdmi
5729 */
5730 frame->extended_colorimetry = (colorimetry_val >> 2) &
5731 EXTENDED_COLORIMETRY_MASK;
5732 }
5733 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5734
5735 /**
5736 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5737 * quantization range information
5738 * @frame: HDMI AVI infoframe
5739 * @connector: the connector
5740 * @mode: DRM display mode
5741 * @rgb_quant_range: RGB quantization range (Q)
5742 */
5743 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)5744 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5745 const struct drm_connector *connector,
5746 const struct drm_display_mode *mode,
5747 enum hdmi_quantization_range rgb_quant_range)
5748 {
5749 const struct drm_display_info *info = &connector->display_info;
5750
5751 /*
5752 * CEA-861:
5753 * "A Source shall not send a non-zero Q value that does not correspond
5754 * to the default RGB Quantization Range for the transmitted Picture
5755 * unless the Sink indicates support for the Q bit in a Video
5756 * Capabilities Data Block."
5757 *
5758 * HDMI 2.0 recommends sending non-zero Q when it does match the
5759 * default RGB quantization range for the mode, even when QS=0.
5760 */
5761 if (info->rgb_quant_range_selectable ||
5762 rgb_quant_range == drm_default_rgb_quant_range(mode))
5763 frame->quantization_range = rgb_quant_range;
5764 else
5765 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5766
5767 /*
5768 * CEA-861-F:
5769 * "When transmitting any RGB colorimetry, the Source should set the
5770 * YQ-field to match the RGB Quantization Range being transmitted
5771 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5772 * set YQ=1) and the Sink shall ignore the YQ-field."
5773 *
5774 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5775 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5776 * good way to tell which version of CEA-861 the sink supports, so
5777 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5778 * on on CEA-861-F.
5779 */
5780 if (!is_hdmi2_sink(connector) ||
5781 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5782 frame->ycc_quantization_range =
5783 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5784 else
5785 frame->ycc_quantization_range =
5786 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5787 }
5788 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5789
5790 /**
5791 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5792 * bar information
5793 * @frame: HDMI AVI infoframe
5794 * @conn_state: connector state
5795 */
5796 void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5797 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5798 const struct drm_connector_state *conn_state)
5799 {
5800 frame->right_bar = conn_state->tv.margins.right;
5801 frame->left_bar = conn_state->tv.margins.left;
5802 frame->top_bar = conn_state->tv.margins.top;
5803 frame->bottom_bar = conn_state->tv.margins.bottom;
5804 }
5805 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5806
5807 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)5808 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5809 {
5810 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5811
5812 switch (layout) {
5813 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5814 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5815 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5816 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5817 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5818 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5819 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5820 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5821 case DRM_MODE_FLAG_3D_L_DEPTH:
5822 return HDMI_3D_STRUCTURE_L_DEPTH;
5823 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5824 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5825 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5826 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5827 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5828 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5829 default:
5830 return HDMI_3D_STRUCTURE_INVALID;
5831 }
5832 }
5833
5834 /**
5835 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5836 * data from a DRM display mode
5837 * @frame: HDMI vendor infoframe
5838 * @connector: the connector
5839 * @mode: DRM display mode
5840 *
5841 * Note that there's is a need to send HDMI vendor infoframes only when using a
5842 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5843 * function will return -EINVAL, error that can be safely ignored.
5844 *
5845 * Return: 0 on success or a negative error code on failure.
5846 */
5847 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)5848 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5849 const struct drm_connector *connector,
5850 const struct drm_display_mode *mode)
5851 {
5852 /*
5853 * FIXME: sil-sii8620 doesn't have a connector around when
5854 * we need one, so we have to be prepared for a NULL connector.
5855 */
5856 bool has_hdmi_infoframe = connector ?
5857 connector->display_info.has_hdmi_infoframe : false;
5858 int err;
5859
5860 if (!frame || !mode)
5861 return -EINVAL;
5862
5863 if (!has_hdmi_infoframe)
5864 return -EINVAL;
5865
5866 err = hdmi_vendor_infoframe_init(frame);
5867 if (err < 0)
5868 return err;
5869
5870 /*
5871 * Even if it's not absolutely necessary to send the infoframe
5872 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5873 * know that the sink can handle it. This is based on a
5874 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5875 * have trouble realizing that they shuld switch from 3D to 2D
5876 * mode if the source simply stops sending the infoframe when
5877 * it wants to switch from 3D to 2D.
5878 */
5879 frame->vic = drm_mode_hdmi_vic(connector, mode);
5880 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5881
5882 return 0;
5883 }
5884 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5885
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)5886 static void drm_parse_tiled_block(struct drm_connector *connector,
5887 const struct displayid_block *block)
5888 {
5889 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5890 u16 w, h;
5891 u8 tile_v_loc, tile_h_loc;
5892 u8 num_v_tile, num_h_tile;
5893 struct drm_tile_group *tg;
5894
5895 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5896 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5897
5898 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5899 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5900 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5901 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5902
5903 connector->has_tile = true;
5904 if (tile->tile_cap & 0x80)
5905 connector->tile_is_single_monitor = true;
5906
5907 connector->num_h_tile = num_h_tile + 1;
5908 connector->num_v_tile = num_v_tile + 1;
5909 connector->tile_h_loc = tile_h_loc;
5910 connector->tile_v_loc = tile_v_loc;
5911 connector->tile_h_size = w + 1;
5912 connector->tile_v_size = h + 1;
5913
5914 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5915 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5916 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5917 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5918 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5919
5920 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5921 if (!tg)
5922 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5923 if (!tg)
5924 return;
5925
5926 if (connector->tile_group != tg) {
5927 /* if we haven't got a pointer,
5928 take the reference, drop ref to old tile group */
5929 if (connector->tile_group)
5930 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5931 connector->tile_group = tg;
5932 } else {
5933 /* if same tile group, then release the ref we just took. */
5934 drm_mode_put_tile_group(connector->dev, tg);
5935 }
5936 }
5937
drm_displayid_parse_tiled(struct drm_connector * connector,const u8 * displayid,int length,int idx)5938 static void drm_displayid_parse_tiled(struct drm_connector *connector,
5939 const u8 *displayid, int length, int idx)
5940 {
5941 const struct displayid_block *block;
5942
5943 idx += sizeof(struct displayid_hdr);
5944 for_each_displayid_db(displayid, block, idx, length) {
5945 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5946 block->tag, block->rev, block->num_bytes);
5947
5948 switch (block->tag) {
5949 case DATA_BLOCK_TILED_DISPLAY:
5950 drm_parse_tiled_block(connector, block);
5951 break;
5952 default:
5953 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5954 break;
5955 }
5956 }
5957 }
5958
drm_update_tile_info(struct drm_connector * connector,const struct edid * edid)5959 void drm_update_tile_info(struct drm_connector *connector,
5960 const struct edid *edid)
5961 {
5962 const void *displayid = NULL;
5963 int ext_index = 0;
5964 int length, idx;
5965
5966 connector->has_tile = false;
5967 for (;;) {
5968 displayid = drm_find_displayid_extension(edid, &length, &idx,
5969 &ext_index);
5970 if (!displayid)
5971 break;
5972
5973 drm_displayid_parse_tiled(connector, displayid, length, idx);
5974 }
5975
5976 if (!connector->has_tile && connector->tile_group) {
5977 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5978 connector->tile_group = NULL;
5979 }
5980 }
5981