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1 /* -*- mesa-c++  -*-
2  *
3  * Copyright (c) 2022 Collabora LTD
4  *
5  * Author: Gert Wollny <gert.wollny@collabora.com>
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * on the rights to use, copy, modify, merge, publish, distribute, sub
11  * license, and/or sell copies of the Software, and to permit persons to whom
12  * the Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the next
15  * paragraph) shall be included in all copies or substantial portions of the
16  * Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 
27 #include "sfn_shader_cs.h"
28 #include "sfn_instr_fetch.h"
29 
30 
31 namespace r600 {
32 
ComputeShader(UNUSED const r600_shader_key & key)33 ComputeShader::ComputeShader(UNUSED const r600_shader_key& key):
34    Shader("CS")
35 {
36 
37 }
38 
do_scan_instruction(UNUSED nir_instr * instr)39 bool ComputeShader::do_scan_instruction(UNUSED nir_instr *instr)
40 {
41    return false;
42 }
43 
do_allocate_reserved_registers()44 int ComputeShader::do_allocate_reserved_registers()
45 {
46    auto& vf = value_factory();
47 
48    const int thread_id_sel = 0;
49    const int wg_id_sel = 1;
50 
51    for (int i = 0; i < 3; ++i) {
52       m_local_invocation_id[i] = vf.allocate_pinned_register(thread_id_sel, i);
53       m_local_invocation_id[i]->pin_live_range(true);
54 
55       m_workgroup_id[i] = vf.allocate_pinned_register(wg_id_sel, i);
56       m_workgroup_id[i]->pin_live_range(true);
57    }
58    return 2;
59 }
60 
process_stage_intrinsic(nir_intrinsic_instr * instr)61 bool ComputeShader::process_stage_intrinsic(nir_intrinsic_instr *instr)
62 {
63    switch (instr->intrinsic) {
64    case nir_intrinsic_load_local_invocation_id:
65       return emit_load_3vec(instr, m_local_invocation_id);
66    case nir_intrinsic_load_workgroup_id:
67       return emit_load_3vec(instr, m_workgroup_id);
68    case nir_intrinsic_load_num_workgroups:
69       return emit_load_num_workgroups(instr);
70    default:
71       return false;
72    }
73 }
74 
do_get_shader_info(r600_shader * sh_info)75 void ComputeShader::do_get_shader_info(r600_shader *sh_info)
76 {
77    sh_info->processor_type = PIPE_SHADER_COMPUTE;
78 }
79 
read_prop(UNUSED std::istream & is)80 bool ComputeShader::read_prop(UNUSED std::istream& is)
81 {
82    return true;
83 }
84 
do_print_properties(UNUSED std::ostream & os) const85 void ComputeShader::do_print_properties(UNUSED std::ostream& os) const
86 {
87 
88 }
89 
emit_load_num_workgroups(nir_intrinsic_instr * instr)90 bool ComputeShader::emit_load_num_workgroups(nir_intrinsic_instr* instr)
91 {
92    auto zero = value_factory().temp_register();
93 
94    emit_instruction(new AluInstr(op1_mov, zero, value_factory().inline_const(ALU_SRC_0, 0),
95                                  AluInstr::last_write));
96    auto dest = value_factory().dest_vec4(instr->dest, pin_group);
97 
98    auto ir = new LoadFromBuffer(dest, {0,1,2,7}, zero, 16,
99                                 R600_BUFFER_INFO_CONST_BUFFER,
100                                 nullptr, fmt_32_32_32_32);
101 
102    ir->set_fetch_flag(LoadFromBuffer::srf_mode);
103    ir->reset_fetch_flag(LoadFromBuffer::format_comp_signed);
104    ir->set_num_format(vtx_nf_int);
105    emit_instruction(ir);
106    return true;
107 
108 }
109 
emit_load_3vec(nir_intrinsic_instr * instr,const std::array<PRegister,3> & src)110 bool ComputeShader::emit_load_3vec(nir_intrinsic_instr* instr, const std::array<PRegister,3>& src)
111 {
112    auto& vf = value_factory();
113 
114    for (int i = 0; i < 3; ++i) {
115       auto dest = vf.dest(instr->dest, i, pin_none);
116       emit_instruction(new AluInstr(op1_mov, dest, src[i], i == 2 ? AluInstr::last_write : AluInstr::write));
117    }
118    return true;
119 }
120 
121 }
122