1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2020 NXP
4 */
5
6 #ifndef __DPAA2_ETH_H
7 #define __DPAA2_ETH_H
8
9 #include <linux/dcbnl.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/fsl/mc.h>
13 #include <linux/net_tstamp.h>
14 #include <net/devlink.h>
15
16 #include <soc/fsl/dpaa2-io.h>
17 #include <soc/fsl/dpaa2-fd.h>
18 #include "dpni.h"
19 #include "dpni-cmd.h"
20
21 #include "dpaa2-eth-trace.h"
22 #include "dpaa2-eth-debugfs.h"
23 #include "dpaa2-mac.h"
24
25 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
26
27 #define DPAA2_ETH_STORE_SIZE 16
28
29 /* Maximum number of scatter-gather entries in an ingress frame,
30 * considering the maximum receive frame size is 64K
31 */
32 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
33
34 /* Maximum acceptable MTU value. It is in direct relation with the hardware
35 * enforced Max Frame Length (currently 10k).
36 */
37 #define DPAA2_ETH_MFL (10 * 1024)
38 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
39 /* Convert L3 MTU to L2 MFL */
40 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
41
42 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large
43 * enough number of jumbo frames in the Rx queues (length of the current
44 * frame is not taken into account when making the taildrop decision)
45 */
46 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
47
48 /* Maximum burst size value for Tx shaping */
49 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
50
51 /* Maximum number of Tx confirmation frames to be processed
52 * in a single NAPI call
53 */
54 #define DPAA2_ETH_TXCONF_PER_NAPI 256
55
56 /* Buffer qouta per channel. We want to keep in check number of ingress frames
57 * in flight: for small sized frames, congestion group taildrop may kick in
58 * first; for large sizes, Rx FQ taildrop threshold will ensure only a
59 * reasonable number of frames will be pending at any given time.
60 * Ingress frame drop due to buffer pool depletion should be a corner case only
61 */
62 #define DPAA2_ETH_NUM_BUFS 1280
63 #define DPAA2_ETH_REFILL_THRESH \
64 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
65
66 /* Congestion group taildrop threshold: number of frames allowed to accumulate
67 * at any moment in a group of Rx queues belonging to the same traffic class.
68 * Choose value such that we don't risk depleting the buffer pool before the
69 * taildrop kicks in
70 */
71 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
72 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
73
74 /* Congestion group notification threshold: when this many frames accumulate
75 * on the Rx queues belonging to the same TC, the MAC is instructed to send
76 * PFC frames for that TC.
77 * When number of pending frames drops below exit threshold transmission of
78 * PFC frames is stopped.
79 */
80 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
81 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
82 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \
83 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
84
85 /* Maximum number of buffers that can be acquired/released through a single
86 * QBMan command
87 */
88 #define DPAA2_ETH_BUFS_PER_CMD 7
89
90 /* Hardware requires alignment for ingress/egress buffer addresses */
91 #define DPAA2_ETH_TX_BUF_ALIGN 64
92
93 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
94 #define DPAA2_ETH_RX_BUF_TAILROOM \
95 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
96 #define DPAA2_ETH_RX_BUF_SIZE \
97 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
98
99 /* Hardware annotation area in RX/TX buffers */
100 #define DPAA2_ETH_RX_HWA_SIZE 64
101 #define DPAA2_ETH_TX_HWA_SIZE 128
102
103 /* PTP nominal frequency 1GHz */
104 #define DPAA2_PTP_CLK_PERIOD_NS 1
105
106 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
107 * to 256B. For newer revisions, the requirement is only for 64B alignment
108 */
109 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
110 #define DPAA2_ETH_RX_BUF_ALIGN 64
111
112 /* We are accommodating a skb backpointer and some S/G info
113 * in the frame's software annotation. The hardware
114 * options are either 0 or 64, so we choose the latter.
115 */
116 #define DPAA2_ETH_SWA_SIZE 64
117
118 /* We store different information in the software annotation area of a Tx frame
119 * based on what type of frame it is
120 */
121 enum dpaa2_eth_swa_type {
122 DPAA2_ETH_SWA_SINGLE,
123 DPAA2_ETH_SWA_SG,
124 DPAA2_ETH_SWA_XDP,
125 };
126
127 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
128 struct dpaa2_eth_swa {
129 enum dpaa2_eth_swa_type type;
130 union {
131 struct {
132 struct sk_buff *skb;
133 int sgt_size;
134 } single;
135 struct {
136 struct sk_buff *skb;
137 struct scatterlist *scl;
138 int num_sg;
139 int sgt_size;
140 } sg;
141 struct {
142 int dma_size;
143 struct xdp_frame *xdpf;
144 } xdp;
145 };
146 };
147
148 /* Annotation valid bits in FD FRC */
149 #define DPAA2_FD_FRC_FASV 0x8000
150 #define DPAA2_FD_FRC_FAEADV 0x4000
151 #define DPAA2_FD_FRC_FAPRV 0x2000
152 #define DPAA2_FD_FRC_FAIADV 0x1000
153 #define DPAA2_FD_FRC_FASWOV 0x0800
154 #define DPAA2_FD_FRC_FAICFDV 0x0400
155
156 /* Error bits in FD CTRL */
157 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
158 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
159 FD_CTRL_SBE | \
160 FD_CTRL_FSE | \
161 FD_CTRL_FAERR)
162
163 /* Annotation bits in FD CTRL */
164 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
165
166 /* Frame annotation status */
167 struct dpaa2_fas {
168 u8 reserved;
169 u8 ppid;
170 __le16 ifpid;
171 __le32 status;
172 };
173
174 /* Frame annotation status word is located in the first 8 bytes
175 * of the buffer's hardware annoatation area
176 */
177 #define DPAA2_FAS_OFFSET 0
178 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
179
180 /* Timestamp is located in the next 8 bytes of the buffer's
181 * hardware annotation area
182 */
183 #define DPAA2_TS_OFFSET 0x8
184
185 /* Frame annotation parse results */
186 struct dpaa2_fapr {
187 /* 64-bit word 1 */
188 __le32 faf_lo;
189 __le16 faf_ext;
190 __le16 nxt_hdr;
191 /* 64-bit word 2 */
192 __le64 faf_hi;
193 /* 64-bit word 3 */
194 u8 last_ethertype_offset;
195 u8 vlan_tci_offset_n;
196 u8 vlan_tci_offset_1;
197 u8 llc_snap_offset;
198 u8 eth_offset;
199 u8 ip1_pid_offset;
200 u8 shim_offset_2;
201 u8 shim_offset_1;
202 /* 64-bit word 4 */
203 u8 l5_offset;
204 u8 l4_offset;
205 u8 gre_offset;
206 u8 l3_offset_n;
207 u8 l3_offset_1;
208 u8 mpls_offset_n;
209 u8 mpls_offset_1;
210 u8 pppoe_offset;
211 /* 64-bit word 5 */
212 __le16 running_sum;
213 __le16 gross_running_sum;
214 u8 ipv6_frag_offset;
215 u8 nxt_hdr_offset;
216 u8 routing_hdr_offset_2;
217 u8 routing_hdr_offset_1;
218 /* 64-bit word 6 */
219 u8 reserved[5]; /* Soft-parsing context */
220 u8 ip_proto_offset_n;
221 u8 nxt_hdr_frag_offset;
222 u8 parse_error_code;
223 };
224
225 #define DPAA2_FAPR_OFFSET 0x10
226 #define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
227
228 /* Frame annotation egress action descriptor */
229 #define DPAA2_FAEAD_OFFSET 0x58
230
231 struct dpaa2_faead {
232 __le32 conf_fqid;
233 __le32 ctrl;
234 };
235
236 #define DPAA2_FAEAD_A2V 0x20000000
237 #define DPAA2_FAEAD_A4V 0x08000000
238 #define DPAA2_FAEAD_UPDV 0x00001000
239 #define DPAA2_FAEAD_EBDDV 0x00002000
240 #define DPAA2_FAEAD_UPD 0x00000010
241
242 struct ptp_tstamp {
243 u16 sec_msb;
244 u32 sec_lsb;
245 u32 nsec;
246 };
247
ns_to_ptp_tstamp(struct ptp_tstamp * tstamp,u64 ns)248 static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
249 {
250 u64 sec, nsec;
251
252 sec = ns;
253 nsec = do_div(sec, 1000000000);
254
255 tstamp->sec_lsb = sec & 0xFFFFFFFF;
256 tstamp->sec_msb = (sec >> 32) & 0xFFFF;
257 tstamp->nsec = nsec;
258 }
259
260 /* Accessors for the hardware annotation fields that we use */
dpaa2_get_hwa(void * buf_addr,bool swa)261 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
262 {
263 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
264 }
265
dpaa2_get_fas(void * buf_addr,bool swa)266 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
267 {
268 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
269 }
270
dpaa2_get_ts(void * buf_addr,bool swa)271 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
272 {
273 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
274 }
275
dpaa2_get_fapr(void * buf_addr,bool swa)276 static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
277 {
278 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
279 }
280
dpaa2_get_faead(void * buf_addr,bool swa)281 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
282 {
283 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
284 }
285
286 /* Error and status bits in the frame annotation status word */
287 /* Debug frame, otherwise supposed to be discarded */
288 #define DPAA2_FAS_DISC 0x80000000
289 /* MACSEC frame */
290 #define DPAA2_FAS_MS 0x40000000
291 #define DPAA2_FAS_PTP 0x08000000
292 /* Ethernet multicast frame */
293 #define DPAA2_FAS_MC 0x04000000
294 /* Ethernet broadcast frame */
295 #define DPAA2_FAS_BC 0x02000000
296 #define DPAA2_FAS_KSE 0x00040000
297 #define DPAA2_FAS_EOFHE 0x00020000
298 #define DPAA2_FAS_MNLE 0x00010000
299 #define DPAA2_FAS_TIDE 0x00008000
300 #define DPAA2_FAS_PIEE 0x00004000
301 /* Frame length error */
302 #define DPAA2_FAS_FLE 0x00002000
303 /* Frame physical error */
304 #define DPAA2_FAS_FPE 0x00001000
305 #define DPAA2_FAS_PTE 0x00000080
306 #define DPAA2_FAS_ISP 0x00000040
307 #define DPAA2_FAS_PHE 0x00000020
308 #define DPAA2_FAS_BLE 0x00000010
309 /* L3 csum validation performed */
310 #define DPAA2_FAS_L3CV 0x00000008
311 /* L3 csum error */
312 #define DPAA2_FAS_L3CE 0x00000004
313 /* L4 csum validation performed */
314 #define DPAA2_FAS_L4CV 0x00000002
315 /* L4 csum error */
316 #define DPAA2_FAS_L4CE 0x00000001
317 /* Possible errors on the ingress path */
318 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
319 DPAA2_FAS_EOFHE | \
320 DPAA2_FAS_MNLE | \
321 DPAA2_FAS_TIDE | \
322 DPAA2_FAS_PIEE | \
323 DPAA2_FAS_FLE | \
324 DPAA2_FAS_FPE | \
325 DPAA2_FAS_PTE | \
326 DPAA2_FAS_ISP | \
327 DPAA2_FAS_PHE | \
328 DPAA2_FAS_BLE | \
329 DPAA2_FAS_L3CE | \
330 DPAA2_FAS_L4CE)
331
332 /* Time in milliseconds between link state updates */
333 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
334
335 /* Number of times to retry a frame enqueue before giving up.
336 * Value determined empirically, in order to minimize the number
337 * of frames dropped on Tx
338 */
339 #define DPAA2_ETH_ENQUEUE_RETRIES 10
340
341 /* Number of times to retry DPIO portal operations while waiting
342 * for portal to finish executing current command and become
343 * available. We want to avoid being stuck in a while loop in case
344 * hardware becomes unresponsive, but not give up too easily if
345 * the portal really is busy for valid reasons
346 */
347 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000
348
349 /* Driver statistics, other than those in struct rtnl_link_stats64.
350 * These are usually collected per-CPU and aggregated by ethtool.
351 */
352 struct dpaa2_eth_drv_stats {
353 __u64 tx_conf_frames;
354 __u64 tx_conf_bytes;
355 __u64 tx_sg_frames;
356 __u64 tx_sg_bytes;
357 __u64 rx_sg_frames;
358 __u64 rx_sg_bytes;
359 /* Linear skbs sent as a S/G FD due to insufficient headroom */
360 __u64 tx_converted_sg_frames;
361 __u64 tx_converted_sg_bytes;
362 /* Enqueues retried due to portal busy */
363 __u64 tx_portal_busy;
364 };
365
366 /* Per-FQ statistics */
367 struct dpaa2_eth_fq_stats {
368 /* Number of frames received on this queue */
369 __u64 frames;
370 };
371
372 /* Per-channel statistics */
373 struct dpaa2_eth_ch_stats {
374 /* Volatile dequeues retried due to portal busy */
375 __u64 dequeue_portal_busy;
376 /* Pull errors */
377 __u64 pull_err;
378 /* Number of CDANs; useful to estimate avg NAPI len */
379 __u64 cdan;
380 /* XDP counters */
381 __u64 xdp_drop;
382 __u64 xdp_tx;
383 __u64 xdp_tx_err;
384 __u64 xdp_redirect;
385 /* Must be last, does not show up in ethtool stats */
386 __u64 frames;
387 };
388
389 /* Maximum number of queues associated with a DPNI */
390 #define DPAA2_ETH_MAX_TCS 8
391 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
392 #define DPAA2_ETH_MAX_RX_QUEUES \
393 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
394 #define DPAA2_ETH_MAX_TX_QUEUES 16
395 #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
396 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
397 DPAA2_ETH_MAX_TX_QUEUES + \
398 DPAA2_ETH_MAX_RX_ERR_QUEUES)
399 #define DPAA2_ETH_MAX_NETDEV_QUEUES \
400 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
401
402 #define DPAA2_ETH_MAX_DPCONS 16
403
404 enum dpaa2_eth_fq_type {
405 DPAA2_RX_FQ = 0,
406 DPAA2_TX_CONF_FQ,
407 DPAA2_RX_ERR_FQ
408 };
409
410 struct dpaa2_eth_priv;
411
412 struct dpaa2_eth_xdp_fds {
413 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
414 ssize_t num;
415 };
416
417 struct dpaa2_eth_fq {
418 u32 fqid;
419 u32 tx_qdbin;
420 u32 tx_fqid[DPAA2_ETH_MAX_TCS];
421 u16 flowid;
422 u8 tc;
423 int target_cpu;
424 u32 dq_frames;
425 u32 dq_bytes;
426 struct dpaa2_eth_channel *channel;
427 enum dpaa2_eth_fq_type type;
428
429 void (*consume)(struct dpaa2_eth_priv *priv,
430 struct dpaa2_eth_channel *ch,
431 const struct dpaa2_fd *fd,
432 struct dpaa2_eth_fq *fq);
433 struct dpaa2_eth_fq_stats stats;
434
435 struct dpaa2_eth_xdp_fds xdp_redirect_fds;
436 struct dpaa2_eth_xdp_fds xdp_tx_fds;
437 };
438
439 struct dpaa2_eth_ch_xdp {
440 struct bpf_prog *prog;
441 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD];
442 int drop_cnt;
443 unsigned int res;
444 };
445
446 struct dpaa2_eth_channel {
447 struct dpaa2_io_notification_ctx nctx;
448 struct fsl_mc_device *dpcon;
449 int dpcon_id;
450 int ch_id;
451 struct napi_struct napi;
452 struct dpaa2_io *dpio;
453 struct dpaa2_io_store *store;
454 struct dpaa2_eth_priv *priv;
455 int buf_count;
456 struct dpaa2_eth_ch_stats stats;
457 struct dpaa2_eth_ch_xdp xdp;
458 struct xdp_rxq_info xdp_rxq;
459 struct list_head *rx_list;
460 };
461
462 struct dpaa2_eth_dist_fields {
463 u64 rxnfc_field;
464 enum net_prot cls_prot;
465 int cls_field;
466 int size;
467 u64 id;
468 };
469
470 struct dpaa2_eth_cls_rule {
471 struct ethtool_rx_flow_spec fs;
472 u8 in_use;
473 };
474
475 #define DPAA2_ETH_SGT_CACHE_SIZE 256
476 struct dpaa2_eth_sgt_cache {
477 void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
478 u16 count;
479 };
480
481 struct dpaa2_eth_trap_item {
482 void *trap_ctx;
483 };
484
485 struct dpaa2_eth_trap_data {
486 struct dpaa2_eth_trap_item *trap_items_arr;
487 struct dpaa2_eth_priv *priv;
488 };
489
490 /* Driver private data */
491 struct dpaa2_eth_priv {
492 struct net_device *net_dev;
493
494 u8 num_fqs;
495 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
496 int (*enqueue)(struct dpaa2_eth_priv *priv,
497 struct dpaa2_eth_fq *fq,
498 struct dpaa2_fd *fd, u8 prio,
499 u32 num_frames,
500 int *frames_enqueued);
501
502 u8 num_channels;
503 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
504 struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
505
506 struct dpni_attr dpni_attrs;
507 u16 dpni_ver_major;
508 u16 dpni_ver_minor;
509 u16 tx_data_offset;
510
511 struct fsl_mc_device *dpbp_dev;
512 u16 rx_buf_size;
513 u16 bpid;
514 struct iommu_domain *iommu_domain;
515
516 enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */
517 bool rx_tstamp; /* Rx timestamping enabled */
518
519 u16 tx_qdid;
520 struct fsl_mc_io *mc_io;
521 /* Cores which have an affine DPIO/DPCON.
522 * This is the cpu set on which Rx and Tx conf frames are processed
523 */
524 struct cpumask dpio_cpumask;
525
526 /* Standard statistics */
527 struct rtnl_link_stats64 __percpu *percpu_stats;
528 /* Extra stats, in addition to the ones known by the kernel */
529 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
530
531 u16 mc_token;
532 u8 rx_fqtd_enabled;
533 u8 rx_cgtd_enabled;
534
535 struct dpni_link_state link_state;
536 bool do_link_poll;
537 struct task_struct *poll_thread;
538
539 /* enabled ethtool hashing bits */
540 u64 rx_hash_fields;
541 u64 rx_cls_fields;
542 struct dpaa2_eth_cls_rule *cls_rules;
543 u8 rx_cls_enabled;
544 u8 vlan_cls_enabled;
545 u8 pfc_enabled;
546 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
547 u8 dcbx_mode;
548 struct ieee_pfc pfc;
549 #endif
550 struct bpf_prog *xdp_prog;
551 #ifdef CONFIG_DEBUG_FS
552 struct dpaa2_debugfs dbg;
553 #endif
554
555 struct dpaa2_mac *mac;
556 struct workqueue_struct *dpaa2_ptp_wq;
557 struct work_struct tx_onestep_tstamp;
558 struct sk_buff_head tx_skbs;
559 /* The one-step timestamping configuration on hardware
560 * registers could only be done when no one-step
561 * timestamping frames are in flight. So we use a mutex
562 * lock here to make sure the lock is released by last
563 * one-step timestamping packet through TX confirmation
564 * queue before transmit current packet.
565 */
566 struct mutex onestep_tstamp_lock;
567 struct devlink *devlink;
568 struct dpaa2_eth_trap_data *trap_data;
569 struct devlink_port devlink_port;
570 };
571
572 struct dpaa2_eth_devlink_priv {
573 struct dpaa2_eth_priv *dpaa2_priv;
574 };
575
576 #define TX_TSTAMP 0x1
577 #define TX_TSTAMP_ONESTEP_SYNC 0x2
578
579 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
580 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
581 | RXH_L4_B_2_3)
582
583 /* default Rx hash options, set during probing */
584 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
585 RXH_L4_B_0_1 | RXH_L4_B_2_3)
586
587 #define dpaa2_eth_hash_enabled(priv) \
588 ((priv)->dpni_attrs.num_queues > 1)
589
590 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
591 #define DPAA2_CLASSIFIER_DMA_SIZE 256
592
593 extern const struct ethtool_ops dpaa2_ethtool_ops;
594 extern int dpaa2_phc_index;
595 extern struct ptp_qoriq *dpaa2_ptp;
596
dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv * priv,u16 ver_major,u16 ver_minor)597 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
598 u16 ver_major, u16 ver_minor)
599 {
600 if (priv->dpni_ver_major == ver_major)
601 return priv->dpni_ver_minor - ver_minor;
602 return priv->dpni_ver_major - ver_major;
603 }
604
605 /* Minimum firmware version that supports a more flexible API
606 * for configuring the Rx flow hash key
607 */
608 #define DPNI_RX_DIST_KEY_VER_MAJOR 7
609 #define DPNI_RX_DIST_KEY_VER_MINOR 5
610
611 #define dpaa2_eth_has_legacy_dist(priv) \
612 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
613 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
614
615 #define dpaa2_eth_fs_enabled(priv) \
616 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
617
618 #define dpaa2_eth_fs_mask_enabled(priv) \
619 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
620
621 #define dpaa2_eth_fs_count(priv) \
622 ((priv)->dpni_attrs.fs_entries)
623
624 #define dpaa2_eth_tc_count(priv) \
625 ((priv)->dpni_attrs.num_tcs)
626
627 /* We have exactly one {Rx, Tx conf} queue per channel */
628 #define dpaa2_eth_queue_count(priv) \
629 ((priv)->num_channels)
630
631 enum dpaa2_eth_rx_dist {
632 DPAA2_ETH_RX_DIST_HASH,
633 DPAA2_ETH_RX_DIST_CLS
634 };
635
636 /* Unique IDs for the supported Rx classification header fields */
637 #define DPAA2_ETH_DIST_ETHDST BIT(0)
638 #define DPAA2_ETH_DIST_ETHSRC BIT(1)
639 #define DPAA2_ETH_DIST_ETHTYPE BIT(2)
640 #define DPAA2_ETH_DIST_VLAN BIT(3)
641 #define DPAA2_ETH_DIST_IPSRC BIT(4)
642 #define DPAA2_ETH_DIST_IPDST BIT(5)
643 #define DPAA2_ETH_DIST_IPPROTO BIT(6)
644 #define DPAA2_ETH_DIST_L4SRC BIT(7)
645 #define DPAA2_ETH_DIST_L4DST BIT(8)
646 #define DPAA2_ETH_DIST_ALL (~0ULL)
647
648 #define DPNI_PAUSE_VER_MAJOR 7
649 #define DPNI_PAUSE_VER_MINOR 13
650 #define dpaa2_eth_has_pause_support(priv) \
651 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
652 DPNI_PAUSE_VER_MINOR) >= 0)
653
dpaa2_eth_tx_pause_enabled(u64 link_options)654 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
655 {
656 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
657 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
658 }
659
dpaa2_eth_rx_pause_enabled(u64 link_options)660 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
661 {
662 return !!(link_options & DPNI_LINK_OPT_PAUSE);
663 }
664
dpaa2_eth_needed_headroom(struct sk_buff * skb)665 static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
666 {
667 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
668
669 /* If we don't have an skb (e.g. XDP buffer), we only need space for
670 * the software annotation area
671 */
672 if (!skb)
673 return headroom;
674
675 /* For non-linear skbs we have no headroom requirement, as we build a
676 * SG frame with a newly allocated SGT buffer
677 */
678 if (skb_is_nonlinear(skb))
679 return 0;
680
681 /* If we have Tx timestamping, need 128B hardware annotation */
682 if (skb->cb[0])
683 headroom += DPAA2_ETH_TX_HWA_SIZE;
684
685 return headroom;
686 }
687
688 /* Extra headroom space requested to hardware, in order to make sure there's
689 * no realloc'ing in forwarding scenarios
690 */
dpaa2_eth_rx_head_room(struct dpaa2_eth_priv * priv)691 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
692 {
693 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
694 }
695
696 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
697 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
698 int dpaa2_eth_cls_key_size(u64 key);
699 int dpaa2_eth_cls_fld_off(int prot, int field);
700 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
701
702 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
703 bool tx_pause, bool pfc);
704
705 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
706
707 int dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
708 void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
709
710 int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
711 void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
712
713 int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
714 void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
715
716 struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
717 struct dpaa2_fapr *fapr);
718 #endif /* __DPAA2_H */
719