1 /*
2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_dump.h"
29 #include "u_tracepoints.h"
30
31 #include "freedreno_resource.h"
32 #include "freedreno_tracepoints.h"
33
34 #include "fd6_compute.h"
35 #include "fd6_const.h"
36 #include "fd6_context.h"
37 #include "fd6_emit.h"
38 #include "fd6_pack.h"
39
40 /* maybe move to fd6_program? */
41 static void
cs_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * v)42 cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
43 struct ir3_shader_variant *v) assert_dt
44 {
45 const struct ir3_info *i = &v->info;
46 enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
47
48 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true,
49 .ds_state = true, .gs_state = true,
50 .fs_state = true, .cs_state = true,
51 .gfx_ibo = true, .cs_ibo = true, ));
52
53 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
54 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) |
55 A6XX_HLSQ_CS_CNTL_ENABLED);
56
57 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
58 OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
59 A6XX_SP_CS_CONFIG_NIBO(ir3_shader_nibo(v)) |
60 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
61 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_VS_CONFIG */
62 OUT_RING(ring, v->instrlen); /* SP_VS_INSTRLEN */
63
64 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
65 OUT_RING(ring,
66 A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
67 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
68 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
69 COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
70 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(v)));
71
72 uint32_t shared_size = MAX2(((int)v->cs.req_local_mem - 1) / 1024, 1);
73 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
74 OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
75 A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
76
77 if (ctx->screen->info->a6xx.has_lpac) {
78 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
79 OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
80 A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);
81 }
82
83 uint32_t local_invocation_id, work_group_id;
84 local_invocation_id =
85 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
86 work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
87
88 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
89 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
90 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
91 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
92 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
93 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
94 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz));
95
96 if (ctx->screen->info->a6xx.has_lpac) {
97 OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
98 OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
99 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
100 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
101 A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
102 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
103 A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
104 }
105
106 OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
107 OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
108
109 if (v->instrlen > 0)
110 fd6_emit_shader(ctx, ring, v);
111 }
112
113 static void
fd6_launch_grid(struct fd_context * ctx,const struct pipe_grid_info * info)114 fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
115 {
116 struct ir3_shader_key key = {};
117 struct ir3_shader_variant *v;
118 struct fd_ringbuffer *ring = ctx->batch->draw;
119 unsigned nglobal = 0;
120
121 v = ir3_shader_variant(ir3_get_shader(ctx->compute), key, false, &ctx->debug);
122 if (!v)
123 return;
124
125 if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
126 cs_program_emit(ctx, ring, v);
127
128 fd6_emit_cs_state(ctx, ring, v);
129 fd6_emit_cs_consts(v, ring, ctx, info);
130
131 u_foreach_bit (i, ctx->global_bindings.enabled_mask)
132 nglobal++;
133
134 if (nglobal > 0) {
135 /* global resources don't otherwise get an OUT_RELOC(), since
136 * the raw ptr address is emitted in ir3_emit_cs_consts().
137 * So to make the kernel aware that these buffers are referenced
138 * by the batch, emit dummy reloc's as part of a no-op packet
139 * payload:
140 */
141 OUT_PKT7(ring, CP_NOP, 2 * nglobal);
142 u_foreach_bit (i, ctx->global_bindings.enabled_mask) {
143 struct pipe_resource *prsc = ctx->global_bindings.buf[i];
144 OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
145 }
146 }
147
148 OUT_PKT7(ring, CP_SET_MARKER, 1);
149 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
150
151 const unsigned *local_size =
152 info->block; // v->shader->nir->info->workgroup_size;
153 const unsigned *num_groups = info->grid;
154 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
155 const unsigned work_dim = info->work_dim ? info->work_dim : 3;
156 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
157 OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
158 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
159 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
160 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
161 OUT_RING(ring,
162 A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
163 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
164 OUT_RING(ring,
165 A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
166 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
167 OUT_RING(ring,
168 A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
169 OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
170
171 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
172 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_X */
173 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
174 OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
175
176 trace_grid_info(&ctx->batch->trace, ring, info);
177 trace_start_compute(&ctx->batch->trace, ring);
178
179 if (info->indirect) {
180 struct fd_resource *rsc = fd_resource(info->indirect);
181
182 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
183 OUT_RING(ring, 0x00000000);
184 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
185 OUT_RING(ring,
186 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
187 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
188 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
189 } else {
190 OUT_PKT7(ring, CP_EXEC_CS, 4);
191 OUT_RING(ring, 0x00000000);
192 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
193 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
194 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
195 }
196
197 trace_end_compute(&ctx->batch->trace, ring);
198
199 OUT_WFI5(ring);
200
201 fd6_cache_flush(ctx->batch, ring);
202 }
203
204 void
fd6_compute_init(struct pipe_context * pctx)205 fd6_compute_init(struct pipe_context *pctx) disable_thread_safety_analysis
206 {
207 struct fd_context *ctx = fd_context(pctx);
208 ctx->launch_grid = fd6_launch_grid;
209 pctx->create_compute_state = ir3_shader_compute_state_create;
210 pctx->delete_compute_state = ir3_shader_state_delete;
211 }
212