1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
10
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <net/dsa.h>
20
21 #define EDSA_HLEN 8
22 #define MV88E6XXX_N_FID 4096
23
24 /* PVT limits for 4-bit port and 5-bit switch */
25 #define MV88E6XXX_MAX_PVT_SWITCHES 32
26 #define MV88E6XXX_MAX_PVT_PORTS 16
27
28 #define MV88E6XXX_MAX_GPIO 16
29
30 enum mv88e6xxx_egress_mode {
31 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
32 MV88E6XXX_EGRESS_MODE_UNTAGGED,
33 MV88E6XXX_EGRESS_MODE_TAGGED,
34 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
35 };
36
37 enum mv88e6xxx_egress_direction {
38 MV88E6XXX_EGRESS_DIR_INGRESS,
39 MV88E6XXX_EGRESS_DIR_EGRESS,
40 };
41
42 enum mv88e6xxx_frame_mode {
43 MV88E6XXX_FRAME_MODE_NORMAL,
44 MV88E6XXX_FRAME_MODE_DSA,
45 MV88E6XXX_FRAME_MODE_PROVIDER,
46 MV88E6XXX_FRAME_MODE_ETHERTYPE,
47 };
48
49 /* List of supported models */
50 enum mv88e6xxx_model {
51 MV88E6085,
52 MV88E6095,
53 MV88E6097,
54 MV88E6123,
55 MV88E6131,
56 MV88E6141,
57 MV88E6161,
58 MV88E6165,
59 MV88E6171,
60 MV88E6172,
61 MV88E6175,
62 MV88E6176,
63 MV88E6185,
64 MV88E6190,
65 MV88E6190X,
66 MV88E6191,
67 MV88E6220,
68 MV88E6240,
69 MV88E6250,
70 MV88E6290,
71 MV88E6320,
72 MV88E6321,
73 MV88E6341,
74 MV88E6350,
75 MV88E6351,
76 MV88E6352,
77 MV88E6390,
78 MV88E6390X,
79 };
80
81 enum mv88e6xxx_family {
82 MV88E6XXX_FAMILY_NONE,
83 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
84 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
85 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
86 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
87 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
88 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
89 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
90 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
91 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
92 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
93 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
94 };
95
96 struct mv88e6xxx_ops;
97
98 struct mv88e6xxx_info {
99 enum mv88e6xxx_family family;
100 u16 prod_num;
101 const char *name;
102 unsigned int num_databases;
103 unsigned int num_macs;
104 unsigned int num_ports;
105 unsigned int num_internal_phys;
106 unsigned int num_gpio;
107 unsigned int max_vid;
108 unsigned int port_base_addr;
109 unsigned int phy_base_addr;
110 unsigned int global1_addr;
111 unsigned int global2_addr;
112 unsigned int age_time_coeff;
113 unsigned int g1_irqs;
114 unsigned int g2_irqs;
115 bool pvt;
116
117 /* Mark certain ports as invalid. This is required for example for the
118 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
119 * ports 2-4 are not routet to pins.
120 */
121 unsigned int invalid_port_mask;
122 /* Multi-chip Addressing Mode.
123 * Some chips respond to only 2 registers of its own SMI device address
124 * when it is non-zero, and use indirect access to internal registers.
125 */
126 bool multi_chip;
127 /* Dual-chip Addressing Mode
128 * Some chips respond to only half of the 32 SMI addresses,
129 * allowing two to coexist on the same SMI interface.
130 */
131 bool dual_chip;
132
133 enum dsa_tag_protocol tag_protocol;
134
135 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
136 * operation. 0 means that the ATU Move operation is not supported.
137 */
138 u8 atu_move_port_mask;
139 const struct mv88e6xxx_ops *ops;
140
141 /* Supports PTP */
142 bool ptp_support;
143 };
144
145 struct mv88e6xxx_atu_entry {
146 u8 state;
147 bool trunk;
148 u16 portvec;
149 u8 mac[ETH_ALEN];
150 };
151
152 struct mv88e6xxx_vtu_entry {
153 u16 vid;
154 u16 fid;
155 u8 sid;
156 bool valid;
157 u8 member[DSA_MAX_PORTS];
158 u8 state[DSA_MAX_PORTS];
159 };
160
161 struct mv88e6xxx_bus_ops;
162 struct mv88e6xxx_irq_ops;
163 struct mv88e6xxx_gpio_ops;
164 struct mv88e6xxx_avb_ops;
165 struct mv88e6xxx_ptp_ops;
166
167 struct mv88e6xxx_irq {
168 u16 masked;
169 struct irq_chip chip;
170 struct irq_domain *domain;
171 int nirqs;
172 };
173
174 /* state flags for mv88e6xxx_port_hwtstamp::state */
175 enum {
176 MV88E6XXX_HWTSTAMP_ENABLED,
177 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
178 };
179
180 struct mv88e6xxx_port_hwtstamp {
181 /* Port index */
182 int port_id;
183
184 /* Timestamping state */
185 unsigned long state;
186
187 /* Resources for receive timestamping */
188 struct sk_buff_head rx_queue;
189 struct sk_buff_head rx_queue2;
190
191 /* Resources for transmit timestamping */
192 unsigned long tx_tstamp_start;
193 struct sk_buff *tx_skb;
194 u16 tx_seq_id;
195
196 /* Current timestamp configuration */
197 struct hwtstamp_config tstamp_config;
198 };
199
200 enum mv88e6xxx_policy_mapping {
201 MV88E6XXX_POLICY_MAPPING_DA,
202 MV88E6XXX_POLICY_MAPPING_SA,
203 MV88E6XXX_POLICY_MAPPING_VTU,
204 MV88E6XXX_POLICY_MAPPING_ETYPE,
205 MV88E6XXX_POLICY_MAPPING_PPPOE,
206 MV88E6XXX_POLICY_MAPPING_VBAS,
207 MV88E6XXX_POLICY_MAPPING_OPT82,
208 MV88E6XXX_POLICY_MAPPING_UDP,
209 };
210
211 enum mv88e6xxx_policy_action {
212 MV88E6XXX_POLICY_ACTION_NORMAL,
213 MV88E6XXX_POLICY_ACTION_MIRROR,
214 MV88E6XXX_POLICY_ACTION_TRAP,
215 MV88E6XXX_POLICY_ACTION_DISCARD,
216 };
217
218 struct mv88e6xxx_policy {
219 enum mv88e6xxx_policy_mapping mapping;
220 enum mv88e6xxx_policy_action action;
221 struct ethtool_rx_flow_spec fs;
222 u8 addr[ETH_ALEN];
223 int port;
224 u16 vid;
225 };
226
227 struct mv88e6xxx_port {
228 struct mv88e6xxx_chip *chip;
229 int port;
230 u64 serdes_stats[2];
231 u64 atu_member_violation;
232 u64 atu_miss_violation;
233 u64 atu_full_violation;
234 u64 vtu_member_violation;
235 u64 vtu_miss_violation;
236 phy_interface_t interface;
237 u8 cmode;
238 bool mirror_ingress;
239 bool mirror_egress;
240 unsigned int serdes_irq;
241 char serdes_irq_name[64];
242 struct devlink_region *region;
243 };
244
245 enum mv88e6xxx_region_id {
246 MV88E6XXX_REGION_GLOBAL1 = 0,
247 MV88E6XXX_REGION_GLOBAL2,
248 MV88E6XXX_REGION_ATU,
249
250 _MV88E6XXX_REGION_MAX,
251 };
252
253 struct mv88e6xxx_region_priv {
254 enum mv88e6xxx_region_id id;
255 };
256
257 struct mv88e6xxx_chip {
258 const struct mv88e6xxx_info *info;
259
260 /* The dsa_switch this private structure is related to */
261 struct dsa_switch *ds;
262
263 /* The device this structure is associated to */
264 struct device *dev;
265
266 /* This mutex protects the access to the switch registers */
267 struct mutex reg_lock;
268
269 /* The MII bus and the address on the bus that is used to
270 * communication with the switch
271 */
272 const struct mv88e6xxx_bus_ops *smi_ops;
273 struct mii_bus *bus;
274 int sw_addr;
275
276 /* Handles automatic disabling and re-enabling of the PHY
277 * polling unit.
278 */
279 const struct mv88e6xxx_bus_ops *phy_ops;
280 struct mutex ppu_mutex;
281 int ppu_disabled;
282 struct work_struct ppu_work;
283 struct timer_list ppu_timer;
284
285 /* This mutex serialises access to the statistics unit.
286 * Hold this mutex over snapshot + dump sequences.
287 */
288 struct mutex stats_mutex;
289
290 /* A switch may have a GPIO line tied to its reset pin. Parse
291 * this from the device tree, and use it before performing
292 * switch soft reset.
293 */
294 struct gpio_desc *reset;
295
296 /* set to size of eeprom if supported by the switch */
297 u32 eeprom_len;
298
299 /* List of mdio busses */
300 struct list_head mdios;
301
302 /* Policy Control List IDs and rules */
303 struct idr policies;
304
305 /* There can be two interrupt controllers, which are chained
306 * off a GPIO as interrupt source
307 */
308 struct mv88e6xxx_irq g1_irq;
309 struct mv88e6xxx_irq g2_irq;
310 int irq;
311 char irq_name[64];
312 int device_irq;
313 char device_irq_name[64];
314 int watchdog_irq;
315 char watchdog_irq_name[64];
316
317 int atu_prob_irq;
318 char atu_prob_irq_name[64];
319 int vtu_prob_irq;
320 char vtu_prob_irq_name[64];
321 struct kthread_worker *kworker;
322 struct kthread_delayed_work irq_poll_work;
323
324 /* GPIO resources */
325 u8 gpio_data[2];
326
327 /* This cyclecounter abstracts the switch PTP time.
328 * reg_lock must be held for any operation that read()s.
329 */
330 struct cyclecounter tstamp_cc;
331 struct timecounter tstamp_tc;
332 struct delayed_work overflow_work;
333
334 struct ptp_clock *ptp_clock;
335 struct ptp_clock_info ptp_clock_info;
336 struct delayed_work tai_event_work;
337 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
338 u16 trig_config;
339 u16 evcap_config;
340 u16 enable_count;
341
342 /* Current ingress and egress monitor ports */
343 int egress_dest_port;
344 int ingress_dest_port;
345
346 /* Per-port timestamping resources. */
347 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
348
349 /* Array of port structures. */
350 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
351
352 /* devlink regions */
353 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
354 };
355
356 struct mv88e6xxx_bus_ops {
357 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
358 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
359 };
360
361 struct mv88e6xxx_mdio_bus {
362 struct mii_bus *bus;
363 struct mv88e6xxx_chip *chip;
364 struct list_head list;
365 bool external;
366 };
367
368 struct mv88e6xxx_ops {
369 /* Switch Setup Errata, called early in the switch setup to
370 * allow any errata actions to be performed
371 */
372 int (*setup_errata)(struct mv88e6xxx_chip *chip);
373
374 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
375 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
376
377 /* Ingress Rate Limit unit (IRL) operations */
378 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
379
380 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
386
387 int (*phy_read)(struct mv88e6xxx_chip *chip,
388 struct mii_bus *bus,
389 int addr, int reg, u16 *val);
390 int (*phy_write)(struct mv88e6xxx_chip *chip,
391 struct mii_bus *bus,
392 int addr, int reg, u16 val);
393
394 /* Priority Override Table operations */
395 int (*pot_clear)(struct mv88e6xxx_chip *chip);
396
397 /* PHY Polling Unit (PPU) operations */
398 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
399 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
400
401 /* Switch Software Reset */
402 int (*reset)(struct mv88e6xxx_chip *chip);
403
404 /* RGMII Receive/Transmit Timing Control
405 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
406 */
407 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
408 phy_interface_t mode);
409
410 #define LINK_FORCED_DOWN 0
411 #define LINK_FORCED_UP 1
412 #define LINK_UNFORCED -2
413
414 /* Port's MAC link state
415 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
416 * or LINK_UNFORCED for normal link detection.
417 */
418 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
419
420 #define PAUSE_ON 1
421 #define PAUSE_OFF 0
422
423 /* Enable/disable sending Pause */
424 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
425 int pause);
426
427 #define SPEED_MAX INT_MAX
428 #define SPEED_UNFORCED -2
429 #define DUPLEX_UNFORCED -2
430
431 /* Port's MAC speed (in Mbps) and MAC duplex mode
432 *
433 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
434 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
435 *
436 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
437 * or DUPLEX_UNFORCED for normal duplex detection.
438 */
439 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
440 int speed, int duplex);
441
442 /* What interface mode should be used for maximum speed? */
443 phy_interface_t (*port_max_speed_mode)(int port);
444
445 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
446
447 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
448 enum mv88e6xxx_policy_mapping mapping,
449 enum mv88e6xxx_policy_action action);
450
451 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
452 enum mv88e6xxx_frame_mode mode);
453 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
454 bool unicast, bool multicast);
455 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
456 u16 etype);
457 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
458 size_t size);
459
460 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
461 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
462 u8 out);
463 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
464 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
465 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
466
467 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
468 * Some chips allow this to be configured on specific ports.
469 */
470 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
471 phy_interface_t mode);
472 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
473
474 /* Some devices have a per port register indicating what is
475 * the upstream port this port should forward to.
476 */
477 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
478 int upstream_port);
479
480 /* Snapshot the statistics for a port. The statistics can then
481 * be read back a leisure but still with a consistent view.
482 */
483 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
484
485 /* Set the histogram mode for statistics, when the control registers
486 * are separated out of the STATS_OP register.
487 */
488 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
489
490 /* Return the number of strings describing statistics */
491 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
492 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
493 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
494 uint64_t *data);
495 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
496 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
497 enum mv88e6xxx_egress_direction direction,
498 int port);
499
500 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
501 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
502
503 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
504
505 const struct mv88e6xxx_irq_ops *watchdog_ops;
506
507 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
508
509 /* Power on/off a SERDES interface */
510 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
511 bool up);
512
513 /* SERDES lane mapping */
514 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
515
516 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
517 u8 lane, struct phylink_link_state *state);
518 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
519 u8 lane, unsigned int mode,
520 phy_interface_t interface,
521 const unsigned long *advertise);
522 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
523 u8 lane);
524 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
525 u8 lane, int speed, int duplex);
526
527 /* SERDES interrupt handling */
528 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
529 int port);
530 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
531 bool enable);
532 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
533 u8 lane);
534
535 /* Statistics from the SERDES interface */
536 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
537 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
538 uint8_t *data);
539 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
540 uint64_t *data);
541
542 /* SERDES registers for ethtool */
543 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
544 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
545 void *_p);
546
547 /* Address Translation Unit operations */
548 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
549 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
550
551 /* VLAN Translation Unit operations */
552 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
553 struct mv88e6xxx_vtu_entry *entry);
554 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
555 struct mv88e6xxx_vtu_entry *entry);
556
557 /* GPIO operations */
558 const struct mv88e6xxx_gpio_ops *gpio_ops;
559
560 /* Interface to the AVB/PTP registers */
561 const struct mv88e6xxx_avb_ops *avb_ops;
562
563 /* Remote Management Unit operations */
564 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
565
566 /* Precision Time Protocol operations */
567 const struct mv88e6xxx_ptp_ops *ptp_ops;
568
569 /* Phylink */
570 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
571 unsigned long *mask,
572 struct phylink_link_state *state);
573
574 /* Max Frame Size */
575 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
576 };
577
578 struct mv88e6xxx_irq_ops {
579 /* Action to be performed when the interrupt happens */
580 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
581 /* Setup the hardware to generate the interrupt */
582 int (*irq_setup)(struct mv88e6xxx_chip *chip);
583 /* Reset the hardware to stop generating the interrupt */
584 void (*irq_free)(struct mv88e6xxx_chip *chip);
585 };
586
587 struct mv88e6xxx_gpio_ops {
588 /* Get/set data on GPIO pin */
589 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
590 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
591 int value);
592
593 /* get/set GPIO direction */
594 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
595 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
596 bool input);
597
598 /* get/set GPIO pin control */
599 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
600 int *func);
601 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
602 int func);
603 };
604
605 struct mv88e6xxx_avb_ops {
606 /* Access port-scoped Precision Time Protocol registers */
607 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
608 u16 *data, int len);
609 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
610 u16 data);
611
612 /* Access global Precision Time Protocol registers */
613 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
614 int len);
615 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
616
617 /* Access global Time Application Interface registers */
618 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
619 int len);
620 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
621 };
622
623 struct mv88e6xxx_ptp_ops {
624 u64 (*clock_read)(const struct cyclecounter *cc);
625 int (*ptp_enable)(struct ptp_clock_info *ptp,
626 struct ptp_clock_request *rq, int on);
627 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
628 enum ptp_pin_function func, unsigned int chan);
629 void (*event_work)(struct work_struct *ugly);
630 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
631 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
632 int (*global_enable)(struct mv88e6xxx_chip *chip);
633 int (*global_disable)(struct mv88e6xxx_chip *chip);
634 int n_ext_ts;
635 int arr0_sts_reg;
636 int arr1_sts_reg;
637 int dep_sts_reg;
638 u32 rx_filters;
639 u32 cc_shift;
640 u32 cc_mult;
641 u32 cc_mult_num;
642 u32 cc_mult_dem;
643 };
644
645 #define STATS_TYPE_PORT BIT(0)
646 #define STATS_TYPE_BANK0 BIT(1)
647 #define STATS_TYPE_BANK1 BIT(2)
648
649 struct mv88e6xxx_hw_stat {
650 char string[ETH_GSTRING_LEN];
651 size_t size;
652 int reg;
653 int type;
654 };
655
mv88e6xxx_has_pvt(struct mv88e6xxx_chip * chip)656 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
657 {
658 return chip->info->pvt;
659 }
660
mv88e6xxx_num_databases(struct mv88e6xxx_chip * chip)661 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
662 {
663 return chip->info->num_databases;
664 }
665
mv88e6xxx_num_macs(struct mv88e6xxx_chip * chip)666 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
667 {
668 return chip->info->num_macs;
669 }
670
mv88e6xxx_num_ports(struct mv88e6xxx_chip * chip)671 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
672 {
673 return chip->info->num_ports;
674 }
675
mv88e6xxx_port_mask(struct mv88e6xxx_chip * chip)676 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
677 {
678 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
679 }
680
mv88e6xxx_num_gpio(struct mv88e6xxx_chip * chip)681 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
682 {
683 return chip->info->num_gpio;
684 }
685
mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip * chip,int port)686 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
687 {
688 return (chip->info->invalid_port_mask & BIT(port)) != 0;
689 }
690
691 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
692 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
693 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
694 u16 mask, u16 val);
695 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
696 int bit, int val);
697 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
698
mv88e6xxx_reg_lock(struct mv88e6xxx_chip * chip)699 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
700 {
701 mutex_lock(&chip->reg_lock);
702 }
703
mv88e6xxx_reg_unlock(struct mv88e6xxx_chip * chip)704 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
705 {
706 mutex_unlock(&chip->reg_lock);
707 }
708
709 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
710
711 #endif /* _MV88E6XXX_CHIP_H */
712