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1 /*
2  * Copyright © 2009 Corbin Simpson
3  * Copyright © 2015 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining
7  * a copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * The above copyright notice and this permission notice (including the
24  * next paragraph) shall be included in all copies or substantial portions
25  * of the Software.
26  */
27 
28 #ifndef AMDGPU_WINSYS_H
29 #define AMDGPU_WINSYS_H
30 
31 #include "pipebuffer/pb_cache.h"
32 #include "pipebuffer/pb_slab.h"
33 #include "winsys/radeon_winsys.h"
34 #include "util/simple_mtx.h"
35 #include "util/u_queue.h"
36 #include <amdgpu.h>
37 
38 struct amdgpu_cs;
39 
40 #define NUM_SLAB_ALLOCATORS 3
41 
42 struct amdgpu_screen_winsys {
43    struct radeon_winsys base;
44    struct amdgpu_winsys *aws;
45    int fd;
46    struct pipe_reference reference;
47    struct amdgpu_screen_winsys *next;
48 
49    /* Maps a BO to its KMS handle valid for this DRM file descriptor
50     * Protected by amdgpu_winsys::sws_list_lock
51     */
52    struct hash_table *kms_handles;
53 };
54 
55 struct amdgpu_winsys {
56    struct pipe_reference reference;
57 
58    /* File descriptor which was passed to amdgpu_device_initialize */
59    int fd;
60 
61    struct pb_cache bo_cache;
62 
63    /* Each slab buffer can only contain suballocations of equal sizes, so we
64     * need to layer the allocators, so that we don't waste too much memory.
65     */
66    struct pb_slabs bo_slabs[NUM_SLAB_ALLOCATORS];
67 
68    amdgpu_device_handle dev;
69 
70    simple_mtx_t bo_fence_lock;
71 
72    int num_cs; /* The number of command streams created. */
73    unsigned num_total_rejected_cs;
74    uint32_t surf_index_color;
75    uint32_t surf_index_fmask;
76    uint32_t next_bo_unique_id;
77    uint64_t allocated_vram;
78    uint64_t allocated_gtt;
79    uint64_t mapped_vram;
80    uint64_t mapped_gtt;
81    uint64_t slab_wasted_vram;
82    uint64_t slab_wasted_gtt;
83    uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
84    uint64_t num_gfx_IBs;
85    uint64_t num_sdma_IBs;
86    uint64_t num_mapped_buffers;
87    uint64_t gfx_bo_list_counter;
88    uint64_t gfx_ib_size_counter;
89 
90    struct radeon_info info;
91 
92    /* multithreaded IB submission */
93    struct util_queue cs_queue;
94 
95    struct ac_addrlib *addrlib;
96 
97    bool check_vm;
98    bool noop_cs;
99    bool reserve_vmid;
100    bool zero_all_vram_allocs;
101 #if DEBUG
102    bool debug_all_bos;
103 
104    /* List of all allocated buffers */
105    simple_mtx_t global_bo_list_lock;
106    struct list_head global_bo_list;
107    unsigned num_buffers;
108 #endif
109 
110    /* Single-linked list of all structs amdgpu_screen_winsys referencing this
111     * struct amdgpu_winsys
112     */
113    simple_mtx_t sws_list_lock;
114    struct amdgpu_screen_winsys *sws_list;
115 
116    /* For returning the same amdgpu_winsys_bo instance for exported
117     * and re-imported buffers. */
118    struct hash_table *bo_export_table;
119    simple_mtx_t bo_export_table_lock;
120 
121    /* Since most winsys functions require struct radeon_winsys *, dummy_ws.base is used
122     * for invoking them because sws_list can be NULL.
123     */
124    struct amdgpu_screen_winsys dummy_ws;
125 };
126 
127 static inline struct amdgpu_screen_winsys *
amdgpu_screen_winsys(struct radeon_winsys * base)128 amdgpu_screen_winsys(struct radeon_winsys *base)
129 {
130    return (struct amdgpu_screen_winsys*)base;
131 }
132 
133 static inline struct amdgpu_winsys *
amdgpu_winsys(struct radeon_winsys * base)134 amdgpu_winsys(struct radeon_winsys *base)
135 {
136    return amdgpu_screen_winsys(base)->aws;
137 }
138 
139 void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *ws);
140 
141 #endif
142