1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Google virtual Ethernet (gve) driver
3 *
4 * Copyright (C) 2015-2019 Google, Inc.
5 */
6
7 #include <linux/etherdevice.h>
8 #include <linux/pci.h>
9 #include "gve.h"
10 #include "gve_adminq.h"
11 #include "gve_register.h"
12
13 #define GVE_MAX_ADMINQ_RELEASE_CHECK 500
14 #define GVE_ADMINQ_SLEEP_LEN 20
15 #define GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK 100
16
gve_adminq_alloc(struct device * dev,struct gve_priv * priv)17 int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)
18 {
19 priv->adminq = dma_alloc_coherent(dev, PAGE_SIZE,
20 &priv->adminq_bus_addr, GFP_KERNEL);
21 if (unlikely(!priv->adminq))
22 return -ENOMEM;
23
24 priv->adminq_mask = (PAGE_SIZE / sizeof(union gve_adminq_command)) - 1;
25 priv->adminq_prod_cnt = 0;
26 priv->adminq_cmd_fail = 0;
27 priv->adminq_timeouts = 0;
28 priv->adminq_describe_device_cnt = 0;
29 priv->adminq_cfg_device_resources_cnt = 0;
30 priv->adminq_register_page_list_cnt = 0;
31 priv->adminq_unregister_page_list_cnt = 0;
32 priv->adminq_create_tx_queue_cnt = 0;
33 priv->adminq_create_rx_queue_cnt = 0;
34 priv->adminq_destroy_tx_queue_cnt = 0;
35 priv->adminq_destroy_rx_queue_cnt = 0;
36 priv->adminq_dcfg_device_resources_cnt = 0;
37 priv->adminq_set_driver_parameter_cnt = 0;
38 priv->adminq_report_stats_cnt = 0;
39 priv->adminq_report_link_speed_cnt = 0;
40
41 /* Setup Admin queue with the device */
42 iowrite32be(priv->adminq_bus_addr / PAGE_SIZE,
43 &priv->reg_bar0->adminq_pfn);
44
45 gve_set_admin_queue_ok(priv);
46 return 0;
47 }
48
gve_adminq_release(struct gve_priv * priv)49 void gve_adminq_release(struct gve_priv *priv)
50 {
51 int i = 0;
52
53 /* Tell the device the adminq is leaving */
54 iowrite32be(0x0, &priv->reg_bar0->adminq_pfn);
55 while (ioread32be(&priv->reg_bar0->adminq_pfn)) {
56 /* If this is reached the device is unrecoverable and still
57 * holding memory. Continue looping to avoid memory corruption,
58 * but WARN so it is visible what is going on.
59 */
60 if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)
61 WARN(1, "Unrecoverable platform error!");
62 i++;
63 msleep(GVE_ADMINQ_SLEEP_LEN);
64 }
65 gve_clear_device_rings_ok(priv);
66 gve_clear_device_resources_ok(priv);
67 gve_clear_admin_queue_ok(priv);
68 }
69
gve_adminq_free(struct device * dev,struct gve_priv * priv)70 void gve_adminq_free(struct device *dev, struct gve_priv *priv)
71 {
72 if (!gve_get_admin_queue_ok(priv))
73 return;
74 gve_adminq_release(priv);
75 dma_free_coherent(dev, PAGE_SIZE, priv->adminq, priv->adminq_bus_addr);
76 gve_clear_admin_queue_ok(priv);
77 }
78
gve_adminq_kick_cmd(struct gve_priv * priv,u32 prod_cnt)79 static void gve_adminq_kick_cmd(struct gve_priv *priv, u32 prod_cnt)
80 {
81 iowrite32be(prod_cnt, &priv->reg_bar0->adminq_doorbell);
82 }
83
gve_adminq_wait_for_cmd(struct gve_priv * priv,u32 prod_cnt)84 static bool gve_adminq_wait_for_cmd(struct gve_priv *priv, u32 prod_cnt)
85 {
86 int i;
87
88 for (i = 0; i < GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK; i++) {
89 if (ioread32be(&priv->reg_bar0->adminq_event_counter)
90 == prod_cnt)
91 return true;
92 msleep(GVE_ADMINQ_SLEEP_LEN);
93 }
94
95 return false;
96 }
97
gve_adminq_parse_err(struct gve_priv * priv,u32 status)98 static int gve_adminq_parse_err(struct gve_priv *priv, u32 status)
99 {
100 if (status != GVE_ADMINQ_COMMAND_PASSED &&
101 status != GVE_ADMINQ_COMMAND_UNSET) {
102 dev_err(&priv->pdev->dev, "AQ command failed with status %d\n", status);
103 priv->adminq_cmd_fail++;
104 }
105 switch (status) {
106 case GVE_ADMINQ_COMMAND_PASSED:
107 return 0;
108 case GVE_ADMINQ_COMMAND_UNSET:
109 dev_err(&priv->pdev->dev, "parse_aq_err: err and status both unset, this should not be possible.\n");
110 return -EINVAL;
111 case GVE_ADMINQ_COMMAND_ERROR_ABORTED:
112 case GVE_ADMINQ_COMMAND_ERROR_CANCELLED:
113 case GVE_ADMINQ_COMMAND_ERROR_DATALOSS:
114 case GVE_ADMINQ_COMMAND_ERROR_FAILED_PRECONDITION:
115 case GVE_ADMINQ_COMMAND_ERROR_UNAVAILABLE:
116 return -EAGAIN;
117 case GVE_ADMINQ_COMMAND_ERROR_ALREADY_EXISTS:
118 case GVE_ADMINQ_COMMAND_ERROR_INTERNAL_ERROR:
119 case GVE_ADMINQ_COMMAND_ERROR_INVALID_ARGUMENT:
120 case GVE_ADMINQ_COMMAND_ERROR_NOT_FOUND:
121 case GVE_ADMINQ_COMMAND_ERROR_OUT_OF_RANGE:
122 case GVE_ADMINQ_COMMAND_ERROR_UNKNOWN_ERROR:
123 return -EINVAL;
124 case GVE_ADMINQ_COMMAND_ERROR_DEADLINE_EXCEEDED:
125 return -ETIME;
126 case GVE_ADMINQ_COMMAND_ERROR_PERMISSION_DENIED:
127 case GVE_ADMINQ_COMMAND_ERROR_UNAUTHENTICATED:
128 return -EACCES;
129 case GVE_ADMINQ_COMMAND_ERROR_RESOURCE_EXHAUSTED:
130 return -ENOMEM;
131 case GVE_ADMINQ_COMMAND_ERROR_UNIMPLEMENTED:
132 return -ENOTSUPP;
133 default:
134 dev_err(&priv->pdev->dev, "parse_aq_err: unknown status code %d\n", status);
135 return -EINVAL;
136 }
137 }
138
139 /* Flushes all AQ commands currently queued and waits for them to complete.
140 * If there are failures, it will return the first error.
141 */
gve_adminq_kick_and_wait(struct gve_priv * priv)142 static int gve_adminq_kick_and_wait(struct gve_priv *priv)
143 {
144 int tail, head;
145 int i;
146
147 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
148 head = priv->adminq_prod_cnt;
149
150 gve_adminq_kick_cmd(priv, head);
151 if (!gve_adminq_wait_for_cmd(priv, head)) {
152 dev_err(&priv->pdev->dev, "AQ commands timed out, need to reset AQ\n");
153 priv->adminq_timeouts++;
154 return -ENOTRECOVERABLE;
155 }
156
157 for (i = tail; i < head; i++) {
158 union gve_adminq_command *cmd;
159 u32 status, err;
160
161 cmd = &priv->adminq[i & priv->adminq_mask];
162 status = be32_to_cpu(READ_ONCE(cmd->status));
163 err = gve_adminq_parse_err(priv, status);
164 if (err)
165 // Return the first error if we failed.
166 return err;
167 }
168
169 return 0;
170 }
171
172 /* This function is not threadsafe - the caller is responsible for any
173 * necessary locks.
174 */
gve_adminq_issue_cmd(struct gve_priv * priv,union gve_adminq_command * cmd_orig)175 static int gve_adminq_issue_cmd(struct gve_priv *priv,
176 union gve_adminq_command *cmd_orig)
177 {
178 union gve_adminq_command *cmd;
179 u32 opcode;
180 u32 tail;
181
182 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
183
184 // Check if next command will overflow the buffer.
185 if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) ==
186 (tail & priv->adminq_mask)) {
187 int err;
188
189 // Flush existing commands to make room.
190 err = gve_adminq_kick_and_wait(priv);
191 if (err)
192 return err;
193
194 // Retry.
195 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
196 if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) ==
197 (tail & priv->adminq_mask)) {
198 // This should never happen. We just flushed the
199 // command queue so there should be enough space.
200 return -ENOMEM;
201 }
202 }
203
204 cmd = &priv->adminq[priv->adminq_prod_cnt & priv->adminq_mask];
205 priv->adminq_prod_cnt++;
206
207 memcpy(cmd, cmd_orig, sizeof(*cmd_orig));
208 opcode = be32_to_cpu(READ_ONCE(cmd->opcode));
209
210 switch (opcode) {
211 case GVE_ADMINQ_DESCRIBE_DEVICE:
212 priv->adminq_describe_device_cnt++;
213 break;
214 case GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES:
215 priv->adminq_cfg_device_resources_cnt++;
216 break;
217 case GVE_ADMINQ_REGISTER_PAGE_LIST:
218 priv->adminq_register_page_list_cnt++;
219 break;
220 case GVE_ADMINQ_UNREGISTER_PAGE_LIST:
221 priv->adminq_unregister_page_list_cnt++;
222 break;
223 case GVE_ADMINQ_CREATE_TX_QUEUE:
224 priv->adminq_create_tx_queue_cnt++;
225 break;
226 case GVE_ADMINQ_CREATE_RX_QUEUE:
227 priv->adminq_create_rx_queue_cnt++;
228 break;
229 case GVE_ADMINQ_DESTROY_TX_QUEUE:
230 priv->adminq_destroy_tx_queue_cnt++;
231 break;
232 case GVE_ADMINQ_DESTROY_RX_QUEUE:
233 priv->adminq_destroy_rx_queue_cnt++;
234 break;
235 case GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES:
236 priv->adminq_dcfg_device_resources_cnt++;
237 break;
238 case GVE_ADMINQ_SET_DRIVER_PARAMETER:
239 priv->adminq_set_driver_parameter_cnt++;
240 break;
241 case GVE_ADMINQ_REPORT_STATS:
242 priv->adminq_report_stats_cnt++;
243 break;
244 case GVE_ADMINQ_REPORT_LINK_SPEED:
245 priv->adminq_report_link_speed_cnt++;
246 break;
247 default:
248 dev_err(&priv->pdev->dev, "unknown AQ command opcode %d\n", opcode);
249 }
250
251 return 0;
252 }
253
254 /* This function is not threadsafe - the caller is responsible for any
255 * necessary locks.
256 * The caller is also responsible for making sure there are no commands
257 * waiting to be executed.
258 */
gve_adminq_execute_cmd(struct gve_priv * priv,union gve_adminq_command * cmd_orig)259 static int gve_adminq_execute_cmd(struct gve_priv *priv, union gve_adminq_command *cmd_orig)
260 {
261 u32 tail, head;
262 int err;
263
264 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
265 head = priv->adminq_prod_cnt;
266 if (tail != head)
267 // This is not a valid path
268 return -EINVAL;
269
270 err = gve_adminq_issue_cmd(priv, cmd_orig);
271 if (err)
272 return err;
273
274 return gve_adminq_kick_and_wait(priv);
275 }
276
277 /* The device specifies that the management vector can either be the first irq
278 * or the last irq. ntfy_blk_msix_base_idx indicates the first irq assigned to
279 * the ntfy blks. It if is 0 then the management vector is last, if it is 1 then
280 * the management vector is first.
281 *
282 * gve arranges the msix vectors so that the management vector is last.
283 */
284 #define GVE_NTFY_BLK_BASE_MSIX_IDX 0
gve_adminq_configure_device_resources(struct gve_priv * priv,dma_addr_t counter_array_bus_addr,u32 num_counters,dma_addr_t db_array_bus_addr,u32 num_ntfy_blks)285 int gve_adminq_configure_device_resources(struct gve_priv *priv,
286 dma_addr_t counter_array_bus_addr,
287 u32 num_counters,
288 dma_addr_t db_array_bus_addr,
289 u32 num_ntfy_blks)
290 {
291 union gve_adminq_command cmd;
292
293 memset(&cmd, 0, sizeof(cmd));
294 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES);
295 cmd.configure_device_resources =
296 (struct gve_adminq_configure_device_resources) {
297 .counter_array = cpu_to_be64(counter_array_bus_addr),
298 .num_counters = cpu_to_be32(num_counters),
299 .irq_db_addr = cpu_to_be64(db_array_bus_addr),
300 .num_irq_dbs = cpu_to_be32(num_ntfy_blks),
301 .irq_db_stride = cpu_to_be32(sizeof(priv->ntfy_blocks[0])),
302 .ntfy_blk_msix_base_idx =
303 cpu_to_be32(GVE_NTFY_BLK_BASE_MSIX_IDX),
304 };
305
306 return gve_adminq_execute_cmd(priv, &cmd);
307 }
308
gve_adminq_deconfigure_device_resources(struct gve_priv * priv)309 int gve_adminq_deconfigure_device_resources(struct gve_priv *priv)
310 {
311 union gve_adminq_command cmd;
312
313 memset(&cmd, 0, sizeof(cmd));
314 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES);
315
316 return gve_adminq_execute_cmd(priv, &cmd);
317 }
318
gve_adminq_create_tx_queue(struct gve_priv * priv,u32 queue_index)319 static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index)
320 {
321 struct gve_tx_ring *tx = &priv->tx[queue_index];
322 union gve_adminq_command cmd;
323 int err;
324
325 memset(&cmd, 0, sizeof(cmd));
326 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_TX_QUEUE);
327 cmd.create_tx_queue = (struct gve_adminq_create_tx_queue) {
328 .queue_id = cpu_to_be32(queue_index),
329 .reserved = 0,
330 .queue_resources_addr =
331 cpu_to_be64(tx->q_resources_bus),
332 .tx_ring_addr = cpu_to_be64(tx->bus),
333 .queue_page_list_id = cpu_to_be32(tx->tx_fifo.qpl->id),
334 .ntfy_id = cpu_to_be32(tx->ntfy_id),
335 };
336
337 err = gve_adminq_issue_cmd(priv, &cmd);
338 if (err)
339 return err;
340
341 return 0;
342 }
343
gve_adminq_create_tx_queues(struct gve_priv * priv,u32 num_queues)344 int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 num_queues)
345 {
346 int err;
347 int i;
348
349 for (i = 0; i < num_queues; i++) {
350 err = gve_adminq_create_tx_queue(priv, i);
351 if (err)
352 return err;
353 }
354
355 return gve_adminq_kick_and_wait(priv);
356 }
357
gve_adminq_create_rx_queue(struct gve_priv * priv,u32 queue_index)358 static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
359 {
360 struct gve_rx_ring *rx = &priv->rx[queue_index];
361 union gve_adminq_command cmd;
362 int err;
363
364 memset(&cmd, 0, sizeof(cmd));
365 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_RX_QUEUE);
366 cmd.create_rx_queue = (struct gve_adminq_create_rx_queue) {
367 .queue_id = cpu_to_be32(queue_index),
368 .index = cpu_to_be32(queue_index),
369 .reserved = 0,
370 .ntfy_id = cpu_to_be32(rx->ntfy_id),
371 .queue_resources_addr = cpu_to_be64(rx->q_resources_bus),
372 .rx_desc_ring_addr = cpu_to_be64(rx->desc.bus),
373 .rx_data_ring_addr = cpu_to_be64(rx->data.data_bus),
374 .queue_page_list_id = cpu_to_be32(rx->data.qpl->id),
375 };
376
377 err = gve_adminq_issue_cmd(priv, &cmd);
378 if (err)
379 return err;
380
381 return 0;
382 }
383
gve_adminq_create_rx_queues(struct gve_priv * priv,u32 num_queues)384 int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues)
385 {
386 int err;
387 int i;
388
389 for (i = 0; i < num_queues; i++) {
390 err = gve_adminq_create_rx_queue(priv, i);
391 if (err)
392 return err;
393 }
394
395 return gve_adminq_kick_and_wait(priv);
396 }
397
gve_adminq_destroy_tx_queue(struct gve_priv * priv,u32 queue_index)398 static int gve_adminq_destroy_tx_queue(struct gve_priv *priv, u32 queue_index)
399 {
400 union gve_adminq_command cmd;
401 int err;
402
403 memset(&cmd, 0, sizeof(cmd));
404 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_TX_QUEUE);
405 cmd.destroy_tx_queue = (struct gve_adminq_destroy_tx_queue) {
406 .queue_id = cpu_to_be32(queue_index),
407 };
408
409 err = gve_adminq_issue_cmd(priv, &cmd);
410 if (err)
411 return err;
412
413 return 0;
414 }
415
gve_adminq_destroy_tx_queues(struct gve_priv * priv,u32 num_queues)416 int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 num_queues)
417 {
418 int err;
419 int i;
420
421 for (i = 0; i < num_queues; i++) {
422 err = gve_adminq_destroy_tx_queue(priv, i);
423 if (err)
424 return err;
425 }
426
427 return gve_adminq_kick_and_wait(priv);
428 }
429
gve_adminq_destroy_rx_queue(struct gve_priv * priv,u32 queue_index)430 static int gve_adminq_destroy_rx_queue(struct gve_priv *priv, u32 queue_index)
431 {
432 union gve_adminq_command cmd;
433 int err;
434
435 memset(&cmd, 0, sizeof(cmd));
436 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_RX_QUEUE);
437 cmd.destroy_rx_queue = (struct gve_adminq_destroy_rx_queue) {
438 .queue_id = cpu_to_be32(queue_index),
439 };
440
441 err = gve_adminq_issue_cmd(priv, &cmd);
442 if (err)
443 return err;
444
445 return 0;
446 }
447
gve_adminq_destroy_rx_queues(struct gve_priv * priv,u32 num_queues)448 int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 num_queues)
449 {
450 int err;
451 int i;
452
453 for (i = 0; i < num_queues; i++) {
454 err = gve_adminq_destroy_rx_queue(priv, i);
455 if (err)
456 return err;
457 }
458
459 return gve_adminq_kick_and_wait(priv);
460 }
461
gve_adminq_describe_device(struct gve_priv * priv)462 int gve_adminq_describe_device(struct gve_priv *priv)
463 {
464 struct gve_device_descriptor *descriptor;
465 union gve_adminq_command cmd;
466 dma_addr_t descriptor_bus;
467 int err = 0;
468 u8 *mac;
469 u16 mtu;
470
471 memset(&cmd, 0, sizeof(cmd));
472 descriptor = dma_alloc_coherent(&priv->pdev->dev, PAGE_SIZE,
473 &descriptor_bus, GFP_KERNEL);
474 if (!descriptor)
475 return -ENOMEM;
476 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESCRIBE_DEVICE);
477 cmd.describe_device.device_descriptor_addr =
478 cpu_to_be64(descriptor_bus);
479 cmd.describe_device.device_descriptor_version =
480 cpu_to_be32(GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION);
481 cmd.describe_device.available_length = cpu_to_be32(PAGE_SIZE);
482
483 err = gve_adminq_execute_cmd(priv, &cmd);
484 if (err)
485 goto free_device_descriptor;
486
487 priv->tx_desc_cnt = be16_to_cpu(descriptor->tx_queue_entries);
488 if (priv->tx_desc_cnt * sizeof(priv->tx->desc[0]) < PAGE_SIZE) {
489 dev_err(&priv->pdev->dev, "Tx desc count %d too low\n", priv->tx_desc_cnt);
490 err = -EINVAL;
491 goto free_device_descriptor;
492 }
493 priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
494 if (priv->rx_desc_cnt * sizeof(priv->rx->desc.desc_ring[0])
495 < PAGE_SIZE ||
496 priv->rx_desc_cnt * sizeof(priv->rx->data.data_ring[0])
497 < PAGE_SIZE) {
498 dev_err(&priv->pdev->dev, "Rx desc count %d too low\n", priv->rx_desc_cnt);
499 err = -EINVAL;
500 goto free_device_descriptor;
501 }
502 priv->max_registered_pages =
503 be64_to_cpu(descriptor->max_registered_pages);
504 mtu = be16_to_cpu(descriptor->mtu);
505 if (mtu < ETH_MIN_MTU) {
506 dev_err(&priv->pdev->dev, "MTU %d below minimum MTU\n", mtu);
507 err = -EINVAL;
508 goto free_device_descriptor;
509 }
510 priv->dev->max_mtu = mtu;
511 priv->num_event_counters = be16_to_cpu(descriptor->counters);
512 ether_addr_copy(priv->dev->dev_addr, descriptor->mac);
513 mac = descriptor->mac;
514 dev_info(&priv->pdev->dev, "MAC addr: %pM\n", mac);
515 priv->tx_pages_per_qpl = be16_to_cpu(descriptor->tx_pages_per_qpl);
516 priv->rx_pages_per_qpl = be16_to_cpu(descriptor->rx_pages_per_qpl);
517 if (priv->rx_pages_per_qpl < priv->rx_desc_cnt) {
518 dev_err(&priv->pdev->dev, "rx_pages_per_qpl cannot be smaller than rx_desc_cnt, setting rx_desc_cnt down to %d.\n",
519 priv->rx_pages_per_qpl);
520 priv->rx_desc_cnt = priv->rx_pages_per_qpl;
521 }
522 priv->default_num_queues = be16_to_cpu(descriptor->default_num_queues);
523
524 free_device_descriptor:
525 dma_free_coherent(&priv->pdev->dev, sizeof(*descriptor), descriptor,
526 descriptor_bus);
527 return err;
528 }
529
gve_adminq_register_page_list(struct gve_priv * priv,struct gve_queue_page_list * qpl)530 int gve_adminq_register_page_list(struct gve_priv *priv,
531 struct gve_queue_page_list *qpl)
532 {
533 struct device *hdev = &priv->pdev->dev;
534 u32 num_entries = qpl->num_entries;
535 u32 size = num_entries * sizeof(qpl->page_buses[0]);
536 union gve_adminq_command cmd;
537 dma_addr_t page_list_bus;
538 __be64 *page_list;
539 int err;
540 int i;
541
542 memset(&cmd, 0, sizeof(cmd));
543 page_list = dma_alloc_coherent(hdev, size, &page_list_bus, GFP_KERNEL);
544 if (!page_list)
545 return -ENOMEM;
546
547 for (i = 0; i < num_entries; i++)
548 page_list[i] = cpu_to_be64(qpl->page_buses[i]);
549
550 cmd.opcode = cpu_to_be32(GVE_ADMINQ_REGISTER_PAGE_LIST);
551 cmd.reg_page_list = (struct gve_adminq_register_page_list) {
552 .page_list_id = cpu_to_be32(qpl->id),
553 .num_pages = cpu_to_be32(num_entries),
554 .page_address_list_addr = cpu_to_be64(page_list_bus),
555 };
556
557 err = gve_adminq_execute_cmd(priv, &cmd);
558 dma_free_coherent(hdev, size, page_list, page_list_bus);
559 return err;
560 }
561
gve_adminq_unregister_page_list(struct gve_priv * priv,u32 page_list_id)562 int gve_adminq_unregister_page_list(struct gve_priv *priv, u32 page_list_id)
563 {
564 union gve_adminq_command cmd;
565
566 memset(&cmd, 0, sizeof(cmd));
567 cmd.opcode = cpu_to_be32(GVE_ADMINQ_UNREGISTER_PAGE_LIST);
568 cmd.unreg_page_list = (struct gve_adminq_unregister_page_list) {
569 .page_list_id = cpu_to_be32(page_list_id),
570 };
571
572 return gve_adminq_execute_cmd(priv, &cmd);
573 }
574
gve_adminq_set_mtu(struct gve_priv * priv,u64 mtu)575 int gve_adminq_set_mtu(struct gve_priv *priv, u64 mtu)
576 {
577 union gve_adminq_command cmd;
578
579 memset(&cmd, 0, sizeof(cmd));
580 cmd.opcode = cpu_to_be32(GVE_ADMINQ_SET_DRIVER_PARAMETER);
581 cmd.set_driver_param = (struct gve_adminq_set_driver_parameter) {
582 .parameter_type = cpu_to_be32(GVE_SET_PARAM_MTU),
583 .parameter_value = cpu_to_be64(mtu),
584 };
585
586 return gve_adminq_execute_cmd(priv, &cmd);
587 }
588
gve_adminq_report_stats(struct gve_priv * priv,u64 stats_report_len,dma_addr_t stats_report_addr,u64 interval)589 int gve_adminq_report_stats(struct gve_priv *priv, u64 stats_report_len,
590 dma_addr_t stats_report_addr, u64 interval)
591 {
592 union gve_adminq_command cmd;
593
594 memset(&cmd, 0, sizeof(cmd));
595 cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_STATS);
596 cmd.report_stats = (struct gve_adminq_report_stats) {
597 .stats_report_len = cpu_to_be64(stats_report_len),
598 .stats_report_addr = cpu_to_be64(stats_report_addr),
599 .interval = cpu_to_be64(interval),
600 };
601
602 return gve_adminq_execute_cmd(priv, &cmd);
603 }
604
gve_adminq_report_link_speed(struct gve_priv * priv)605 int gve_adminq_report_link_speed(struct gve_priv *priv)
606 {
607 union gve_adminq_command gvnic_cmd;
608 dma_addr_t link_speed_region_bus;
609 __be64 *link_speed_region;
610 int err;
611
612 link_speed_region =
613 dma_alloc_coherent(&priv->pdev->dev, sizeof(*link_speed_region),
614 &link_speed_region_bus, GFP_KERNEL);
615
616 if (!link_speed_region)
617 return -ENOMEM;
618
619 memset(&gvnic_cmd, 0, sizeof(gvnic_cmd));
620 gvnic_cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_LINK_SPEED);
621 gvnic_cmd.report_link_speed.link_speed_address =
622 cpu_to_be64(link_speed_region_bus);
623
624 err = gve_adminq_execute_cmd(priv, &gvnic_cmd);
625
626 priv->link_speed = be64_to_cpu(*link_speed_region);
627 dma_free_coherent(&priv->pdev->dev, sizeof(*link_speed_region), link_speed_region,
628 link_speed_region_bus);
629 return err;
630 }
631