1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for HDA DSP code loader
16 */
17
18 #include <linux/firmware.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include <sound/sof.h>
22 #include "../ops.h"
23 #include "hda.h"
24
25 #define HDA_FW_BOOT_ATTEMPTS 3
26 #define HDA_CL_STREAM_FORMAT 0x40
27
cl_stream_prepare(struct snd_sof_dev * sdev,unsigned int format,unsigned int size,struct snd_dma_buffer * dmab,int direction)28 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
29 unsigned int size, struct snd_dma_buffer *dmab,
30 int direction)
31 {
32 struct hdac_ext_stream *dsp_stream;
33 struct hdac_stream *hstream;
34 struct pci_dev *pci = to_pci_dev(sdev->dev);
35 int ret;
36
37 dsp_stream = hda_dsp_stream_get(sdev, direction);
38
39 if (!dsp_stream) {
40 dev_err(sdev->dev, "error: no stream available\n");
41 return ERR_PTR(-ENODEV);
42 }
43 hstream = &dsp_stream->hstream;
44 hstream->substream = NULL;
45
46 /* allocate DMA buffer */
47 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
48 if (ret < 0) {
49 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
50 goto out_put;
51 }
52
53 hstream->period_bytes = 0;/* initialize period_bytes */
54 hstream->format_val = format;
55 hstream->bufsize = size;
56
57 if (direction == SNDRV_PCM_STREAM_CAPTURE) {
58 ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL);
59 if (ret < 0) {
60 dev_err(sdev->dev, "error: iccmax stream prepare failed: %x\n", ret);
61 goto out_free;
62 }
63 } else {
64 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
65 if (ret < 0) {
66 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
67 goto out_free;
68 }
69 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
70 }
71
72 return dsp_stream;
73
74 out_free:
75 snd_dma_free_pages(dmab);
76 out_put:
77 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
78 return ERR_PTR(ret);
79 }
80
81 /*
82 * first boot sequence has some extra steps.
83 * power on all host managed cores and only unstall/run the boot core to boot the
84 * DSP then turn off all non boot cores (if any) is powered on.
85 */
cl_dsp_init(struct snd_sof_dev * sdev,int stream_tag)86 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
87 {
88 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
89 const struct sof_intel_dsp_desc *chip = hda->desc;
90 unsigned int status;
91 int ret;
92 int i;
93
94 /* step 1: power up corex */
95 ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
96 if (ret < 0) {
97 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
98 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
99 goto err;
100 }
101
102 /* DSP is powered up, set all SSPs to slave mode */
103 for (i = 0; i < chip->ssp_count; i++) {
104 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
105 chip->ssp_base_offset
106 + i * SSP_DEV_MEM_SIZE
107 + SSP_SSC1_OFFSET,
108 SSP_SET_SLAVE,
109 SSP_SET_SLAVE);
110 }
111
112 /* step 2: purge FW request */
113 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
114 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
115 ((stream_tag - 1) << 9)));
116
117 /* step 3: unset core 0 reset state & unstall/run core 0 */
118 ret = hda_dsp_core_run(sdev, chip->init_core_mask);
119 if (ret < 0) {
120 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
121 dev_err(sdev->dev,
122 "error: dsp core start failed %d\n", ret);
123 ret = -EIO;
124 goto err;
125 }
126
127 /* step 4: wait for IPC DONE bit from ROM */
128 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
129 chip->ipc_ack, status,
130 ((status & chip->ipc_ack_mask)
131 == chip->ipc_ack_mask),
132 HDA_DSP_REG_POLL_INTERVAL_US,
133 HDA_DSP_INIT_TIMEOUT_US);
134
135 if (ret < 0) {
136 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
137 dev_err(sdev->dev,
138 "error: %s: timeout for HIPCIE done\n",
139 __func__);
140 goto err;
141 }
142
143 /* set DONE bit to clear the reply IPC message */
144 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
145 chip->ipc_ack,
146 chip->ipc_ack_mask,
147 chip->ipc_ack_mask);
148
149 /* step 5: power down corex */
150 ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
151 if (ret < 0) {
152 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
153 dev_err(sdev->dev,
154 "error: dsp core x power down failed\n");
155 goto err;
156 }
157
158 /* step 6: enable IPC interrupts */
159 hda_dsp_ipc_int_enable(sdev);
160
161 /* step 7: wait for ROM init */
162 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
163 HDA_DSP_SRAM_REG_ROM_STATUS, status,
164 ((status & HDA_DSP_ROM_STS_MASK)
165 == HDA_DSP_ROM_INIT),
166 HDA_DSP_REG_POLL_INTERVAL_US,
167 chip->rom_init_timeout *
168 USEC_PER_MSEC);
169 if (!ret)
170 return 0;
171
172 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
173 dev_err(sdev->dev,
174 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
175 __func__);
176
177 err:
178 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
179 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
180
181 return ret;
182 }
183
cl_trigger(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream,int cmd)184 static int cl_trigger(struct snd_sof_dev *sdev,
185 struct hdac_ext_stream *stream, int cmd)
186 {
187 struct hdac_stream *hstream = &stream->hstream;
188 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
189
190 /* code loader is special case that reuses stream ops */
191 switch (cmd) {
192 case SNDRV_PCM_TRIGGER_START:
193 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
194 1 << hstream->index,
195 1 << hstream->index);
196
197 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
198 sd_offset,
199 SOF_HDA_SD_CTL_DMA_START |
200 SOF_HDA_CL_DMA_SD_INT_MASK,
201 SOF_HDA_SD_CTL_DMA_START |
202 SOF_HDA_CL_DMA_SD_INT_MASK);
203
204 hstream->running = true;
205 return 0;
206 default:
207 return hda_dsp_stream_trigger(sdev, stream, cmd);
208 }
209 }
210
cl_cleanup(struct snd_sof_dev * sdev,struct snd_dma_buffer * dmab,struct hdac_ext_stream * stream)211 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
212 struct hdac_ext_stream *stream)
213 {
214 struct hdac_stream *hstream = &stream->hstream;
215 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
216 int ret = 0;
217
218 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
219 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
220 else
221 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
222 SOF_HDA_SD_CTL_DMA_START, 0);
223
224 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
225 hstream->running = 0;
226 hstream->substream = NULL;
227
228 /* reset BDL address */
229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
230 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
231 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
232 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
233
234 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
235 snd_dma_free_pages(dmab);
236 dmab->area = NULL;
237 hstream->bufsize = 0;
238 hstream->format_val = 0;
239
240 return ret;
241 }
242
cl_copy_fw(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream)243 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
244 {
245 unsigned int reg;
246 int ret, status;
247
248 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
249 if (ret < 0) {
250 dev_err(sdev->dev, "error: DMA trigger start failed\n");
251 return ret;
252 }
253
254 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
255 HDA_DSP_SRAM_REG_ROM_STATUS, reg,
256 ((reg & HDA_DSP_ROM_STS_MASK)
257 == HDA_DSP_ROM_FW_ENTERED),
258 HDA_DSP_REG_POLL_INTERVAL_US,
259 HDA_DSP_BASEFW_TIMEOUT_US);
260
261 /*
262 * even in case of errors we still need to stop the DMAs,
263 * but we return the initial error should the DMA stop also fail
264 */
265
266 if (status < 0) {
267 dev_err(sdev->dev,
268 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
269 __func__);
270 }
271
272 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
273 if (ret < 0) {
274 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
275 if (!status)
276 status = ret;
277 }
278
279 return status;
280 }
281
hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev * sdev)282 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
283 {
284 struct snd_sof_pdata *plat_data = sdev->pdata;
285 struct hdac_ext_stream *iccmax_stream;
286 struct hdac_bus *bus = sof_to_bus(sdev);
287 struct firmware stripped_firmware;
288 int ret, ret1;
289 u8 original_gb;
290
291 /* save the original LTRP guardband value */
292 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
293
294 if (plat_data->fw->size <= plat_data->fw_offset) {
295 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
296 return -EINVAL;
297 }
298
299 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
300
301 /* prepare capture stream for ICCMAX */
302 iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
303 &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
304 if (IS_ERR(iccmax_stream)) {
305 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
306 return PTR_ERR(iccmax_stream);
307 }
308
309 ret = hda_dsp_cl_boot_firmware(sdev);
310
311 /*
312 * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
313 * If the cleanup also fails, we return the initial error
314 */
315 ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream);
316 if (ret1 < 0) {
317 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
318
319 /* set return value to indicate cleanup failure */
320 if (!ret)
321 ret = ret1;
322 }
323
324 /* restore the original guardband value after FW boot */
325 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
326
327 return ret;
328 }
329
hda_dsp_cl_boot_firmware(struct snd_sof_dev * sdev)330 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
331 {
332 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
333 struct snd_sof_pdata *plat_data = sdev->pdata;
334 const struct sof_dev_desc *desc = plat_data->desc;
335 const struct sof_intel_dsp_desc *chip_info;
336 struct hdac_ext_stream *stream;
337 struct firmware stripped_firmware;
338 int ret, ret1, i;
339
340 chip_info = desc->chip_info;
341
342 if (plat_data->fw->size <= plat_data->fw_offset) {
343 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
344 return -EINVAL;
345 }
346
347 stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
348 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
349
350 /* init for booting wait */
351 init_waitqueue_head(&sdev->boot_wait);
352
353 /* prepare DMA for code loader stream */
354 stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
355 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
356 if (IS_ERR(stream)) {
357 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
358 return PTR_ERR(stream);
359 }
360
361 memcpy(sdev->dmab.area, stripped_firmware.data,
362 stripped_firmware.size);
363
364 /* try ROM init a few times before giving up */
365 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
366 dev_dbg(sdev->dev,
367 "Attempting iteration %d of Core En/ROM load...\n", i);
368
369 hda->boot_iteration = i + 1;
370 ret = cl_dsp_init(sdev, stream->hstream.stream_tag);
371
372 /* don't retry anymore if successful */
373 if (!ret)
374 break;
375 }
376
377 if (i == HDA_FW_BOOT_ATTEMPTS) {
378 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
379 i, ret);
380 dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
381 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
382 HDA_DSP_SRAM_REG_ROM_ERROR),
383 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
384 HDA_DSP_SRAM_REG_ROM_STATUS));
385 goto cleanup;
386 }
387
388 /*
389 * When a SoundWire link is in clock stop state, a Slave
390 * device may trigger in-band wakes for events such as jack
391 * insertion or acoustic event detection. This event will lead
392 * to a WAKEEN interrupt, handled by the PCI device and routed
393 * to PME if the PCI device is in D3. The resume function in
394 * audio PCI driver will be invoked by ACPI for PME event and
395 * initialize the device and process WAKEEN interrupt.
396 *
397 * The WAKEEN interrupt should be processed ASAP to prevent an
398 * interrupt flood, otherwise other interrupts, such IPC,
399 * cannot work normally. The WAKEEN is handled after the ROM
400 * is initialized successfully, which ensures power rails are
401 * enabled before accessing the SoundWire SHIM registers
402 */
403 if (!sdev->first_boot)
404 hda_sdw_process_wakeen(sdev);
405
406 /*
407 * at this point DSP ROM has been initialized and
408 * should be ready for code loading and firmware boot
409 */
410 ret = cl_copy_fw(sdev, stream);
411 if (!ret)
412 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
413 else
414 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
415
416 cleanup:
417 /*
418 * Perform codeloader stream cleanup.
419 * This should be done even if firmware loading fails.
420 * If the cleanup also fails, we return the initial error
421 */
422 ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
423 if (ret1 < 0) {
424 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
425
426 /* set return value to indicate cleanup failure */
427 if (!ret)
428 ret = ret1;
429 }
430
431 /*
432 * return primary core id if both fw copy
433 * and stream clean up are successful
434 */
435 if (!ret)
436 return chip_info->init_core_mask;
437
438 /* dump dsp registers and disable DSP upon error */
439 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
440
441 /* disable DSP */
442 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
443 SOF_HDA_REG_PP_PPCTL,
444 SOF_HDA_PPCTL_GPROCEN, 0);
445 return ret;
446 }
447
448 /* pre fw run operations */
hda_dsp_pre_fw_run(struct snd_sof_dev * sdev)449 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
450 {
451 /* disable clock gating and power gating */
452 return hda_dsp_ctrl_clock_power_gating(sdev, false);
453 }
454
455 /* post fw run operations */
hda_dsp_post_fw_run(struct snd_sof_dev * sdev)456 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
457 {
458 int ret;
459
460 if (sdev->first_boot) {
461 ret = hda_sdw_startup(sdev);
462 if (ret < 0) {
463 dev_err(sdev->dev,
464 "error: could not startup SoundWire links\n");
465 return ret;
466 }
467 }
468
469 hda_sdw_int_enable(sdev, true);
470
471 /* re-enable clock gating and power gating */
472 return hda_dsp_ctrl_clock_power_gating(sdev, true);
473 }
474