1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/platform_device.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/uverbs_ioctl.h>
36 #include "hns_roce_device.h"
37 #include "hns_roce_cmd.h"
38 #include "hns_roce_hem.h"
39 #include <rdma/hns-abi.h>
40 #include "hns_roce_common.h"
41
alloc_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)42 static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
43 {
44 struct hns_roce_cmd_mailbox *mailbox;
45 struct hns_roce_cq_table *cq_table;
46 struct ib_device *ibdev = &hr_dev->ib_dev;
47 u64 mtts[MTT_MIN_COUNT] = { 0 };
48 dma_addr_t dma_handle;
49 int ret;
50
51 ret = hns_roce_mtr_find(hr_dev, &hr_cq->mtr, 0, mtts, ARRAY_SIZE(mtts),
52 &dma_handle);
53 if (!ret) {
54 ibdev_err(ibdev, "failed to find CQ mtr, ret = %d.\n", ret);
55 return -EINVAL;
56 }
57
58 cq_table = &hr_dev->cq_table;
59 ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn);
60 if (ret) {
61 ibdev_err(ibdev, "failed to alloc CQ bitmap, ret = %d.\n", ret);
62 return ret;
63 }
64
65 /* Get CQC memory HEM(Hardware Entry Memory) table */
66 ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
67 if (ret) {
68 ibdev_err(ibdev, "failed to get CQ(0x%lx) context, ret = %d.\n",
69 hr_cq->cqn, ret);
70 goto err_out;
71 }
72
73 ret = xa_err(xa_store(&cq_table->array, hr_cq->cqn, hr_cq, GFP_KERNEL));
74 if (ret) {
75 ibdev_err(ibdev, "failed to xa_store CQ, ret = %d.\n", ret);
76 goto err_put;
77 }
78
79 /* Allocate mailbox memory */
80 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
81 if (IS_ERR(mailbox)) {
82 ret = PTR_ERR(mailbox);
83 goto err_xa;
84 }
85
86 hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle);
87
88 /* Send mailbox to hw */
89 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 0,
90 HNS_ROCE_CMD_CREATE_CQC, HNS_ROCE_CMD_TIMEOUT_MSECS);
91 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
92 if (ret) {
93 ibdev_err(ibdev,
94 "failed to send create cmd for CQ(0x%lx), ret = %d.\n",
95 hr_cq->cqn, ret);
96 goto err_xa;
97 }
98
99 hr_cq->cons_index = 0;
100 hr_cq->arm_sn = 1;
101
102 atomic_set(&hr_cq->refcount, 1);
103 init_completion(&hr_cq->free);
104
105 return 0;
106
107 err_xa:
108 xa_erase(&cq_table->array, hr_cq->cqn);
109
110 err_put:
111 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
112
113 err_out:
114 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
115 return ret;
116 }
117
free_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)118 static void free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
119 {
120 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
121 struct device *dev = hr_dev->dev;
122 int ret;
123
124 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, hr_cq->cqn, 1,
125 HNS_ROCE_CMD_DESTROY_CQC,
126 HNS_ROCE_CMD_TIMEOUT_MSECS);
127 if (ret)
128 dev_err(dev, "DESTROY_CQ failed (%d) for CQN %06lx\n", ret,
129 hr_cq->cqn);
130
131 xa_erase(&cq_table->array, hr_cq->cqn);
132
133 /* Waiting interrupt process procedure carried out */
134 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
135
136 /* wait for all interrupt processed */
137 if (atomic_dec_and_test(&hr_cq->refcount))
138 complete(&hr_cq->free);
139 wait_for_completion(&hr_cq->free);
140
141 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
142 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
143 }
144
alloc_cq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,struct ib_udata * udata,unsigned long addr)145 static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
146 struct ib_udata *udata, unsigned long addr)
147 {
148 struct ib_device *ibdev = &hr_dev->ib_dev;
149 struct hns_roce_buf_attr buf_attr = {};
150 int ret;
151
152 buf_attr.page_shift = hr_dev->caps.cqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
153 buf_attr.region[0].size = hr_cq->cq_depth * hr_cq->cqe_size;
154 buf_attr.region[0].hopnum = hr_dev->caps.cqe_hop_num;
155 buf_attr.region_count = 1;
156 buf_attr.fixed_page = true;
157
158 ret = hns_roce_mtr_create(hr_dev, &hr_cq->mtr, &buf_attr,
159 hr_dev->caps.cqe_ba_pg_sz + HNS_HW_PAGE_SHIFT,
160 udata, addr);
161 if (ret)
162 ibdev_err(ibdev, "failed to alloc CQ mtr, ret = %d.\n", ret);
163
164 return ret;
165 }
166
free_cq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)167 static void free_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
168 {
169 hns_roce_mtr_destroy(hr_dev, &hr_cq->mtr);
170 }
171
alloc_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,struct ib_udata * udata,unsigned long addr,struct hns_roce_ib_create_cq_resp * resp)172 static int alloc_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
173 struct ib_udata *udata, unsigned long addr,
174 struct hns_roce_ib_create_cq_resp *resp)
175 {
176 bool has_db = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB;
177 struct hns_roce_ucontext *uctx;
178 int err;
179
180 if (udata) {
181 if (has_db &&
182 udata->outlen >= offsetofend(typeof(*resp), cap_flags)) {
183 uctx = rdma_udata_to_drv_context(udata,
184 struct hns_roce_ucontext, ibucontext);
185 err = hns_roce_db_map_user(uctx, udata, addr,
186 &hr_cq->db);
187 if (err)
188 return err;
189 hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
190 resp->cap_flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
191 }
192 } else {
193 if (has_db) {
194 err = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1);
195 if (err)
196 return err;
197 hr_cq->set_ci_db = hr_cq->db.db_record;
198 *hr_cq->set_ci_db = 0;
199 hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
200 }
201 hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset +
202 DB_REG_OFFSET * hr_dev->priv_uar.index;
203 }
204
205 return 0;
206 }
207
free_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,struct ib_udata * udata)208 static void free_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
209 struct ib_udata *udata)
210 {
211 struct hns_roce_ucontext *uctx;
212
213 if (!(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB))
214 return;
215
216 hr_cq->flags &= ~HNS_ROCE_CQ_FLAG_RECORD_DB;
217 if (udata) {
218 uctx = rdma_udata_to_drv_context(udata,
219 struct hns_roce_ucontext,
220 ibucontext);
221 hns_roce_db_unmap_user(uctx, &hr_cq->db);
222 } else {
223 hns_roce_free_db(hr_dev, &hr_cq->db);
224 }
225 }
226
set_cqe_size(struct hns_roce_cq * hr_cq,struct ib_udata * udata,struct hns_roce_ib_create_cq * ucmd)227 static void set_cqe_size(struct hns_roce_cq *hr_cq, struct ib_udata *udata,
228 struct hns_roce_ib_create_cq *ucmd)
229 {
230 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
231
232 if (udata) {
233 if (udata->inlen >= offsetofend(typeof(*ucmd), cqe_size))
234 hr_cq->cqe_size = ucmd->cqe_size;
235 else
236 hr_cq->cqe_size = HNS_ROCE_V2_CQE_SIZE;
237 } else {
238 hr_cq->cqe_size = hr_dev->caps.cqe_sz;
239 }
240 }
241
hns_roce_create_cq(struct ib_cq * ib_cq,const struct ib_cq_init_attr * attr,struct ib_udata * udata)242 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
243 struct ib_udata *udata)
244 {
245 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
246 struct hns_roce_ib_create_cq_resp resp = {};
247 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
248 struct ib_device *ibdev = &hr_dev->ib_dev;
249 struct hns_roce_ib_create_cq ucmd = {};
250 int vector = attr->comp_vector;
251 u32 cq_entries = attr->cqe;
252 int ret;
253
254 if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
255 ibdev_err(ibdev, "failed to check CQ count %u, max = %u.\n",
256 cq_entries, hr_dev->caps.max_cqes);
257 return -EINVAL;
258 }
259
260 if (vector >= hr_dev->caps.num_comp_vectors) {
261 ibdev_err(ibdev, "failed to check CQ vector = %d, max = %d.\n",
262 vector, hr_dev->caps.num_comp_vectors);
263 return -EINVAL;
264 }
265
266 cq_entries = max(cq_entries, hr_dev->caps.min_cqes);
267 cq_entries = roundup_pow_of_two(cq_entries);
268 hr_cq->ib_cq.cqe = cq_entries - 1; /* used as cqe index */
269 hr_cq->cq_depth = cq_entries;
270 hr_cq->vector = vector;
271 spin_lock_init(&hr_cq->lock);
272 INIT_LIST_HEAD(&hr_cq->sq_list);
273 INIT_LIST_HEAD(&hr_cq->rq_list);
274
275 if (udata) {
276 ret = ib_copy_from_udata(&ucmd, udata,
277 min(udata->inlen, sizeof(ucmd)));
278 if (ret) {
279 ibdev_err(ibdev, "failed to copy CQ udata, ret = %d.\n",
280 ret);
281 return ret;
282 }
283 }
284
285 set_cqe_size(hr_cq, udata, &ucmd);
286
287 ret = alloc_cq_buf(hr_dev, hr_cq, udata, ucmd.buf_addr);
288 if (ret) {
289 ibdev_err(ibdev, "failed to alloc CQ buf, ret = %d.\n", ret);
290 return ret;
291 }
292
293 ret = alloc_cq_db(hr_dev, hr_cq, udata, ucmd.db_addr, &resp);
294 if (ret) {
295 ibdev_err(ibdev, "failed to alloc CQ db, ret = %d.\n", ret);
296 goto err_cq_buf;
297 }
298
299 ret = alloc_cqc(hr_dev, hr_cq);
300 if (ret) {
301 ibdev_err(ibdev,
302 "failed to alloc CQ context, ret = %d.\n", ret);
303 goto err_cq_db;
304 }
305
306 /*
307 * For the QP created by kernel space, tptr value should be initialized
308 * to zero; For the QP created by user space, it will cause synchronous
309 * problems if tptr is set to zero here, so we initialize it in user
310 * space.
311 */
312 if (!udata && hr_cq->tptr_addr)
313 *hr_cq->tptr_addr = 0;
314
315 if (udata) {
316 resp.cqn = hr_cq->cqn;
317 ret = ib_copy_to_udata(udata, &resp,
318 min(udata->outlen, sizeof(resp)));
319 if (ret)
320 goto err_cqc;
321 }
322
323 return 0;
324
325 err_cqc:
326 free_cqc(hr_dev, hr_cq);
327 err_cq_db:
328 free_cq_db(hr_dev, hr_cq, udata);
329 err_cq_buf:
330 free_cq_buf(hr_dev, hr_cq);
331 return ret;
332 }
333
hns_roce_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)334 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
335 {
336 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
337 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
338
339 if (hr_dev->hw->destroy_cq)
340 hr_dev->hw->destroy_cq(ib_cq, udata);
341
342 free_cq_buf(hr_dev, hr_cq);
343 free_cq_db(hr_dev, hr_cq, udata);
344 free_cqc(hr_dev, hr_cq);
345 return 0;
346 }
347
hns_roce_cq_completion(struct hns_roce_dev * hr_dev,u32 cqn)348 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
349 {
350 struct hns_roce_cq *hr_cq;
351 struct ib_cq *ibcq;
352
353 hr_cq = xa_load(&hr_dev->cq_table.array,
354 cqn & (hr_dev->caps.num_cqs - 1));
355 if (!hr_cq) {
356 dev_warn(hr_dev->dev, "Completion event for bogus CQ 0x%06x\n",
357 cqn);
358 return;
359 }
360
361 ++hr_cq->arm_sn;
362 ibcq = &hr_cq->ib_cq;
363 if (ibcq->comp_handler)
364 ibcq->comp_handler(ibcq, ibcq->cq_context);
365 }
366
hns_roce_cq_event(struct hns_roce_dev * hr_dev,u32 cqn,int event_type)367 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
368 {
369 struct device *dev = hr_dev->dev;
370 struct hns_roce_cq *hr_cq;
371 struct ib_event event;
372 struct ib_cq *ibcq;
373
374 hr_cq = xa_load(&hr_dev->cq_table.array,
375 cqn & (hr_dev->caps.num_cqs - 1));
376 if (!hr_cq) {
377 dev_warn(dev, "Async event for bogus CQ 0x%06x\n", cqn);
378 return;
379 }
380
381 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
382 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
383 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
384 dev_err(dev, "Unexpected event type 0x%x on CQ 0x%06x\n",
385 event_type, cqn);
386 return;
387 }
388
389 atomic_inc(&hr_cq->refcount);
390
391 ibcq = &hr_cq->ib_cq;
392 if (ibcq->event_handler) {
393 event.device = ibcq->device;
394 event.element.cq = ibcq;
395 event.event = IB_EVENT_CQ_ERR;
396 ibcq->event_handler(&event, ibcq->cq_context);
397 }
398
399 if (atomic_dec_and_test(&hr_cq->refcount))
400 complete(&hr_cq->free);
401 }
402
hns_roce_init_cq_table(struct hns_roce_dev * hr_dev)403 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
404 {
405 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
406
407 xa_init(&cq_table->array);
408
409 return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs,
410 hr_dev->caps.num_cqs - 1,
411 hr_dev->caps.reserved_cqs, 0);
412 }
413
hns_roce_cleanup_cq_table(struct hns_roce_dev * hr_dev)414 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev)
415 {
416 hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap);
417 }
418