1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bsearch.h>
13 #include <linux/kvm_host.h>
14 #include <linux/mm.h>
15 #include <linux/printk.h>
16 #include <linux/uaccess.h>
17
18 #include <asm/cacheflush.h>
19 #include <asm/cputype.h>
20 #include <asm/debug-monitors.h>
21 #include <asm/esr.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_coproc.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
29
30 #include <trace/events/kvm.h>
31
32 #include "sys_regs.h"
33
34 #include "trace.h"
35
36 /*
37 * All of this file is extremely similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)47 static bool read_from_write_only(struct kvm_vcpu *vcpu,
48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
50 {
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55 }
56
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)57 static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60 {
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65 }
66
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)67 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
68 {
69 /*
70 * System registers listed in the switch are not saved on every
71 * exit from the guest but are only saved on vcpu_put.
72 *
73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
74 * should never be listed below, because the guest cannot modify its
75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
76 * thread when emulating cross-VCPU communication.
77 */
78 switch (reg) {
79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
97 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
98 case PAR_EL1: *val = read_sysreg_par(); break;
99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
102 default: return false;
103 }
104
105 return true;
106 }
107
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)108 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
109 {
110 /*
111 * System registers listed in the switch are not restored on every
112 * entry to the guest but are only restored on vcpu_load.
113 *
114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
115 * should never be listed below, because the MPIDR should only be set
116 * once, before running the VCPU, and never changed later.
117 */
118 switch (reg) {
119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
121 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
122 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
123 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
124 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
125 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
126 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
127 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
128 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
129 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
130 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
131 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
132 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
133 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
134 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
135 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
136 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
137 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
142 default: return false;
143 }
144
145 return true;
146 }
147
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)148 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
149 {
150 u64 val = 0x8badf00d8badf00d;
151
152 if (vcpu->arch.sysregs_loaded_on_cpu &&
153 __vcpu_read_sys_reg_from_cpu(reg, &val))
154 return val;
155
156 return __vcpu_sys_reg(vcpu, reg);
157 }
158
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)159 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
160 {
161 if (vcpu->arch.sysregs_loaded_on_cpu &&
162 __vcpu_write_sys_reg_to_cpu(val, reg))
163 return;
164
165 __vcpu_sys_reg(vcpu, reg) = val;
166 }
167
168 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
169 static u32 cache_levels;
170
171 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
172 #define CSSELR_MAX 12
173
174 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(u32 csselr)175 static u32 get_ccsidr(u32 csselr)
176 {
177 u32 ccsidr;
178
179 /* Make sure noone else changes CSSELR during this! */
180 local_irq_disable();
181 write_sysreg(csselr, csselr_el1);
182 isb();
183 ccsidr = read_sysreg(ccsidr_el1);
184 local_irq_enable();
185
186 return ccsidr;
187 }
188
189 /*
190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
191 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)192 static bool access_dcsw(struct kvm_vcpu *vcpu,
193 struct sys_reg_params *p,
194 const struct sys_reg_desc *r)
195 {
196 if (!p->is_write)
197 return read_from_write_only(vcpu, p, r);
198
199 /*
200 * Only track S/W ops if we don't have FWB. It still indicates
201 * that the guest is a bit broken (S/W operations should only
202 * be done by firmware, knowing that there is only a single
203 * CPU left in the system, and certainly not from non-secure
204 * software).
205 */
206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
207 kvm_set_way_flush(vcpu);
208
209 return true;
210 }
211
212 /*
213 * Generic accessor for VM registers. Only called as long as HCR_TVM
214 * is set. If the guest enables the MMU, we stop trapping the VM
215 * sys_regs and leave it in complete control of the caches.
216 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)217 static bool access_vm_reg(struct kvm_vcpu *vcpu,
218 struct sys_reg_params *p,
219 const struct sys_reg_desc *r)
220 {
221 bool was_enabled = vcpu_has_cache_enabled(vcpu);
222 u64 val;
223 int reg = r->reg;
224
225 BUG_ON(!p->is_write);
226
227 /* See the 32bit mapping in kvm_host.h */
228 if (p->is_aarch32)
229 reg = r->reg / 2;
230
231 if (!p->is_aarch32 || !p->is_32bit) {
232 val = p->regval;
233 } else {
234 val = vcpu_read_sys_reg(vcpu, reg);
235 if (r->reg % 2)
236 val = (p->regval << 32) | (u64)lower_32_bits(val);
237 else
238 val = ((u64)upper_32_bits(val) << 32) |
239 lower_32_bits(p->regval);
240 }
241 vcpu_write_sys_reg(vcpu, val, reg);
242
243 kvm_toggle_cache(vcpu, was_enabled);
244 return true;
245 }
246
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)247 static bool access_actlr(struct kvm_vcpu *vcpu,
248 struct sys_reg_params *p,
249 const struct sys_reg_desc *r)
250 {
251 if (p->is_write)
252 return ignore_write(vcpu, p);
253
254 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
255
256 if (p->is_aarch32) {
257 if (r->Op2 & 2)
258 p->regval = upper_32_bits(p->regval);
259 else
260 p->regval = lower_32_bits(p->regval);
261 }
262
263 return true;
264 }
265
266 /*
267 * Trap handler for the GICv3 SGI generation system register.
268 * Forward the request to the VGIC emulation.
269 * The cp15_64 code makes sure this automatically works
270 * for both AArch64 and AArch32 accesses.
271 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)272 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
273 struct sys_reg_params *p,
274 const struct sys_reg_desc *r)
275 {
276 bool g1;
277
278 if (!p->is_write)
279 return read_from_write_only(vcpu, p, r);
280
281 /*
282 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
284 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
285 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
286 * group.
287 */
288 if (p->is_aarch32) {
289 switch (p->Op1) {
290 default: /* Keep GCC quiet */
291 case 0: /* ICC_SGI1R */
292 g1 = true;
293 break;
294 case 1: /* ICC_ASGI1R */
295 case 2: /* ICC_SGI0R */
296 g1 = false;
297 break;
298 }
299 } else {
300 switch (p->Op2) {
301 default: /* Keep GCC quiet */
302 case 5: /* ICC_SGI1R_EL1 */
303 g1 = true;
304 break;
305 case 6: /* ICC_ASGI1R_EL1 */
306 case 7: /* ICC_SGI0R_EL1 */
307 g1 = false;
308 break;
309 }
310 }
311
312 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
313
314 return true;
315 }
316
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)317 static bool access_gic_sre(struct kvm_vcpu *vcpu,
318 struct sys_reg_params *p,
319 const struct sys_reg_desc *r)
320 {
321 if (p->is_write)
322 return ignore_write(vcpu, p);
323
324 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
325 return true;
326 }
327
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)328 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
329 struct sys_reg_params *p,
330 const struct sys_reg_desc *r)
331 {
332 if (p->is_write)
333 return ignore_write(vcpu, p);
334 else
335 return read_zero(vcpu, p);
336 }
337
338 /*
339 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
340 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
341 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
342 * treat it separately.
343 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)344 static bool trap_loregion(struct kvm_vcpu *vcpu,
345 struct sys_reg_params *p,
346 const struct sys_reg_desc *r)
347 {
348 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
350 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
351
352 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
353 kvm_inject_undefined(vcpu);
354 return false;
355 }
356
357 if (p->is_write && sr == SYS_LORID_EL1)
358 return write_to_read_only(vcpu, p, r);
359
360 return trap_raz_wi(vcpu, p, r);
361 }
362
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)363 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
364 struct sys_reg_params *p,
365 const struct sys_reg_desc *r)
366 {
367 if (p->is_write) {
368 return ignore_write(vcpu, p);
369 } else {
370 p->regval = (1 << 3);
371 return true;
372 }
373 }
374
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)375 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
376 struct sys_reg_params *p,
377 const struct sys_reg_desc *r)
378 {
379 if (p->is_write) {
380 return ignore_write(vcpu, p);
381 } else {
382 p->regval = read_sysreg(dbgauthstatus_el1);
383 return true;
384 }
385 }
386
387 /*
388 * We want to avoid world-switching all the DBG registers all the
389 * time:
390 *
391 * - If we've touched any debug register, it is likely that we're
392 * going to touch more of them. It then makes sense to disable the
393 * traps and start doing the save/restore dance
394 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
395 * then mandatory to save/restore the registers, as the guest
396 * depends on them.
397 *
398 * For this, we use a DIRTY bit, indicating the guest has modified the
399 * debug registers, used as follow:
400 *
401 * On guest entry:
402 * - If the dirty bit is set (because we're coming back from trapping),
403 * disable the traps, save host registers, restore guest registers.
404 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
405 * set the dirty bit, disable the traps, save host registers,
406 * restore guest registers.
407 * - Otherwise, enable the traps
408 *
409 * On guest exit:
410 * - If the dirty bit is set, save guest registers, restore host
411 * registers and clear the dirty bit. This ensure that the host can
412 * now use the debug registers.
413 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)414 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
415 struct sys_reg_params *p,
416 const struct sys_reg_desc *r)
417 {
418 if (p->is_write) {
419 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
420 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
421 } else {
422 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
423 }
424
425 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
426
427 return true;
428 }
429
430 /*
431 * reg_to_dbg/dbg_to_reg
432 *
433 * A 32 bit write to a debug register leave top bits alone
434 * A 32 bit read from a debug register only returns the bottom bits
435 *
436 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
437 * hyp.S code switches between host and guest values in future.
438 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,u64 * dbg_reg)439 static void reg_to_dbg(struct kvm_vcpu *vcpu,
440 struct sys_reg_params *p,
441 u64 *dbg_reg)
442 {
443 u64 val = p->regval;
444
445 if (p->is_32bit) {
446 val &= 0xffffffffUL;
447 val |= ((*dbg_reg >> 32) << 32);
448 }
449
450 *dbg_reg = val;
451 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
452 }
453
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,u64 * dbg_reg)454 static void dbg_to_reg(struct kvm_vcpu *vcpu,
455 struct sys_reg_params *p,
456 u64 *dbg_reg)
457 {
458 p->regval = *dbg_reg;
459 if (p->is_32bit)
460 p->regval &= 0xffffffffUL;
461 }
462
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)463 static bool trap_bvr(struct kvm_vcpu *vcpu,
464 struct sys_reg_params *p,
465 const struct sys_reg_desc *rd)
466 {
467 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
468
469 if (p->is_write)
470 reg_to_dbg(vcpu, p, dbg_reg);
471 else
472 dbg_to_reg(vcpu, p, dbg_reg);
473
474 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
475
476 return true;
477 }
478
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)479 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
480 const struct kvm_one_reg *reg, void __user *uaddr)
481 {
482 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
483
484 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
485 return -EFAULT;
486 return 0;
487 }
488
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)489 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
490 const struct kvm_one_reg *reg, void __user *uaddr)
491 {
492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
493
494 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
495 return -EFAULT;
496 return 0;
497 }
498
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)499 static void reset_bvr(struct kvm_vcpu *vcpu,
500 const struct sys_reg_desc *rd)
501 {
502 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
503 }
504
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)505 static bool trap_bcr(struct kvm_vcpu *vcpu,
506 struct sys_reg_params *p,
507 const struct sys_reg_desc *rd)
508 {
509 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
510
511 if (p->is_write)
512 reg_to_dbg(vcpu, p, dbg_reg);
513 else
514 dbg_to_reg(vcpu, p, dbg_reg);
515
516 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
517
518 return true;
519 }
520
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)521 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
522 const struct kvm_one_reg *reg, void __user *uaddr)
523 {
524 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
525
526 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
527 return -EFAULT;
528
529 return 0;
530 }
531
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)532 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
533 const struct kvm_one_reg *reg, void __user *uaddr)
534 {
535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
536
537 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
538 return -EFAULT;
539 return 0;
540 }
541
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)542 static void reset_bcr(struct kvm_vcpu *vcpu,
543 const struct sys_reg_desc *rd)
544 {
545 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
546 }
547
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)548 static bool trap_wvr(struct kvm_vcpu *vcpu,
549 struct sys_reg_params *p,
550 const struct sys_reg_desc *rd)
551 {
552 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
553
554 if (p->is_write)
555 reg_to_dbg(vcpu, p, dbg_reg);
556 else
557 dbg_to_reg(vcpu, p, dbg_reg);
558
559 trace_trap_reg(__func__, rd->CRm, p->is_write,
560 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
561
562 return true;
563 }
564
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)565 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
566 const struct kvm_one_reg *reg, void __user *uaddr)
567 {
568 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
569
570 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
571 return -EFAULT;
572 return 0;
573 }
574
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)575 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
576 const struct kvm_one_reg *reg, void __user *uaddr)
577 {
578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
579
580 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
581 return -EFAULT;
582 return 0;
583 }
584
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)585 static void reset_wvr(struct kvm_vcpu *vcpu,
586 const struct sys_reg_desc *rd)
587 {
588 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
589 }
590
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)591 static bool trap_wcr(struct kvm_vcpu *vcpu,
592 struct sys_reg_params *p,
593 const struct sys_reg_desc *rd)
594 {
595 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
596
597 if (p->is_write)
598 reg_to_dbg(vcpu, p, dbg_reg);
599 else
600 dbg_to_reg(vcpu, p, dbg_reg);
601
602 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
603
604 return true;
605 }
606
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)607 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
608 const struct kvm_one_reg *reg, void __user *uaddr)
609 {
610 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
611
612 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
613 return -EFAULT;
614 return 0;
615 }
616
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)617 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
618 const struct kvm_one_reg *reg, void __user *uaddr)
619 {
620 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
621
622 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
623 return -EFAULT;
624 return 0;
625 }
626
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)627 static void reset_wcr(struct kvm_vcpu *vcpu,
628 const struct sys_reg_desc *rd)
629 {
630 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
631 }
632
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)633 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
634 {
635 u64 amair = read_sysreg(amair_el1);
636 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
637 }
638
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)639 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
640 {
641 u64 actlr = read_sysreg(actlr_el1);
642 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
643 }
644
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)645 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
646 {
647 u64 mpidr;
648
649 /*
650 * Map the vcpu_id into the first three affinity level fields of
651 * the MPIDR. We limit the number of VCPUs in level 0 due to a
652 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
653 * of the GICv3 to be able to address each CPU directly when
654 * sending IPIs.
655 */
656 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
657 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
658 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
659 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
660 }
661
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)662 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
663 {
664 u64 pmcr, val;
665
666 /* No PMU available, PMCR_EL0 may UNDEF... */
667 if (!kvm_arm_support_pmu_v3())
668 return;
669
670 pmcr = read_sysreg(pmcr_el0);
671 /*
672 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
673 * except PMCR.E resetting to zero.
674 */
675 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
676 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
677 if (!system_supports_32bit_el0())
678 val |= ARMV8_PMU_PMCR_LC;
679 __vcpu_sys_reg(vcpu, r->reg) = val;
680 }
681
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)682 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
683 {
684 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
685 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
686
687 if (!enabled)
688 kvm_inject_undefined(vcpu);
689
690 return !enabled;
691 }
692
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)693 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
694 {
695 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
696 }
697
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)698 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
699 {
700 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
701 }
702
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)703 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
704 {
705 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
706 }
707
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)708 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
709 {
710 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
711 }
712
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)713 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
714 const struct sys_reg_desc *r)
715 {
716 u64 val;
717
718 if (!kvm_arm_pmu_v3_ready(vcpu))
719 return trap_raz_wi(vcpu, p, r);
720
721 if (pmu_access_el0_disabled(vcpu))
722 return false;
723
724 if (p->is_write) {
725 /* Only update writeable bits of PMCR */
726 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
727 val &= ~ARMV8_PMU_PMCR_MASK;
728 val |= p->regval & ARMV8_PMU_PMCR_MASK;
729 if (!system_supports_32bit_el0())
730 val |= ARMV8_PMU_PMCR_LC;
731 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
732 kvm_pmu_handle_pmcr(vcpu, val);
733 kvm_vcpu_pmu_restore_guest(vcpu);
734 } else {
735 /* PMCR.P & PMCR.C are RAZ */
736 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
737 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
738 p->regval = val;
739 }
740
741 return true;
742 }
743
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)744 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
745 const struct sys_reg_desc *r)
746 {
747 if (!kvm_arm_pmu_v3_ready(vcpu))
748 return trap_raz_wi(vcpu, p, r);
749
750 if (pmu_access_event_counter_el0_disabled(vcpu))
751 return false;
752
753 if (p->is_write)
754 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
755 else
756 /* return PMSELR.SEL field */
757 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
758 & ARMV8_PMU_COUNTER_MASK;
759
760 return true;
761 }
762
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)763 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
764 const struct sys_reg_desc *r)
765 {
766 u64 pmceid;
767
768 if (!kvm_arm_pmu_v3_ready(vcpu))
769 return trap_raz_wi(vcpu, p, r);
770
771 BUG_ON(p->is_write);
772
773 if (pmu_access_el0_disabled(vcpu))
774 return false;
775
776 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
777
778 p->regval = pmceid;
779
780 return true;
781 }
782
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)783 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
784 {
785 u64 pmcr, val;
786
787 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
788 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
789 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
790 kvm_inject_undefined(vcpu);
791 return false;
792 }
793
794 return true;
795 }
796
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)797 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
798 struct sys_reg_params *p,
799 const struct sys_reg_desc *r)
800 {
801 u64 idx;
802
803 if (!kvm_arm_pmu_v3_ready(vcpu))
804 return trap_raz_wi(vcpu, p, r);
805
806 if (r->CRn == 9 && r->CRm == 13) {
807 if (r->Op2 == 2) {
808 /* PMXEVCNTR_EL0 */
809 if (pmu_access_event_counter_el0_disabled(vcpu))
810 return false;
811
812 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
813 & ARMV8_PMU_COUNTER_MASK;
814 } else if (r->Op2 == 0) {
815 /* PMCCNTR_EL0 */
816 if (pmu_access_cycle_counter_el0_disabled(vcpu))
817 return false;
818
819 idx = ARMV8_PMU_CYCLE_IDX;
820 } else {
821 return false;
822 }
823 } else if (r->CRn == 0 && r->CRm == 9) {
824 /* PMCCNTR */
825 if (pmu_access_event_counter_el0_disabled(vcpu))
826 return false;
827
828 idx = ARMV8_PMU_CYCLE_IDX;
829 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
830 /* PMEVCNTRn_EL0 */
831 if (pmu_access_event_counter_el0_disabled(vcpu))
832 return false;
833
834 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
835 } else {
836 return false;
837 }
838
839 if (!pmu_counter_idx_valid(vcpu, idx))
840 return false;
841
842 if (p->is_write) {
843 if (pmu_access_el0_disabled(vcpu))
844 return false;
845
846 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
847 } else {
848 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
849 }
850
851 return true;
852 }
853
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)854 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
855 const struct sys_reg_desc *r)
856 {
857 u64 idx, reg;
858
859 if (!kvm_arm_pmu_v3_ready(vcpu))
860 return trap_raz_wi(vcpu, p, r);
861
862 if (pmu_access_el0_disabled(vcpu))
863 return false;
864
865 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
866 /* PMXEVTYPER_EL0 */
867 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
868 reg = PMEVTYPER0_EL0 + idx;
869 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
870 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
871 if (idx == ARMV8_PMU_CYCLE_IDX)
872 reg = PMCCFILTR_EL0;
873 else
874 /* PMEVTYPERn_EL0 */
875 reg = PMEVTYPER0_EL0 + idx;
876 } else {
877 BUG();
878 }
879
880 if (!pmu_counter_idx_valid(vcpu, idx))
881 return false;
882
883 if (p->is_write) {
884 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
885 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
886 kvm_vcpu_pmu_restore_guest(vcpu);
887 } else {
888 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
889 }
890
891 return true;
892 }
893
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)894 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
895 const struct sys_reg_desc *r)
896 {
897 u64 val, mask;
898
899 if (!kvm_arm_pmu_v3_ready(vcpu))
900 return trap_raz_wi(vcpu, p, r);
901
902 if (pmu_access_el0_disabled(vcpu))
903 return false;
904
905 mask = kvm_pmu_valid_counter_mask(vcpu);
906 if (p->is_write) {
907 val = p->regval & mask;
908 if (r->Op2 & 0x1) {
909 /* accessing PMCNTENSET_EL0 */
910 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
911 kvm_pmu_enable_counter_mask(vcpu, val);
912 kvm_vcpu_pmu_restore_guest(vcpu);
913 } else {
914 /* accessing PMCNTENCLR_EL0 */
915 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
916 kvm_pmu_disable_counter_mask(vcpu, val);
917 }
918 } else {
919 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
920 }
921
922 return true;
923 }
924
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)925 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
926 const struct sys_reg_desc *r)
927 {
928 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
929
930 if (!kvm_arm_pmu_v3_ready(vcpu))
931 return trap_raz_wi(vcpu, p, r);
932
933 if (!vcpu_mode_priv(vcpu)) {
934 kvm_inject_undefined(vcpu);
935 return false;
936 }
937
938 if (p->is_write) {
939 u64 val = p->regval & mask;
940
941 if (r->Op2 & 0x1)
942 /* accessing PMINTENSET_EL1 */
943 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
944 else
945 /* accessing PMINTENCLR_EL1 */
946 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
947 } else {
948 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
949 }
950
951 return true;
952 }
953
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)954 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
955 const struct sys_reg_desc *r)
956 {
957 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
958
959 if (!kvm_arm_pmu_v3_ready(vcpu))
960 return trap_raz_wi(vcpu, p, r);
961
962 if (pmu_access_el0_disabled(vcpu))
963 return false;
964
965 if (p->is_write) {
966 if (r->CRm & 0x2)
967 /* accessing PMOVSSET_EL0 */
968 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
969 else
970 /* accessing PMOVSCLR_EL0 */
971 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
972 } else {
973 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
974 }
975
976 return true;
977 }
978
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)979 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
980 const struct sys_reg_desc *r)
981 {
982 u64 mask;
983
984 if (!kvm_arm_pmu_v3_ready(vcpu))
985 return trap_raz_wi(vcpu, p, r);
986
987 if (!p->is_write)
988 return read_from_write_only(vcpu, p, r);
989
990 if (pmu_write_swinc_el0_disabled(vcpu))
991 return false;
992
993 mask = kvm_pmu_valid_counter_mask(vcpu);
994 kvm_pmu_software_increment(vcpu, p->regval & mask);
995 return true;
996 }
997
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)998 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
999 const struct sys_reg_desc *r)
1000 {
1001 if (!kvm_arm_pmu_v3_ready(vcpu))
1002 return trap_raz_wi(vcpu, p, r);
1003
1004 if (p->is_write) {
1005 if (!vcpu_mode_priv(vcpu)) {
1006 kvm_inject_undefined(vcpu);
1007 return false;
1008 }
1009
1010 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1011 p->regval & ARMV8_PMU_USERENR_MASK;
1012 } else {
1013 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1014 & ARMV8_PMU_USERENR_MASK;
1015 }
1016
1017 return true;
1018 }
1019
1020 #define reg_to_encoding(x) \
1021 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1022 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
1023
1024 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1025 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1026 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1027 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1028 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1029 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1030 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1031 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1032 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1033 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1034
1035 /* Macro to expand the PMEVCNTRn_EL0 register */
1036 #define PMU_PMEVCNTR_EL0(n) \
1037 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
1038 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1039
1040 /* Macro to expand the PMEVTYPERn_EL0 register */
1041 #define PMU_PMEVTYPER_EL0(n) \
1042 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
1043 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1044
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1045 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1046 const struct sys_reg_desc *r)
1047 {
1048 kvm_inject_undefined(vcpu);
1049
1050 return false;
1051 }
1052
1053 /* Macro to expand the AMU counter and type registers*/
1054 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1055 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1056 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1057 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1058
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1059 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1060 const struct sys_reg_desc *rd)
1061 {
1062 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1063 }
1064
1065 /*
1066 * If we land here on a PtrAuth access, that is because we didn't
1067 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1068 * way this happens is when the guest does not have PtrAuth support
1069 * enabled.
1070 */
1071 #define __PTRAUTH_KEY(k) \
1072 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1073 .visibility = ptrauth_visibility}
1074
1075 #define PTRAUTH_KEY(k) \
1076 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1077 __PTRAUTH_KEY(k ## KEYHI_EL1)
1078
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1079 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1080 struct sys_reg_params *p,
1081 const struct sys_reg_desc *r)
1082 {
1083 enum kvm_arch_timers tmr;
1084 enum kvm_arch_timer_regs treg;
1085 u64 reg = reg_to_encoding(r);
1086
1087 switch (reg) {
1088 case SYS_CNTP_TVAL_EL0:
1089 case SYS_AARCH32_CNTP_TVAL:
1090 tmr = TIMER_PTIMER;
1091 treg = TIMER_REG_TVAL;
1092 break;
1093 case SYS_CNTP_CTL_EL0:
1094 case SYS_AARCH32_CNTP_CTL:
1095 tmr = TIMER_PTIMER;
1096 treg = TIMER_REG_CTL;
1097 break;
1098 case SYS_CNTP_CVAL_EL0:
1099 case SYS_AARCH32_CNTP_CVAL:
1100 tmr = TIMER_PTIMER;
1101 treg = TIMER_REG_CVAL;
1102 break;
1103 default:
1104 BUG();
1105 }
1106
1107 if (p->is_write)
1108 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1109 else
1110 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1111
1112 return true;
1113 }
1114
1115 /* Read a sanitised cpufeature ID register by sys_reg_desc */
read_id_reg(const struct kvm_vcpu * vcpu,struct sys_reg_desc const * r,bool raz)1116 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1117 struct sys_reg_desc const *r, bool raz)
1118 {
1119 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1120 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1121 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1122
1123 if (id == SYS_ID_AA64PFR0_EL1) {
1124 if (!vcpu_has_sve(vcpu))
1125 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1126 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
1127 val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
1128 val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
1129 } else if (id == SYS_ID_AA64PFR1_EL1) {
1130 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
1131 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
1132 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1133 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1134 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1135 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
1136 } else if (id == SYS_ID_AA64DFR0_EL1) {
1137 /* Limit guests to PMUv3 for ARMv8.1 */
1138 val = cpuid_feature_cap_perfmon_field(val,
1139 ID_AA64DFR0_PMUVER_SHIFT,
1140 ID_AA64DFR0_PMUVER_8_1);
1141 } else if (id == SYS_ID_DFR0_EL1) {
1142 /* Limit guests to PMUv3 for ARMv8.1 */
1143 val = cpuid_feature_cap_perfmon_field(val,
1144 ID_DFR0_PERFMON_SHIFT,
1145 ID_DFR0_PERFMON_8_1);
1146 }
1147
1148 return val;
1149 }
1150
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1151 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1152 const struct sys_reg_desc *r)
1153 {
1154 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1155 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1156
1157 switch (id) {
1158 case SYS_ID_AA64ZFR0_EL1:
1159 if (!vcpu_has_sve(vcpu))
1160 return REG_RAZ;
1161 break;
1162 }
1163
1164 return 0;
1165 }
1166
1167 /* cpufeature ID register access trap handlers */
1168
__access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r,bool raz)1169 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1170 struct sys_reg_params *p,
1171 const struct sys_reg_desc *r,
1172 bool raz)
1173 {
1174 if (p->is_write)
1175 return write_to_read_only(vcpu, p, r);
1176
1177 p->regval = read_id_reg(vcpu, r, raz);
1178 return true;
1179 }
1180
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1181 static bool access_id_reg(struct kvm_vcpu *vcpu,
1182 struct sys_reg_params *p,
1183 const struct sys_reg_desc *r)
1184 {
1185 bool raz = sysreg_visible_as_raz(vcpu, r);
1186
1187 return __access_id_reg(vcpu, p, r, raz);
1188 }
1189
access_raz_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1190 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1191 struct sys_reg_params *p,
1192 const struct sys_reg_desc *r)
1193 {
1194 return __access_id_reg(vcpu, p, r, true);
1195 }
1196
1197 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1198 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1199 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1200
1201 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1202 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1203 const struct sys_reg_desc *rd)
1204 {
1205 if (vcpu_has_sve(vcpu))
1206 return 0;
1207
1208 return REG_HIDDEN;
1209 }
1210
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1211 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1212 const struct sys_reg_desc *rd,
1213 const struct kvm_one_reg *reg, void __user *uaddr)
1214 {
1215 const u64 id = sys_reg_to_index(rd);
1216 int err;
1217 u64 val;
1218 u8 csv2;
1219
1220 err = reg_from_user(&val, uaddr, id);
1221 if (err)
1222 return err;
1223
1224 /*
1225 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1226 * it doesn't promise more than what is actually provided (the
1227 * guest could otherwise be covered in ectoplasmic residue).
1228 */
1229 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1230 if (csv2 > 1 ||
1231 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1232 return -EINVAL;
1233
1234 /* We can only differ with CSV2, and anything else is an error */
1235 val ^= read_id_reg(vcpu, rd, false);
1236 val &= ~(0xFUL << ID_AA64PFR0_CSV2_SHIFT);
1237 if (val)
1238 return -EINVAL;
1239
1240 vcpu->kvm->arch.pfr0_csv2 = csv2;
1241
1242 return 0;
1243 }
1244
1245 /*
1246 * cpufeature ID register user accessors
1247 *
1248 * For now, these registers are immutable for userspace, so no values
1249 * are stored, and for set_id_reg() we don't allow the effective value
1250 * to be changed.
1251 */
__get_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1252 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1253 const struct sys_reg_desc *rd, void __user *uaddr,
1254 bool raz)
1255 {
1256 const u64 id = sys_reg_to_index(rd);
1257 const u64 val = read_id_reg(vcpu, rd, raz);
1258
1259 return reg_to_user(uaddr, &val, id);
1260 }
1261
__set_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1262 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1263 const struct sys_reg_desc *rd, void __user *uaddr,
1264 bool raz)
1265 {
1266 const u64 id = sys_reg_to_index(rd);
1267 int err;
1268 u64 val;
1269
1270 err = reg_from_user(&val, uaddr, id);
1271 if (err)
1272 return err;
1273
1274 /* This is what we mean by invariant: you can't change it. */
1275 if (val != read_id_reg(vcpu, rd, raz))
1276 return -EINVAL;
1277
1278 return 0;
1279 }
1280
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1281 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1282 const struct kvm_one_reg *reg, void __user *uaddr)
1283 {
1284 bool raz = sysreg_visible_as_raz(vcpu, rd);
1285
1286 return __get_id_reg(vcpu, rd, uaddr, raz);
1287 }
1288
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1289 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1290 const struct kvm_one_reg *reg, void __user *uaddr)
1291 {
1292 bool raz = sysreg_visible_as_raz(vcpu, rd);
1293
1294 return __set_id_reg(vcpu, rd, uaddr, raz);
1295 }
1296
get_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1297 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1298 const struct kvm_one_reg *reg, void __user *uaddr)
1299 {
1300 return __get_id_reg(vcpu, rd, uaddr, true);
1301 }
1302
set_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1303 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1304 const struct kvm_one_reg *reg, void __user *uaddr)
1305 {
1306 return __set_id_reg(vcpu, rd, uaddr, true);
1307 }
1308
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1309 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1310 const struct sys_reg_desc *r)
1311 {
1312 if (p->is_write)
1313 return write_to_read_only(vcpu, p, r);
1314
1315 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1316 return true;
1317 }
1318
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1319 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1320 const struct sys_reg_desc *r)
1321 {
1322 if (p->is_write)
1323 return write_to_read_only(vcpu, p, r);
1324
1325 p->regval = read_sysreg(clidr_el1);
1326 return true;
1327 }
1328
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1329 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1330 const struct sys_reg_desc *r)
1331 {
1332 int reg = r->reg;
1333
1334 /* See the 32bit mapping in kvm_host.h */
1335 if (p->is_aarch32)
1336 reg = r->reg / 2;
1337
1338 if (p->is_write)
1339 vcpu_write_sys_reg(vcpu, p->regval, reg);
1340 else
1341 p->regval = vcpu_read_sys_reg(vcpu, reg);
1342 return true;
1343 }
1344
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1345 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1346 const struct sys_reg_desc *r)
1347 {
1348 u32 csselr;
1349
1350 if (p->is_write)
1351 return write_to_read_only(vcpu, p, r);
1352
1353 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1354 p->regval = get_ccsidr(csselr);
1355
1356 /*
1357 * Guests should not be doing cache operations by set/way at all, and
1358 * for this reason, we trap them and attempt to infer the intent, so
1359 * that we can flush the entire guest's address space at the appropriate
1360 * time.
1361 * To prevent this trapping from causing performance problems, let's
1362 * expose the geometry of all data and unified caches (which are
1363 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1364 * [If guests should attempt to infer aliasing properties from the
1365 * geometry (which is not permitted by the architecture), they would
1366 * only do so for virtually indexed caches.]
1367 */
1368 if (!(csselr & 1)) // data or unified cache
1369 p->regval &= ~GENMASK(27, 3);
1370 return true;
1371 }
1372
1373 /* sys_reg_desc initialiser for known cpufeature ID registers */
1374 #define ID_SANITISED(name) { \
1375 SYS_DESC(SYS_##name), \
1376 .access = access_id_reg, \
1377 .get_user = get_id_reg, \
1378 .set_user = set_id_reg, \
1379 .visibility = id_visibility, \
1380 }
1381
1382 /*
1383 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1384 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1385 * (1 <= crm < 8, 0 <= Op2 < 8).
1386 */
1387 #define ID_UNALLOCATED(crm, op2) { \
1388 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1389 .access = access_raz_id_reg, \
1390 .get_user = get_raz_id_reg, \
1391 .set_user = set_raz_id_reg, \
1392 }
1393
1394 /*
1395 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1396 * For now, these are exposed just like unallocated ID regs: they appear
1397 * RAZ for the guest.
1398 */
1399 #define ID_HIDDEN(name) { \
1400 SYS_DESC(SYS_##name), \
1401 .access = access_raz_id_reg, \
1402 .get_user = get_raz_id_reg, \
1403 .set_user = set_raz_id_reg, \
1404 }
1405
1406 /*
1407 * Architected system registers.
1408 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1409 *
1410 * Debug handling: We do trap most, if not all debug related system
1411 * registers. The implementation is good enough to ensure that a guest
1412 * can use these with minimal performance degradation. The drawback is
1413 * that we don't implement any of the external debug, none of the
1414 * OSlock protocol. This should be revisited if we ever encounter a
1415 * more demanding guest...
1416 */
1417 static const struct sys_reg_desc sys_reg_descs[] = {
1418 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1419 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1420 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1421
1422 DBG_BCR_BVR_WCR_WVR_EL1(0),
1423 DBG_BCR_BVR_WCR_WVR_EL1(1),
1424 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1425 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1426 DBG_BCR_BVR_WCR_WVR_EL1(2),
1427 DBG_BCR_BVR_WCR_WVR_EL1(3),
1428 DBG_BCR_BVR_WCR_WVR_EL1(4),
1429 DBG_BCR_BVR_WCR_WVR_EL1(5),
1430 DBG_BCR_BVR_WCR_WVR_EL1(6),
1431 DBG_BCR_BVR_WCR_WVR_EL1(7),
1432 DBG_BCR_BVR_WCR_WVR_EL1(8),
1433 DBG_BCR_BVR_WCR_WVR_EL1(9),
1434 DBG_BCR_BVR_WCR_WVR_EL1(10),
1435 DBG_BCR_BVR_WCR_WVR_EL1(11),
1436 DBG_BCR_BVR_WCR_WVR_EL1(12),
1437 DBG_BCR_BVR_WCR_WVR_EL1(13),
1438 DBG_BCR_BVR_WCR_WVR_EL1(14),
1439 DBG_BCR_BVR_WCR_WVR_EL1(15),
1440
1441 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1442 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1443 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1444 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1445 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1446 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1447 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1448 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1449
1450 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1451 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1452 // DBGDTR[TR]X_EL0 share the same encoding
1453 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1454
1455 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1456
1457 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1458
1459 /*
1460 * ID regs: all ID_SANITISED() entries here must have corresponding
1461 * entries in arm64_ftr_regs[].
1462 */
1463
1464 /* AArch64 mappings of the AArch32 ID registers */
1465 /* CRm=1 */
1466 ID_SANITISED(ID_PFR0_EL1),
1467 ID_SANITISED(ID_PFR1_EL1),
1468 ID_SANITISED(ID_DFR0_EL1),
1469 ID_HIDDEN(ID_AFR0_EL1),
1470 ID_SANITISED(ID_MMFR0_EL1),
1471 ID_SANITISED(ID_MMFR1_EL1),
1472 ID_SANITISED(ID_MMFR2_EL1),
1473 ID_SANITISED(ID_MMFR3_EL1),
1474
1475 /* CRm=2 */
1476 ID_SANITISED(ID_ISAR0_EL1),
1477 ID_SANITISED(ID_ISAR1_EL1),
1478 ID_SANITISED(ID_ISAR2_EL1),
1479 ID_SANITISED(ID_ISAR3_EL1),
1480 ID_SANITISED(ID_ISAR4_EL1),
1481 ID_SANITISED(ID_ISAR5_EL1),
1482 ID_SANITISED(ID_MMFR4_EL1),
1483 ID_SANITISED(ID_ISAR6_EL1),
1484
1485 /* CRm=3 */
1486 ID_SANITISED(MVFR0_EL1),
1487 ID_SANITISED(MVFR1_EL1),
1488 ID_SANITISED(MVFR2_EL1),
1489 ID_UNALLOCATED(3,3),
1490 ID_SANITISED(ID_PFR2_EL1),
1491 ID_HIDDEN(ID_DFR1_EL1),
1492 ID_SANITISED(ID_MMFR5_EL1),
1493 ID_UNALLOCATED(3,7),
1494
1495 /* AArch64 ID registers */
1496 /* CRm=4 */
1497 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1498 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1499 ID_SANITISED(ID_AA64PFR1_EL1),
1500 ID_UNALLOCATED(4,2),
1501 ID_UNALLOCATED(4,3),
1502 ID_SANITISED(ID_AA64ZFR0_EL1),
1503 ID_UNALLOCATED(4,5),
1504 ID_UNALLOCATED(4,6),
1505 ID_UNALLOCATED(4,7),
1506
1507 /* CRm=5 */
1508 ID_SANITISED(ID_AA64DFR0_EL1),
1509 ID_SANITISED(ID_AA64DFR1_EL1),
1510 ID_UNALLOCATED(5,2),
1511 ID_UNALLOCATED(5,3),
1512 ID_HIDDEN(ID_AA64AFR0_EL1),
1513 ID_HIDDEN(ID_AA64AFR1_EL1),
1514 ID_UNALLOCATED(5,6),
1515 ID_UNALLOCATED(5,7),
1516
1517 /* CRm=6 */
1518 ID_SANITISED(ID_AA64ISAR0_EL1),
1519 ID_SANITISED(ID_AA64ISAR1_EL1),
1520 ID_SANITISED(ID_AA64ISAR2_EL1),
1521 ID_UNALLOCATED(6,3),
1522 ID_UNALLOCATED(6,4),
1523 ID_UNALLOCATED(6,5),
1524 ID_UNALLOCATED(6,6),
1525 ID_UNALLOCATED(6,7),
1526
1527 /* CRm=7 */
1528 ID_SANITISED(ID_AA64MMFR0_EL1),
1529 ID_SANITISED(ID_AA64MMFR1_EL1),
1530 ID_SANITISED(ID_AA64MMFR2_EL1),
1531 ID_UNALLOCATED(7,3),
1532 ID_UNALLOCATED(7,4),
1533 ID_UNALLOCATED(7,5),
1534 ID_UNALLOCATED(7,6),
1535 ID_UNALLOCATED(7,7),
1536
1537 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1538 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1539 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1540
1541 { SYS_DESC(SYS_RGSR_EL1), undef_access },
1542 { SYS_DESC(SYS_GCR_EL1), undef_access },
1543
1544 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1545 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1546 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1547 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1548
1549 PTRAUTH_KEY(APIA),
1550 PTRAUTH_KEY(APIB),
1551 PTRAUTH_KEY(APDA),
1552 PTRAUTH_KEY(APDB),
1553 PTRAUTH_KEY(APGA),
1554
1555 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1556 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1557 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1558
1559 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1560 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1561 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1562 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1563 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1564 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1565 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1566 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1567
1568 { SYS_DESC(SYS_TFSR_EL1), undef_access },
1569 { SYS_DESC(SYS_TFSRE0_EL1), undef_access },
1570
1571 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1572 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1573
1574 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1575 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1576
1577 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1578 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1579
1580 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1581 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1582 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1583 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1584 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1585
1586 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1587 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1588
1589 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1590 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1591 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1592 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1593 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1594 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1595 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1596 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1597 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1598 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1599 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1600 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1601
1602 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1603 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1604
1605 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1606
1607 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1608
1609 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1610 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1611 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1612 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1613
1614 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1615 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1616 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1617 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1618 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1619 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1620 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1621 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1622 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1623 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1624 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1625 /*
1626 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1627 * in 32bit mode. Here we choose to reset it as zero for consistency.
1628 */
1629 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1630 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1631
1632 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1633 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1634
1635 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1636
1637 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1638 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1639 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1640 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1641 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1642 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1643 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1644 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1645 AMU_AMEVCNTR0_EL0(0),
1646 AMU_AMEVCNTR0_EL0(1),
1647 AMU_AMEVCNTR0_EL0(2),
1648 AMU_AMEVCNTR0_EL0(3),
1649 AMU_AMEVCNTR0_EL0(4),
1650 AMU_AMEVCNTR0_EL0(5),
1651 AMU_AMEVCNTR0_EL0(6),
1652 AMU_AMEVCNTR0_EL0(7),
1653 AMU_AMEVCNTR0_EL0(8),
1654 AMU_AMEVCNTR0_EL0(9),
1655 AMU_AMEVCNTR0_EL0(10),
1656 AMU_AMEVCNTR0_EL0(11),
1657 AMU_AMEVCNTR0_EL0(12),
1658 AMU_AMEVCNTR0_EL0(13),
1659 AMU_AMEVCNTR0_EL0(14),
1660 AMU_AMEVCNTR0_EL0(15),
1661 AMU_AMEVTYPER0_EL0(0),
1662 AMU_AMEVTYPER0_EL0(1),
1663 AMU_AMEVTYPER0_EL0(2),
1664 AMU_AMEVTYPER0_EL0(3),
1665 AMU_AMEVTYPER0_EL0(4),
1666 AMU_AMEVTYPER0_EL0(5),
1667 AMU_AMEVTYPER0_EL0(6),
1668 AMU_AMEVTYPER0_EL0(7),
1669 AMU_AMEVTYPER0_EL0(8),
1670 AMU_AMEVTYPER0_EL0(9),
1671 AMU_AMEVTYPER0_EL0(10),
1672 AMU_AMEVTYPER0_EL0(11),
1673 AMU_AMEVTYPER0_EL0(12),
1674 AMU_AMEVTYPER0_EL0(13),
1675 AMU_AMEVTYPER0_EL0(14),
1676 AMU_AMEVTYPER0_EL0(15),
1677 AMU_AMEVCNTR1_EL0(0),
1678 AMU_AMEVCNTR1_EL0(1),
1679 AMU_AMEVCNTR1_EL0(2),
1680 AMU_AMEVCNTR1_EL0(3),
1681 AMU_AMEVCNTR1_EL0(4),
1682 AMU_AMEVCNTR1_EL0(5),
1683 AMU_AMEVCNTR1_EL0(6),
1684 AMU_AMEVCNTR1_EL0(7),
1685 AMU_AMEVCNTR1_EL0(8),
1686 AMU_AMEVCNTR1_EL0(9),
1687 AMU_AMEVCNTR1_EL0(10),
1688 AMU_AMEVCNTR1_EL0(11),
1689 AMU_AMEVCNTR1_EL0(12),
1690 AMU_AMEVCNTR1_EL0(13),
1691 AMU_AMEVCNTR1_EL0(14),
1692 AMU_AMEVCNTR1_EL0(15),
1693 AMU_AMEVTYPER1_EL0(0),
1694 AMU_AMEVTYPER1_EL0(1),
1695 AMU_AMEVTYPER1_EL0(2),
1696 AMU_AMEVTYPER1_EL0(3),
1697 AMU_AMEVTYPER1_EL0(4),
1698 AMU_AMEVTYPER1_EL0(5),
1699 AMU_AMEVTYPER1_EL0(6),
1700 AMU_AMEVTYPER1_EL0(7),
1701 AMU_AMEVTYPER1_EL0(8),
1702 AMU_AMEVTYPER1_EL0(9),
1703 AMU_AMEVTYPER1_EL0(10),
1704 AMU_AMEVTYPER1_EL0(11),
1705 AMU_AMEVTYPER1_EL0(12),
1706 AMU_AMEVTYPER1_EL0(13),
1707 AMU_AMEVTYPER1_EL0(14),
1708 AMU_AMEVTYPER1_EL0(15),
1709
1710 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1711 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1712 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1713
1714 /* PMEVCNTRn_EL0 */
1715 PMU_PMEVCNTR_EL0(0),
1716 PMU_PMEVCNTR_EL0(1),
1717 PMU_PMEVCNTR_EL0(2),
1718 PMU_PMEVCNTR_EL0(3),
1719 PMU_PMEVCNTR_EL0(4),
1720 PMU_PMEVCNTR_EL0(5),
1721 PMU_PMEVCNTR_EL0(6),
1722 PMU_PMEVCNTR_EL0(7),
1723 PMU_PMEVCNTR_EL0(8),
1724 PMU_PMEVCNTR_EL0(9),
1725 PMU_PMEVCNTR_EL0(10),
1726 PMU_PMEVCNTR_EL0(11),
1727 PMU_PMEVCNTR_EL0(12),
1728 PMU_PMEVCNTR_EL0(13),
1729 PMU_PMEVCNTR_EL0(14),
1730 PMU_PMEVCNTR_EL0(15),
1731 PMU_PMEVCNTR_EL0(16),
1732 PMU_PMEVCNTR_EL0(17),
1733 PMU_PMEVCNTR_EL0(18),
1734 PMU_PMEVCNTR_EL0(19),
1735 PMU_PMEVCNTR_EL0(20),
1736 PMU_PMEVCNTR_EL0(21),
1737 PMU_PMEVCNTR_EL0(22),
1738 PMU_PMEVCNTR_EL0(23),
1739 PMU_PMEVCNTR_EL0(24),
1740 PMU_PMEVCNTR_EL0(25),
1741 PMU_PMEVCNTR_EL0(26),
1742 PMU_PMEVCNTR_EL0(27),
1743 PMU_PMEVCNTR_EL0(28),
1744 PMU_PMEVCNTR_EL0(29),
1745 PMU_PMEVCNTR_EL0(30),
1746 /* PMEVTYPERn_EL0 */
1747 PMU_PMEVTYPER_EL0(0),
1748 PMU_PMEVTYPER_EL0(1),
1749 PMU_PMEVTYPER_EL0(2),
1750 PMU_PMEVTYPER_EL0(3),
1751 PMU_PMEVTYPER_EL0(4),
1752 PMU_PMEVTYPER_EL0(5),
1753 PMU_PMEVTYPER_EL0(6),
1754 PMU_PMEVTYPER_EL0(7),
1755 PMU_PMEVTYPER_EL0(8),
1756 PMU_PMEVTYPER_EL0(9),
1757 PMU_PMEVTYPER_EL0(10),
1758 PMU_PMEVTYPER_EL0(11),
1759 PMU_PMEVTYPER_EL0(12),
1760 PMU_PMEVTYPER_EL0(13),
1761 PMU_PMEVTYPER_EL0(14),
1762 PMU_PMEVTYPER_EL0(15),
1763 PMU_PMEVTYPER_EL0(16),
1764 PMU_PMEVTYPER_EL0(17),
1765 PMU_PMEVTYPER_EL0(18),
1766 PMU_PMEVTYPER_EL0(19),
1767 PMU_PMEVTYPER_EL0(20),
1768 PMU_PMEVTYPER_EL0(21),
1769 PMU_PMEVTYPER_EL0(22),
1770 PMU_PMEVTYPER_EL0(23),
1771 PMU_PMEVTYPER_EL0(24),
1772 PMU_PMEVTYPER_EL0(25),
1773 PMU_PMEVTYPER_EL0(26),
1774 PMU_PMEVTYPER_EL0(27),
1775 PMU_PMEVTYPER_EL0(28),
1776 PMU_PMEVTYPER_EL0(29),
1777 PMU_PMEVTYPER_EL0(30),
1778 /*
1779 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1780 * in 32bit mode. Here we choose to reset it as zero for consistency.
1781 */
1782 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1783
1784 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1785 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1786 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1787 };
1788
trap_dbgidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1789 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1790 struct sys_reg_params *p,
1791 const struct sys_reg_desc *r)
1792 {
1793 if (p->is_write) {
1794 return ignore_write(vcpu, p);
1795 } else {
1796 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1797 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1798 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1799
1800 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1801 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1802 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1803 | (6 << 16) | (el3 << 14) | (el3 << 12));
1804 return true;
1805 }
1806 }
1807
trap_debug32(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1808 static bool trap_debug32(struct kvm_vcpu *vcpu,
1809 struct sys_reg_params *p,
1810 const struct sys_reg_desc *r)
1811 {
1812 if (p->is_write) {
1813 vcpu_cp14(vcpu, r->reg) = p->regval;
1814 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1815 } else {
1816 p->regval = vcpu_cp14(vcpu, r->reg);
1817 }
1818
1819 return true;
1820 }
1821
1822 /* AArch32 debug register mappings
1823 *
1824 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1825 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1826 *
1827 * All control registers and watchpoint value registers are mapped to
1828 * the lower 32 bits of their AArch64 equivalents. We share the trap
1829 * handlers with the above AArch64 code which checks what mode the
1830 * system is in.
1831 */
1832
trap_xvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)1833 static bool trap_xvr(struct kvm_vcpu *vcpu,
1834 struct sys_reg_params *p,
1835 const struct sys_reg_desc *rd)
1836 {
1837 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1838
1839 if (p->is_write) {
1840 u64 val = *dbg_reg;
1841
1842 val &= 0xffffffffUL;
1843 val |= p->regval << 32;
1844 *dbg_reg = val;
1845
1846 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1847 } else {
1848 p->regval = *dbg_reg >> 32;
1849 }
1850
1851 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1852
1853 return true;
1854 }
1855
1856 #define DBG_BCR_BVR_WCR_WVR(n) \
1857 /* DBGBVRn */ \
1858 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1859 /* DBGBCRn */ \
1860 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1861 /* DBGWVRn */ \
1862 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1863 /* DBGWCRn */ \
1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1865
1866 #define DBGBXVR(n) \
1867 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1868
1869 /*
1870 * Trapped cp14 registers. We generally ignore most of the external
1871 * debug, on the principle that they don't really make sense to a
1872 * guest. Revisit this one day, would this principle change.
1873 */
1874 static const struct sys_reg_desc cp14_regs[] = {
1875 /* DBGIDR */
1876 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1877 /* DBGDTRRXext */
1878 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1879
1880 DBG_BCR_BVR_WCR_WVR(0),
1881 /* DBGDSCRint */
1882 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1883 DBG_BCR_BVR_WCR_WVR(1),
1884 /* DBGDCCINT */
1885 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1886 /* DBGDSCRext */
1887 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1888 DBG_BCR_BVR_WCR_WVR(2),
1889 /* DBGDTR[RT]Xint */
1890 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1891 /* DBGDTR[RT]Xext */
1892 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1893 DBG_BCR_BVR_WCR_WVR(3),
1894 DBG_BCR_BVR_WCR_WVR(4),
1895 DBG_BCR_BVR_WCR_WVR(5),
1896 /* DBGWFAR */
1897 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1898 /* DBGOSECCR */
1899 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1900 DBG_BCR_BVR_WCR_WVR(6),
1901 /* DBGVCR */
1902 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1903 DBG_BCR_BVR_WCR_WVR(7),
1904 DBG_BCR_BVR_WCR_WVR(8),
1905 DBG_BCR_BVR_WCR_WVR(9),
1906 DBG_BCR_BVR_WCR_WVR(10),
1907 DBG_BCR_BVR_WCR_WVR(11),
1908 DBG_BCR_BVR_WCR_WVR(12),
1909 DBG_BCR_BVR_WCR_WVR(13),
1910 DBG_BCR_BVR_WCR_WVR(14),
1911 DBG_BCR_BVR_WCR_WVR(15),
1912
1913 /* DBGDRAR (32bit) */
1914 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1915
1916 DBGBXVR(0),
1917 /* DBGOSLAR */
1918 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1919 DBGBXVR(1),
1920 /* DBGOSLSR */
1921 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1922 DBGBXVR(2),
1923 DBGBXVR(3),
1924 /* DBGOSDLR */
1925 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1926 DBGBXVR(4),
1927 /* DBGPRCR */
1928 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1929 DBGBXVR(5),
1930 DBGBXVR(6),
1931 DBGBXVR(7),
1932 DBGBXVR(8),
1933 DBGBXVR(9),
1934 DBGBXVR(10),
1935 DBGBXVR(11),
1936 DBGBXVR(12),
1937 DBGBXVR(13),
1938 DBGBXVR(14),
1939 DBGBXVR(15),
1940
1941 /* DBGDSAR (32bit) */
1942 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1943
1944 /* DBGDEVID2 */
1945 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1946 /* DBGDEVID1 */
1947 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1948 /* DBGDEVID */
1949 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1950 /* DBGCLAIMSET */
1951 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1952 /* DBGCLAIMCLR */
1953 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1954 /* DBGAUTHSTATUS */
1955 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1956 };
1957
1958 /* Trapped cp14 64bit registers */
1959 static const struct sys_reg_desc cp14_64_regs[] = {
1960 /* DBGDRAR (64bit) */
1961 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1962
1963 /* DBGDSAR (64bit) */
1964 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1965 };
1966
1967 /* Macro to expand the PMEVCNTRn register */
1968 #define PMU_PMEVCNTR(n) \
1969 /* PMEVCNTRn */ \
1970 { Op1(0), CRn(0b1110), \
1971 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1972 access_pmu_evcntr }
1973
1974 /* Macro to expand the PMEVTYPERn register */
1975 #define PMU_PMEVTYPER(n) \
1976 /* PMEVTYPERn */ \
1977 { Op1(0), CRn(0b1110), \
1978 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1979 access_pmu_evtyper }
1980
1981 /*
1982 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1983 * depending on the way they are accessed (as a 32bit or a 64bit
1984 * register).
1985 */
1986 static const struct sys_reg_desc cp15_regs[] = {
1987 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1988 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1989 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr },
1990 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
1991 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1992 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1993 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1994 { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1995 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1996 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1997 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1998 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1999 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
2000 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
2001 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
2002
2003 /*
2004 * DC{C,I,CI}SW operations:
2005 */
2006 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2007 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2008 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2009
2010 /* PMU */
2011 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
2012 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2013 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
2014 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2015 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
2016 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
2017 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2018 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
2019 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2020 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2021 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2022 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2023 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2024 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2025 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2026
2027 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
2028 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
2029 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
2030 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
2031
2032 /* ICC_SRE */
2033 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2034
2035 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
2036
2037 /* Arch Tmers */
2038 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2039 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2040
2041 /* PMEVCNTRn */
2042 PMU_PMEVCNTR(0),
2043 PMU_PMEVCNTR(1),
2044 PMU_PMEVCNTR(2),
2045 PMU_PMEVCNTR(3),
2046 PMU_PMEVCNTR(4),
2047 PMU_PMEVCNTR(5),
2048 PMU_PMEVCNTR(6),
2049 PMU_PMEVCNTR(7),
2050 PMU_PMEVCNTR(8),
2051 PMU_PMEVCNTR(9),
2052 PMU_PMEVCNTR(10),
2053 PMU_PMEVCNTR(11),
2054 PMU_PMEVCNTR(12),
2055 PMU_PMEVCNTR(13),
2056 PMU_PMEVCNTR(14),
2057 PMU_PMEVCNTR(15),
2058 PMU_PMEVCNTR(16),
2059 PMU_PMEVCNTR(17),
2060 PMU_PMEVCNTR(18),
2061 PMU_PMEVCNTR(19),
2062 PMU_PMEVCNTR(20),
2063 PMU_PMEVCNTR(21),
2064 PMU_PMEVCNTR(22),
2065 PMU_PMEVCNTR(23),
2066 PMU_PMEVCNTR(24),
2067 PMU_PMEVCNTR(25),
2068 PMU_PMEVCNTR(26),
2069 PMU_PMEVCNTR(27),
2070 PMU_PMEVCNTR(28),
2071 PMU_PMEVCNTR(29),
2072 PMU_PMEVCNTR(30),
2073 /* PMEVTYPERn */
2074 PMU_PMEVTYPER(0),
2075 PMU_PMEVTYPER(1),
2076 PMU_PMEVTYPER(2),
2077 PMU_PMEVTYPER(3),
2078 PMU_PMEVTYPER(4),
2079 PMU_PMEVTYPER(5),
2080 PMU_PMEVTYPER(6),
2081 PMU_PMEVTYPER(7),
2082 PMU_PMEVTYPER(8),
2083 PMU_PMEVTYPER(9),
2084 PMU_PMEVTYPER(10),
2085 PMU_PMEVTYPER(11),
2086 PMU_PMEVTYPER(12),
2087 PMU_PMEVTYPER(13),
2088 PMU_PMEVTYPER(14),
2089 PMU_PMEVTYPER(15),
2090 PMU_PMEVTYPER(16),
2091 PMU_PMEVTYPER(17),
2092 PMU_PMEVTYPER(18),
2093 PMU_PMEVTYPER(19),
2094 PMU_PMEVTYPER(20),
2095 PMU_PMEVTYPER(21),
2096 PMU_PMEVTYPER(22),
2097 PMU_PMEVTYPER(23),
2098 PMU_PMEVTYPER(24),
2099 PMU_PMEVTYPER(25),
2100 PMU_PMEVTYPER(26),
2101 PMU_PMEVTYPER(27),
2102 PMU_PMEVTYPER(28),
2103 PMU_PMEVTYPER(29),
2104 PMU_PMEVTYPER(30),
2105 /* PMCCFILTR */
2106 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2107
2108 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2109 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2110 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
2111 };
2112
2113 static const struct sys_reg_desc cp15_64_regs[] = {
2114 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
2115 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2116 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2117 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
2118 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2119 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2120 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2121 };
2122
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)2123 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2124 bool is_32)
2125 {
2126 unsigned int i;
2127
2128 for (i = 0; i < n; i++) {
2129 if (!is_32 && table[i].reg && !table[i].reset) {
2130 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2131 table, i);
2132 return 1;
2133 }
2134
2135 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2136 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2137 return 1;
2138 }
2139 }
2140
2141 return 0;
2142 }
2143
match_sys_reg(const void * key,const void * elt)2144 static int match_sys_reg(const void *key, const void *elt)
2145 {
2146 const unsigned long pval = (unsigned long)key;
2147 const struct sys_reg_desc *r = elt;
2148
2149 return pval - reg_to_encoding(r);
2150 }
2151
find_reg(const struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2152 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2153 const struct sys_reg_desc table[],
2154 unsigned int num)
2155 {
2156 unsigned long pval = reg_to_encoding(params);
2157
2158 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2159 }
2160
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)2161 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2162 {
2163 kvm_inject_undefined(vcpu);
2164 return 1;
2165 }
2166
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2167 static void perform_access(struct kvm_vcpu *vcpu,
2168 struct sys_reg_params *params,
2169 const struct sys_reg_desc *r)
2170 {
2171 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2172
2173 /* Check for regs disabled by runtime config */
2174 if (sysreg_hidden(vcpu, r)) {
2175 kvm_inject_undefined(vcpu);
2176 return;
2177 }
2178
2179 /*
2180 * Not having an accessor means that we have configured a trap
2181 * that we don't know how to handle. This certainly qualifies
2182 * as a gross bug that should be fixed right away.
2183 */
2184 BUG_ON(!r->access);
2185
2186 /* Skip instruction if instructed so */
2187 if (likely(r->access(vcpu, params, r)))
2188 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2189 }
2190
2191 /*
2192 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2193 * call the corresponding trap handler.
2194 *
2195 * @params: pointer to the descriptor of the access
2196 * @table: array of trap descriptors
2197 * @num: size of the trap descriptor array
2198 *
2199 * Return 0 if the access has been handled, and -1 if not.
2200 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2201 static int emulate_cp(struct kvm_vcpu *vcpu,
2202 struct sys_reg_params *params,
2203 const struct sys_reg_desc *table,
2204 size_t num)
2205 {
2206 const struct sys_reg_desc *r;
2207
2208 if (!table)
2209 return -1; /* Not handled */
2210
2211 r = find_reg(params, table, num);
2212
2213 if (r) {
2214 perform_access(vcpu, params, r);
2215 return 0;
2216 }
2217
2218 /* Not handled */
2219 return -1;
2220 }
2221
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2222 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2223 struct sys_reg_params *params)
2224 {
2225 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2226 int cp = -1;
2227
2228 switch (esr_ec) {
2229 case ESR_ELx_EC_CP15_32:
2230 case ESR_ELx_EC_CP15_64:
2231 cp = 15;
2232 break;
2233 case ESR_ELx_EC_CP14_MR:
2234 case ESR_ELx_EC_CP14_64:
2235 cp = 14;
2236 break;
2237 default:
2238 WARN_ON(1);
2239 }
2240
2241 print_sys_reg_msg(params,
2242 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2243 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2244 kvm_inject_undefined(vcpu);
2245 }
2246
2247 /**
2248 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2249 * @vcpu: The VCPU pointer
2250 * @run: The kvm_run struct
2251 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2252 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2253 const struct sys_reg_desc *global,
2254 size_t nr_global)
2255 {
2256 struct sys_reg_params params;
2257 u32 esr = kvm_vcpu_get_esr(vcpu);
2258 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2259 int Rt2 = (esr >> 10) & 0x1f;
2260
2261 params.is_aarch32 = true;
2262 params.is_32bit = false;
2263 params.CRm = (esr >> 1) & 0xf;
2264 params.is_write = ((esr & 1) == 0);
2265
2266 params.Op0 = 0;
2267 params.Op1 = (esr >> 16) & 0xf;
2268 params.Op2 = 0;
2269 params.CRn = 0;
2270
2271 /*
2272 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2273 * backends between AArch32 and AArch64, we get away with it.
2274 */
2275 if (params.is_write) {
2276 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2277 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2278 }
2279
2280 /*
2281 * If the table contains a handler, handle the
2282 * potential register operation in the case of a read and return
2283 * with success.
2284 */
2285 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2286 /* Split up the value between registers for the read side */
2287 if (!params.is_write) {
2288 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2289 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2290 }
2291
2292 return 1;
2293 }
2294
2295 unhandled_cp_access(vcpu, ¶ms);
2296 return 1;
2297 }
2298
2299 /**
2300 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2301 * @vcpu: The VCPU pointer
2302 * @run: The kvm_run struct
2303 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2304 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2305 const struct sys_reg_desc *global,
2306 size_t nr_global)
2307 {
2308 struct sys_reg_params params;
2309 u32 esr = kvm_vcpu_get_esr(vcpu);
2310 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2311
2312 params.is_aarch32 = true;
2313 params.is_32bit = true;
2314 params.CRm = (esr >> 1) & 0xf;
2315 params.regval = vcpu_get_reg(vcpu, Rt);
2316 params.is_write = ((esr & 1) == 0);
2317 params.CRn = (esr >> 10) & 0xf;
2318 params.Op0 = 0;
2319 params.Op1 = (esr >> 14) & 0x7;
2320 params.Op2 = (esr >> 17) & 0x7;
2321
2322 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2323 if (!params.is_write)
2324 vcpu_set_reg(vcpu, Rt, params.regval);
2325 return 1;
2326 }
2327
2328 unhandled_cp_access(vcpu, ¶ms);
2329 return 1;
2330 }
2331
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)2332 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2333 {
2334 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2335 }
2336
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)2337 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2338 {
2339 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2340 }
2341
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)2342 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2343 {
2344 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2345 }
2346
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)2347 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2348 {
2349 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2350 }
2351
is_imp_def_sys_reg(struct sys_reg_params * params)2352 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2353 {
2354 // See ARM DDI 0487E.a, section D12.3.2
2355 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2356 }
2357
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2358 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2359 struct sys_reg_params *params)
2360 {
2361 const struct sys_reg_desc *r;
2362
2363 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2364
2365 if (likely(r)) {
2366 perform_access(vcpu, params, r);
2367 } else if (is_imp_def_sys_reg(params)) {
2368 kvm_inject_undefined(vcpu);
2369 } else {
2370 print_sys_reg_msg(params,
2371 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2372 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2373 kvm_inject_undefined(vcpu);
2374 }
2375 return 1;
2376 }
2377
2378 /**
2379 * kvm_reset_sys_regs - sets system registers to reset value
2380 * @vcpu: The VCPU pointer
2381 *
2382 * This function finds the right table above and sets the registers on the
2383 * virtual CPU struct to their architecturally defined reset values.
2384 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)2385 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2386 {
2387 unsigned long i;
2388
2389 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2390 if (sys_reg_descs[i].reset)
2391 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2392 }
2393
2394 /**
2395 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2396 * @vcpu: The VCPU pointer
2397 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)2398 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2399 {
2400 struct sys_reg_params params;
2401 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2402 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2403 int ret;
2404
2405 trace_kvm_handle_sys_reg(esr);
2406
2407 params.is_aarch32 = false;
2408 params.is_32bit = false;
2409 params.Op0 = (esr >> 20) & 3;
2410 params.Op1 = (esr >> 14) & 0x7;
2411 params.CRn = (esr >> 10) & 0xf;
2412 params.CRm = (esr >> 1) & 0xf;
2413 params.Op2 = (esr >> 17) & 0x7;
2414 params.regval = vcpu_get_reg(vcpu, Rt);
2415 params.is_write = !(esr & 1);
2416
2417 ret = emulate_sys_reg(vcpu, ¶ms);
2418
2419 if (!params.is_write)
2420 vcpu_set_reg(vcpu, Rt, params.regval);
2421 return ret;
2422 }
2423
2424 /******************************************************************************
2425 * Userspace API
2426 *****************************************************************************/
2427
index_to_params(u64 id,struct sys_reg_params * params)2428 static bool index_to_params(u64 id, struct sys_reg_params *params)
2429 {
2430 switch (id & KVM_REG_SIZE_MASK) {
2431 case KVM_REG_SIZE_U64:
2432 /* Any unused index bits means it's not valid. */
2433 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2434 | KVM_REG_ARM_COPROC_MASK
2435 | KVM_REG_ARM64_SYSREG_OP0_MASK
2436 | KVM_REG_ARM64_SYSREG_OP1_MASK
2437 | KVM_REG_ARM64_SYSREG_CRN_MASK
2438 | KVM_REG_ARM64_SYSREG_CRM_MASK
2439 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2440 return false;
2441 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2442 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2443 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2444 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2445 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2446 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2447 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2448 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2449 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2450 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2451 return true;
2452 default:
2453 return false;
2454 }
2455 }
2456
find_reg_by_id(u64 id,struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2457 const struct sys_reg_desc *find_reg_by_id(u64 id,
2458 struct sys_reg_params *params,
2459 const struct sys_reg_desc table[],
2460 unsigned int num)
2461 {
2462 if (!index_to_params(id, params))
2463 return NULL;
2464
2465 return find_reg(params, table, num);
2466 }
2467
2468 /* Decode an index value, and find the sys_reg_desc entry. */
index_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id)2469 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2470 u64 id)
2471 {
2472 const struct sys_reg_desc *r;
2473 struct sys_reg_params params;
2474
2475 /* We only do sys_reg for now. */
2476 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2477 return NULL;
2478
2479 if (!index_to_params(id, ¶ms))
2480 return NULL;
2481
2482 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2483
2484 /* Not saved in the sys_reg array and not otherwise accessible? */
2485 if (r && !(r->reg || r->get_user))
2486 r = NULL;
2487
2488 return r;
2489 }
2490
2491 /*
2492 * These are the invariant sys_reg registers: we let the guest see the
2493 * host versions of these, so they're part of the guest state.
2494 *
2495 * A future CPU may provide a mechanism to present different values to
2496 * the guest, or a future kvm may trap them.
2497 */
2498
2499 #define FUNCTION_INVARIANT(reg) \
2500 static void get_##reg(struct kvm_vcpu *v, \
2501 const struct sys_reg_desc *r) \
2502 { \
2503 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2504 }
2505
2506 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)2507 FUNCTION_INVARIANT(revidr_el1)
2508 FUNCTION_INVARIANT(clidr_el1)
2509 FUNCTION_INVARIANT(aidr_el1)
2510
2511 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2512 {
2513 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2514 }
2515
2516 /* ->val is filled in by kvm_sys_reg_table_init() */
2517 static struct sys_reg_desc invariant_sys_regs[] = {
2518 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2519 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2520 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2521 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2522 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2523 };
2524
reg_from_user(u64 * val,const void __user * uaddr,u64 id)2525 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2526 {
2527 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2528 return -EFAULT;
2529 return 0;
2530 }
2531
reg_to_user(void __user * uaddr,const u64 * val,u64 id)2532 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2533 {
2534 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2535 return -EFAULT;
2536 return 0;
2537 }
2538
get_invariant_sys_reg(u64 id,void __user * uaddr)2539 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2540 {
2541 struct sys_reg_params params;
2542 const struct sys_reg_desc *r;
2543
2544 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2545 ARRAY_SIZE(invariant_sys_regs));
2546 if (!r)
2547 return -ENOENT;
2548
2549 return reg_to_user(uaddr, &r->val, id);
2550 }
2551
set_invariant_sys_reg(u64 id,void __user * uaddr)2552 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2553 {
2554 struct sys_reg_params params;
2555 const struct sys_reg_desc *r;
2556 int err;
2557 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2558
2559 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2560 ARRAY_SIZE(invariant_sys_regs));
2561 if (!r)
2562 return -ENOENT;
2563
2564 err = reg_from_user(&val, uaddr, id);
2565 if (err)
2566 return err;
2567
2568 /* This is what we mean by invariant: you can't change it. */
2569 if (r->val != val)
2570 return -EINVAL;
2571
2572 return 0;
2573 }
2574
is_valid_cache(u32 val)2575 static bool is_valid_cache(u32 val)
2576 {
2577 u32 level, ctype;
2578
2579 if (val >= CSSELR_MAX)
2580 return false;
2581
2582 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2583 level = (val >> 1);
2584 ctype = (cache_levels >> (level * 3)) & 7;
2585
2586 switch (ctype) {
2587 case 0: /* No cache */
2588 return false;
2589 case 1: /* Instruction cache only */
2590 return (val & 1);
2591 case 2: /* Data cache only */
2592 case 4: /* Unified cache */
2593 return !(val & 1);
2594 case 3: /* Separate instruction and data caches */
2595 return true;
2596 default: /* Reserved: we can't know instruction or data. */
2597 return false;
2598 }
2599 }
2600
demux_c15_get(u64 id,void __user * uaddr)2601 static int demux_c15_get(u64 id, void __user *uaddr)
2602 {
2603 u32 val;
2604 u32 __user *uval = uaddr;
2605
2606 /* Fail if we have unknown bits set. */
2607 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2608 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2609 return -ENOENT;
2610
2611 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2612 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2613 if (KVM_REG_SIZE(id) != 4)
2614 return -ENOENT;
2615 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2616 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2617 if (!is_valid_cache(val))
2618 return -ENOENT;
2619
2620 return put_user(get_ccsidr(val), uval);
2621 default:
2622 return -ENOENT;
2623 }
2624 }
2625
demux_c15_set(u64 id,void __user * uaddr)2626 static int demux_c15_set(u64 id, void __user *uaddr)
2627 {
2628 u32 val, newval;
2629 u32 __user *uval = uaddr;
2630
2631 /* Fail if we have unknown bits set. */
2632 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2633 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2634 return -ENOENT;
2635
2636 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2637 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2638 if (KVM_REG_SIZE(id) != 4)
2639 return -ENOENT;
2640 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2641 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2642 if (!is_valid_cache(val))
2643 return -ENOENT;
2644
2645 if (get_user(newval, uval))
2646 return -EFAULT;
2647
2648 /* This is also invariant: you can't change it. */
2649 if (newval != get_ccsidr(val))
2650 return -EINVAL;
2651 return 0;
2652 default:
2653 return -ENOENT;
2654 }
2655 }
2656
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2657 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2658 {
2659 const struct sys_reg_desc *r;
2660 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2661
2662 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2663 return demux_c15_get(reg->id, uaddr);
2664
2665 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2666 return -ENOENT;
2667
2668 r = index_to_sys_reg_desc(vcpu, reg->id);
2669 if (!r)
2670 return get_invariant_sys_reg(reg->id, uaddr);
2671
2672 /* Check for regs disabled by runtime config */
2673 if (sysreg_hidden(vcpu, r))
2674 return -ENOENT;
2675
2676 if (r->get_user)
2677 return (r->get_user)(vcpu, r, reg, uaddr);
2678
2679 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2680 }
2681
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2682 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2683 {
2684 const struct sys_reg_desc *r;
2685 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2686
2687 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2688 return demux_c15_set(reg->id, uaddr);
2689
2690 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2691 return -ENOENT;
2692
2693 r = index_to_sys_reg_desc(vcpu, reg->id);
2694 if (!r)
2695 return set_invariant_sys_reg(reg->id, uaddr);
2696
2697 /* Check for regs disabled by runtime config */
2698 if (sysreg_hidden(vcpu, r))
2699 return -ENOENT;
2700
2701 if (r->set_user)
2702 return (r->set_user)(vcpu, r, reg, uaddr);
2703
2704 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2705 }
2706
num_demux_regs(void)2707 static unsigned int num_demux_regs(void)
2708 {
2709 unsigned int i, count = 0;
2710
2711 for (i = 0; i < CSSELR_MAX; i++)
2712 if (is_valid_cache(i))
2713 count++;
2714
2715 return count;
2716 }
2717
write_demux_regids(u64 __user * uindices)2718 static int write_demux_regids(u64 __user *uindices)
2719 {
2720 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2721 unsigned int i;
2722
2723 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2724 for (i = 0; i < CSSELR_MAX; i++) {
2725 if (!is_valid_cache(i))
2726 continue;
2727 if (put_user(val | i, uindices))
2728 return -EFAULT;
2729 uindices++;
2730 }
2731 return 0;
2732 }
2733
sys_reg_to_index(const struct sys_reg_desc * reg)2734 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2735 {
2736 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2737 KVM_REG_ARM64_SYSREG |
2738 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2739 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2740 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2741 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2742 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2743 }
2744
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)2745 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2746 {
2747 if (!*uind)
2748 return true;
2749
2750 if (put_user(sys_reg_to_index(reg), *uind))
2751 return false;
2752
2753 (*uind)++;
2754 return true;
2755 }
2756
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)2757 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2758 const struct sys_reg_desc *rd,
2759 u64 __user **uind,
2760 unsigned int *total)
2761 {
2762 /*
2763 * Ignore registers we trap but don't save,
2764 * and for which no custom user accessor is provided.
2765 */
2766 if (!(rd->reg || rd->get_user))
2767 return 0;
2768
2769 if (sysreg_hidden(vcpu, rd))
2770 return 0;
2771
2772 if (!copy_reg_to_user(rd, uind))
2773 return -EFAULT;
2774
2775 (*total)++;
2776 return 0;
2777 }
2778
2779 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)2780 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2781 {
2782 const struct sys_reg_desc *i2, *end2;
2783 unsigned int total = 0;
2784 int err;
2785
2786 i2 = sys_reg_descs;
2787 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2788
2789 while (i2 != end2) {
2790 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2791 if (err)
2792 return err;
2793 }
2794 return total;
2795 }
2796
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)2797 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2798 {
2799 return ARRAY_SIZE(invariant_sys_regs)
2800 + num_demux_regs()
2801 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2802 }
2803
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)2804 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2805 {
2806 unsigned int i;
2807 int err;
2808
2809 /* Then give them all the invariant registers' indices. */
2810 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2811 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2812 return -EFAULT;
2813 uindices++;
2814 }
2815
2816 err = walk_sys_regs(vcpu, uindices);
2817 if (err < 0)
2818 return err;
2819 uindices += err;
2820
2821 return write_demux_regids(uindices);
2822 }
2823
kvm_sys_reg_table_init(void)2824 void kvm_sys_reg_table_init(void)
2825 {
2826 unsigned int i;
2827 struct sys_reg_desc clidr;
2828
2829 /* Make sure tables are unique and in order. */
2830 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2831 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2832 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2833 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2834 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2835 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2836
2837 /* We abuse the reset function to overwrite the table itself. */
2838 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2839 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2840
2841 /*
2842 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2843 *
2844 * If software reads the Cache Type fields from Ctype1
2845 * upwards, once it has seen a value of 0b000, no caches
2846 * exist at further-out levels of the hierarchy. So, for
2847 * example, if Ctype3 is the first Cache Type field with a
2848 * value of 0b000, the values of Ctype4 to Ctype7 must be
2849 * ignored.
2850 */
2851 get_clidr_el1(NULL, &clidr); /* Ugly... */
2852 cache_levels = clidr.val;
2853 for (i = 0; i < 7; i++)
2854 if (((cache_levels >> (i*3)) & 7) == 0)
2855 break;
2856 /* Clear all higher bits. */
2857 cache_levels &= (1 << (i*3))-1;
2858 }
2859