1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/intel_ds.h>
18
19 /* To enable MSR tracing please use the generic trace points. */
20
21 /*
22 * | NHM/WSM | SNB |
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
30 *
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
34 */
35 enum extra_reg_type {
36 EXTRA_REG_NONE = -1, /* not used */
37
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
43
44 EXTRA_REG_MAX /* number of entries needed */
45 };
46
47 struct event_constraint {
48 union {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
50 u64 idxmsk64;
51 };
52 u64 code;
53 u64 cmask;
54 int weight;
55 int overlap;
56 int flags;
57 unsigned int size;
58 };
59
constraint_match(struct event_constraint * c,u64 ecode)60 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
61 {
62 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
63 }
64
65 /*
66 * struct hw_perf_event.flags flags
67 */
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */
72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */
73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */
74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */
75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */
76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */
77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */
78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */
79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */
80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */
81 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */
82 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */
83
is_topdown_count(struct perf_event * event)84 static inline bool is_topdown_count(struct perf_event *event)
85 {
86 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
87 }
88
is_metric_event(struct perf_event * event)89 static inline bool is_metric_event(struct perf_event *event)
90 {
91 u64 config = event->attr.config;
92
93 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
94 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
95 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
96 }
97
is_slots_event(struct perf_event * event)98 static inline bool is_slots_event(struct perf_event *event)
99 {
100 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
101 }
102
is_topdown_event(struct perf_event * event)103 static inline bool is_topdown_event(struct perf_event *event)
104 {
105 return is_metric_event(event) || is_slots_event(event);
106 }
107
108 struct amd_nb {
109 int nb_id; /* NorthBridge id */
110 int refcnt; /* reference count */
111 struct perf_event *owners[X86_PMC_IDX_MAX];
112 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
113 };
114
115 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
116 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
117 #define PEBS_OUTPUT_OFFSET 61
118 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
119 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
120 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
121
122 /*
123 * Flags PEBS can handle without an PMI.
124 *
125 * TID can only be handled by flushing at context switch.
126 * REGS_USER can be handled for events limited to ring 3.
127 *
128 */
129 #define LARGE_PEBS_FLAGS \
130 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
131 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
132 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
133 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
134 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
135 PERF_SAMPLE_PERIOD)
136
137 #define PEBS_GP_REGS \
138 ((1ULL << PERF_REG_X86_AX) | \
139 (1ULL << PERF_REG_X86_BX) | \
140 (1ULL << PERF_REG_X86_CX) | \
141 (1ULL << PERF_REG_X86_DX) | \
142 (1ULL << PERF_REG_X86_DI) | \
143 (1ULL << PERF_REG_X86_SI) | \
144 (1ULL << PERF_REG_X86_SP) | \
145 (1ULL << PERF_REG_X86_BP) | \
146 (1ULL << PERF_REG_X86_IP) | \
147 (1ULL << PERF_REG_X86_FLAGS) | \
148 (1ULL << PERF_REG_X86_R8) | \
149 (1ULL << PERF_REG_X86_R9) | \
150 (1ULL << PERF_REG_X86_R10) | \
151 (1ULL << PERF_REG_X86_R11) | \
152 (1ULL << PERF_REG_X86_R12) | \
153 (1ULL << PERF_REG_X86_R13) | \
154 (1ULL << PERF_REG_X86_R14) | \
155 (1ULL << PERF_REG_X86_R15))
156
157 /*
158 * Per register state.
159 */
160 struct er_account {
161 raw_spinlock_t lock; /* per-core: protect structure */
162 u64 config; /* extra MSR config */
163 u64 reg; /* extra MSR number */
164 atomic_t ref; /* reference count */
165 };
166
167 /*
168 * Per core/cpu state
169 *
170 * Used to coordinate shared registers between HT threads or
171 * among events on a single PMU.
172 */
173 struct intel_shared_regs {
174 struct er_account regs[EXTRA_REG_MAX];
175 int refcnt; /* per-core: #HT threads */
176 unsigned core_id; /* per-core: core id */
177 };
178
179 enum intel_excl_state_type {
180 INTEL_EXCL_UNUSED = 0, /* counter is unused */
181 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
182 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
183 };
184
185 struct intel_excl_states {
186 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
187 bool sched_started; /* true if scheduling has started */
188 };
189
190 struct intel_excl_cntrs {
191 raw_spinlock_t lock;
192
193 struct intel_excl_states states[2];
194
195 union {
196 u16 has_exclusive[2];
197 u32 exclusive_present;
198 };
199
200 int refcnt; /* per-core: #HT threads */
201 unsigned core_id; /* per-core: core id */
202 };
203
204 struct x86_perf_task_context;
205 #define MAX_LBR_ENTRIES 32
206
207 enum {
208 LBR_FORMAT_32 = 0x00,
209 LBR_FORMAT_LIP = 0x01,
210 LBR_FORMAT_EIP = 0x02,
211 LBR_FORMAT_EIP_FLAGS = 0x03,
212 LBR_FORMAT_EIP_FLAGS2 = 0x04,
213 LBR_FORMAT_INFO = 0x05,
214 LBR_FORMAT_TIME = 0x06,
215 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
216 };
217
218 enum {
219 X86_PERF_KFREE_SHARED = 0,
220 X86_PERF_KFREE_EXCL = 1,
221 X86_PERF_KFREE_MAX
222 };
223
224 struct cpu_hw_events {
225 /*
226 * Generic x86 PMC bits
227 */
228 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
229 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
230 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
231 int enabled;
232
233 int n_events; /* the # of events in the below arrays */
234 int n_added; /* the # last events in the below arrays;
235 they've never been enabled yet */
236 int n_txn; /* the # last events in the below arrays;
237 added in the current transaction */
238 int n_txn_pair;
239 int n_txn_metric;
240 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
241 u64 tags[X86_PMC_IDX_MAX];
242
243 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
244 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
245
246 int n_excl; /* the number of exclusive events */
247
248 unsigned int txn_flags;
249 int is_fake;
250
251 /*
252 * Intel DebugStore bits
253 */
254 struct debug_store *ds;
255 void *ds_pebs_vaddr;
256 void *ds_bts_vaddr;
257 u64 pebs_enabled;
258 int n_pebs;
259 int n_large_pebs;
260 int n_pebs_via_pt;
261 int pebs_output;
262
263 /* Current super set of events hardware configuration */
264 u64 pebs_data_cfg;
265 u64 active_pebs_data_cfg;
266 int pebs_record_size;
267
268 /*
269 * Intel LBR bits
270 */
271 int lbr_users;
272 int lbr_pebs_users;
273 struct perf_branch_stack lbr_stack;
274 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
275 union {
276 struct er_account *lbr_sel;
277 struct er_account *lbr_ctl;
278 };
279 u64 br_sel;
280 void *last_task_ctx;
281 int last_log_id;
282 int lbr_select;
283 void *lbr_xsave;
284
285 /*
286 * Intel host/guest exclude bits
287 */
288 u64 intel_ctrl_guest_mask;
289 u64 intel_ctrl_host_mask;
290 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
291
292 /*
293 * Intel checkpoint mask
294 */
295 u64 intel_cp_status;
296
297 /*
298 * manage shared (per-core, per-cpu) registers
299 * used on Intel NHM/WSM/SNB
300 */
301 struct intel_shared_regs *shared_regs;
302 /*
303 * manage exclusive counter access between hyperthread
304 */
305 struct event_constraint *constraint_list; /* in enable order */
306 struct intel_excl_cntrs *excl_cntrs;
307 int excl_thread_id; /* 0 or 1 */
308
309 /*
310 * SKL TSX_FORCE_ABORT shadow
311 */
312 u64 tfa_shadow;
313
314 /*
315 * Perf Metrics
316 */
317 /* number of accepted metrics events */
318 int n_metric;
319
320 /*
321 * AMD specific bits
322 */
323 struct amd_nb *amd_nb;
324 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
325 u64 perf_ctr_virt_mask;
326 int n_pair; /* Large increment events */
327
328 void *kfree_on_online[X86_PERF_KFREE_MAX];
329
330 struct pmu *pmu;
331 };
332
333 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
334 { .idxmsk64 = (n) }, \
335 .code = (c), \
336 .size = (e) - (c), \
337 .cmask = (m), \
338 .weight = (w), \
339 .overlap = (o), \
340 .flags = f, \
341 }
342
343 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
344 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
345
346 #define EVENT_CONSTRAINT(c, n, m) \
347 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
348
349 /*
350 * The constraint_match() function only works for 'simple' event codes
351 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
352 */
353 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
354 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
355
356 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
357 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
358 0, PERF_X86_EVENT_EXCL)
359
360 /*
361 * The overlap flag marks event constraints with overlapping counter
362 * masks. This is the case if the counter mask of such an event is not
363 * a subset of any other counter mask of a constraint with an equal or
364 * higher weight, e.g.:
365 *
366 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
367 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
368 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
369 *
370 * The event scheduler may not select the correct counter in the first
371 * cycle because it needs to know which subsequent events will be
372 * scheduled. It may fail to schedule the events then. So we set the
373 * overlap flag for such constraints to give the scheduler a hint which
374 * events to select for counter rescheduling.
375 *
376 * Care must be taken as the rescheduling algorithm is O(n!) which
377 * will increase scheduling cycles for an over-committed system
378 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
379 * and its counter masks must be kept at a minimum.
380 */
381 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
382 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
383
384 /*
385 * Constraint on the Event code.
386 */
387 #define INTEL_EVENT_CONSTRAINT(c, n) \
388 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
389
390 /*
391 * Constraint on a range of Event codes
392 */
393 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
394 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
395
396 /*
397 * Constraint on the Event code + UMask + fixed-mask
398 *
399 * filter mask to validate fixed counter events.
400 * the following filters disqualify for fixed counters:
401 * - inv
402 * - edge
403 * - cnt-mask
404 * - in_tx
405 * - in_tx_checkpointed
406 * The other filters are supported by fixed counters.
407 * The any-thread option is supported starting with v3.
408 */
409 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
410 #define FIXED_EVENT_CONSTRAINT(c, n) \
411 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
412
413 /*
414 * The special metric counters do not actually exist. They are calculated from
415 * the combination of the FxCtr3 + MSR_PERF_METRICS.
416 *
417 * The special metric counters are mapped to a dummy offset for the scheduler.
418 * The sharing between multiple users of the same metric without multiplexing
419 * is not allowed, even though the hardware supports that in principle.
420 */
421
422 #define METRIC_EVENT_CONSTRAINT(c, n) \
423 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
424 INTEL_ARCH_EVENT_MASK)
425
426 /*
427 * Constraint on the Event code + UMask
428 */
429 #define INTEL_UEVENT_CONSTRAINT(c, n) \
430 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
431
432 /* Constraint on specific umask bit only + event */
433 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
434 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
435
436 /* Like UEVENT_CONSTRAINT, but match flags too */
437 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
438 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
439
440 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
441 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
442 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
443
444 #define INTEL_PLD_CONSTRAINT(c, n) \
445 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
446 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
447
448 #define INTEL_PST_CONSTRAINT(c, n) \
449 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
450 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
451
452 /* Event constraint, but match on all event flags too. */
453 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
454 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
455
456 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
457 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
458
459 /* Check only flags, but allow all event/umask */
460 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
461 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
462
463 /* Check flags and event code, and set the HSW store flag */
464 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
465 __EVENT_CONSTRAINT(code, n, \
466 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
467 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
468
469 /* Check flags and event code, and set the HSW load flag */
470 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
471 __EVENT_CONSTRAINT(code, n, \
472 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
473 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
474
475 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
476 __EVENT_CONSTRAINT_RANGE(code, end, n, \
477 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
478 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
479
480 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
481 __EVENT_CONSTRAINT(code, n, \
482 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
483 HWEIGHT(n), 0, \
484 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
485
486 /* Check flags and event code/umask, and set the HSW store flag */
487 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
488 __EVENT_CONSTRAINT(code, n, \
489 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
490 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
491
492 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
493 __EVENT_CONSTRAINT(code, n, \
494 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
495 HWEIGHT(n), 0, \
496 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
497
498 /* Check flags and event code/umask, and set the HSW load flag */
499 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
500 __EVENT_CONSTRAINT(code, n, \
501 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
502 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
503
504 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
505 __EVENT_CONSTRAINT(code, n, \
506 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
507 HWEIGHT(n), 0, \
508 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
509
510 /* Check flags and event code/umask, and set the HSW N/A flag */
511 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
512 __EVENT_CONSTRAINT(code, n, \
513 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
514 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
515
516
517 /*
518 * We define the end marker as having a weight of -1
519 * to enable blacklisting of events using a counter bitmask
520 * of zero and thus a weight of zero.
521 * The end marker has a weight that cannot possibly be
522 * obtained from counting the bits in the bitmask.
523 */
524 #define EVENT_CONSTRAINT_END { .weight = -1 }
525
526 /*
527 * Check for end marker with weight == -1
528 */
529 #define for_each_event_constraint(e, c) \
530 for ((e) = (c); (e)->weight != -1; (e)++)
531
532 /*
533 * Extra registers for specific events.
534 *
535 * Some events need large masks and require external MSRs.
536 * Those extra MSRs end up being shared for all events on
537 * a PMU and sometimes between PMU of sibling HT threads.
538 * In either case, the kernel needs to handle conflicting
539 * accesses to those extra, shared, regs. The data structure
540 * to manage those registers is stored in cpu_hw_event.
541 */
542 struct extra_reg {
543 unsigned int event;
544 unsigned int msr;
545 u64 config_mask;
546 u64 valid_mask;
547 int idx; /* per_xxx->regs[] reg index */
548 bool extra_msr_access;
549 };
550
551 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
552 .event = (e), \
553 .msr = (ms), \
554 .config_mask = (m), \
555 .valid_mask = (vm), \
556 .idx = EXTRA_REG_##i, \
557 .extra_msr_access = true, \
558 }
559
560 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
561 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
562
563 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
564 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
565 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
566
567 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
568 INTEL_UEVENT_EXTRA_REG(c, \
569 MSR_PEBS_LD_LAT_THRESHOLD, \
570 0xffff, \
571 LDLAT)
572
573 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
574
575 union perf_capabilities {
576 struct {
577 u64 lbr_format:6;
578 u64 pebs_trap:1;
579 u64 pebs_arch_reg:1;
580 u64 pebs_format:4;
581 u64 smm_freeze:1;
582 /*
583 * PMU supports separate counter range for writing
584 * values > 32bit.
585 */
586 u64 full_width_write:1;
587 u64 pebs_baseline:1;
588 u64 perf_metrics:1;
589 u64 pebs_output_pt_available:1;
590 u64 anythread_deprecated:1;
591 };
592 u64 capabilities;
593 };
594
595 struct x86_pmu_quirk {
596 struct x86_pmu_quirk *next;
597 void (*func)(void);
598 };
599
600 union x86_pmu_config {
601 struct {
602 u64 event:8,
603 umask:8,
604 usr:1,
605 os:1,
606 edge:1,
607 pc:1,
608 interrupt:1,
609 __reserved1:1,
610 en:1,
611 inv:1,
612 cmask:8,
613 event2:4,
614 __reserved2:4,
615 go:1,
616 ho:1;
617 } bits;
618 u64 value;
619 };
620
621 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
622
623 enum {
624 x86_lbr_exclusive_lbr,
625 x86_lbr_exclusive_bts,
626 x86_lbr_exclusive_pt,
627 x86_lbr_exclusive_max,
628 };
629
630 /*
631 * struct x86_pmu - generic x86 pmu
632 */
633 struct x86_pmu {
634 /*
635 * Generic x86 PMC bits
636 */
637 const char *name;
638 int version;
639 int (*handle_irq)(struct pt_regs *);
640 void (*disable_all)(void);
641 void (*enable_all)(int added);
642 void (*enable)(struct perf_event *);
643 void (*disable)(struct perf_event *);
644 void (*add)(struct perf_event *);
645 void (*del)(struct perf_event *);
646 void (*read)(struct perf_event *event);
647 int (*hw_config)(struct perf_event *event);
648 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
649 unsigned eventsel;
650 unsigned perfctr;
651 int (*addr_offset)(int index, bool eventsel);
652 int (*rdpmc_index)(int index);
653 u64 (*event_map)(int);
654 int max_events;
655 int num_counters;
656 int num_counters_fixed;
657 int cntval_bits;
658 u64 cntval_mask;
659 union {
660 unsigned long events_maskl;
661 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
662 };
663 int events_mask_len;
664 int apic;
665 u64 max_period;
666 struct event_constraint *
667 (*get_event_constraints)(struct cpu_hw_events *cpuc,
668 int idx,
669 struct perf_event *event);
670
671 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
672 struct perf_event *event);
673
674 void (*start_scheduling)(struct cpu_hw_events *cpuc);
675
676 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
677
678 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
679
680 struct event_constraint *event_constraints;
681 struct x86_pmu_quirk *quirks;
682 int perfctr_second_write;
683 u64 (*limit_period)(struct perf_event *event, u64 l);
684
685 /* PMI handler bits */
686 unsigned int late_ack :1,
687 enabled_ack :1,
688 counter_freezing :1;
689 /*
690 * sysfs attrs
691 */
692 int attr_rdpmc_broken;
693 int attr_rdpmc;
694 struct attribute **format_attrs;
695
696 ssize_t (*events_sysfs_show)(char *page, u64 config);
697 const struct attribute_group **attr_update;
698
699 unsigned long attr_freeze_on_smi;
700
701 /*
702 * CPU Hotplug hooks
703 */
704 int (*cpu_prepare)(int cpu);
705 void (*cpu_starting)(int cpu);
706 void (*cpu_dying)(int cpu);
707 void (*cpu_dead)(int cpu);
708
709 void (*check_microcode)(void);
710 void (*sched_task)(struct perf_event_context *ctx,
711 bool sched_in);
712
713 /*
714 * Intel Arch Perfmon v2+
715 */
716 u64 intel_ctrl;
717 union perf_capabilities intel_cap;
718
719 /*
720 * Intel DebugStore bits
721 */
722 unsigned int bts :1,
723 bts_active :1,
724 pebs :1,
725 pebs_active :1,
726 pebs_broken :1,
727 pebs_prec_dist :1,
728 pebs_no_tlb :1,
729 pebs_no_isolation :1;
730 int pebs_record_size;
731 int pebs_buffer_size;
732 int max_pebs_events;
733 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
734 struct event_constraint *pebs_constraints;
735 void (*pebs_aliases)(struct perf_event *event);
736 unsigned long large_pebs_flags;
737 u64 rtm_abort_event;
738
739 /*
740 * Intel LBR
741 */
742 unsigned int lbr_tos, lbr_from, lbr_to,
743 lbr_info, lbr_nr; /* LBR base regs and size */
744 union {
745 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
746 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
747 };
748 union {
749 const int *lbr_sel_map; /* lbr_select mappings */
750 int *lbr_ctl_map; /* LBR_CTL mappings */
751 };
752 bool lbr_double_abort; /* duplicated lbr aborts */
753 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
754
755 /*
756 * Intel Architectural LBR CPUID Enumeration
757 */
758 unsigned int lbr_depth_mask:8;
759 unsigned int lbr_deep_c_reset:1;
760 unsigned int lbr_lip:1;
761 unsigned int lbr_cpl:1;
762 unsigned int lbr_filter:1;
763 unsigned int lbr_call_stack:1;
764 unsigned int lbr_mispred:1;
765 unsigned int lbr_timed_lbr:1;
766 unsigned int lbr_br_type:1;
767
768 void (*lbr_reset)(void);
769 void (*lbr_read)(struct cpu_hw_events *cpuc);
770 void (*lbr_save)(void *ctx);
771 void (*lbr_restore)(void *ctx);
772
773 /*
774 * Intel PT/LBR/BTS are exclusive
775 */
776 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
777
778 /*
779 * Intel perf metrics
780 */
781 u64 (*update_topdown_event)(struct perf_event *event);
782 int (*set_topdown_event_period)(struct perf_event *event);
783
784 /*
785 * perf task context (i.e. struct perf_event_context::task_ctx_data)
786 * switch helper to bridge calls from perf/core to perf/x86.
787 * See struct pmu::swap_task_ctx() usage for examples;
788 */
789 void (*swap_task_ctx)(struct perf_event_context *prev,
790 struct perf_event_context *next);
791
792 /*
793 * AMD bits
794 */
795 unsigned int amd_nb_constraints : 1;
796 u64 perf_ctr_pair_en;
797
798 /*
799 * Extra registers for events
800 */
801 struct extra_reg *extra_regs;
802 unsigned int flags;
803
804 /*
805 * Intel host/guest support (KVM)
806 */
807 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
808
809 /*
810 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
811 */
812 int (*check_period) (struct perf_event *event, u64 period);
813
814 int (*aux_output_match) (struct perf_event *event);
815 };
816
817 struct x86_perf_task_context_opt {
818 int lbr_callstack_users;
819 int lbr_stack_state;
820 int log_id;
821 };
822
823 struct x86_perf_task_context {
824 u64 lbr_sel;
825 int tos;
826 int valid_lbrs;
827 struct x86_perf_task_context_opt opt;
828 struct lbr_entry lbr[MAX_LBR_ENTRIES];
829 };
830
831 struct x86_perf_task_context_arch_lbr {
832 struct x86_perf_task_context_opt opt;
833 struct lbr_entry entries[];
834 };
835
836 /*
837 * Add padding to guarantee the 64-byte alignment of the state buffer.
838 *
839 * The structure is dynamically allocated. The size of the LBR state may vary
840 * based on the number of LBR registers.
841 *
842 * Do not put anything after the LBR state.
843 */
844 struct x86_perf_task_context_arch_lbr_xsave {
845 struct x86_perf_task_context_opt opt;
846
847 union {
848 struct xregs_state xsave;
849 struct {
850 struct fxregs_state i387;
851 struct xstate_header header;
852 struct arch_lbr_state lbr;
853 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
854 };
855 };
856
857 #define x86_add_quirk(func_) \
858 do { \
859 static struct x86_pmu_quirk __quirk __initdata = { \
860 .func = func_, \
861 }; \
862 __quirk.next = x86_pmu.quirks; \
863 x86_pmu.quirks = &__quirk; \
864 } while (0)
865
866 /*
867 * x86_pmu flags
868 */
869 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
870 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
871 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
872 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
873 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
874 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
875 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
876
877 #define EVENT_VAR(_id) event_attr_##_id
878 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
879
880 #define EVENT_ATTR(_name, _id) \
881 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
882 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
883 .id = PERF_COUNT_HW_##_id, \
884 .event_str = NULL, \
885 };
886
887 #define EVENT_ATTR_STR(_name, v, str) \
888 static struct perf_pmu_events_attr event_attr_##v = { \
889 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
890 .id = 0, \
891 .event_str = str, \
892 };
893
894 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
895 static struct perf_pmu_events_ht_attr event_attr_##v = { \
896 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
897 .id = 0, \
898 .event_str_noht = noht, \
899 .event_str_ht = ht, \
900 }
901
902 struct pmu *x86_get_pmu(unsigned int cpu);
903 extern struct x86_pmu x86_pmu __read_mostly;
904
task_context_opt(void * ctx)905 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
906 {
907 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
908 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
909
910 return &((struct x86_perf_task_context *)ctx)->opt;
911 }
912
x86_pmu_has_lbr_callstack(void)913 static inline bool x86_pmu_has_lbr_callstack(void)
914 {
915 return x86_pmu.lbr_sel_map &&
916 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
917 }
918
919 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
920
921 int x86_perf_event_set_period(struct perf_event *event);
922
923 /*
924 * Generalized hw caching related hw_event table, filled
925 * in on a per model basis. A value of 0 means
926 * 'not supported', -1 means 'hw_event makes no sense on
927 * this CPU', any other value means the raw hw_event
928 * ID.
929 */
930
931 #define C(x) PERF_COUNT_HW_CACHE_##x
932
933 extern u64 __read_mostly hw_cache_event_ids
934 [PERF_COUNT_HW_CACHE_MAX]
935 [PERF_COUNT_HW_CACHE_OP_MAX]
936 [PERF_COUNT_HW_CACHE_RESULT_MAX];
937 extern u64 __read_mostly hw_cache_extra_regs
938 [PERF_COUNT_HW_CACHE_MAX]
939 [PERF_COUNT_HW_CACHE_OP_MAX]
940 [PERF_COUNT_HW_CACHE_RESULT_MAX];
941
942 u64 x86_perf_event_update(struct perf_event *event);
943
x86_pmu_config_addr(int index)944 static inline unsigned int x86_pmu_config_addr(int index)
945 {
946 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
947 x86_pmu.addr_offset(index, true) : index);
948 }
949
x86_pmu_event_addr(int index)950 static inline unsigned int x86_pmu_event_addr(int index)
951 {
952 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
953 x86_pmu.addr_offset(index, false) : index);
954 }
955
x86_pmu_rdpmc_index(int index)956 static inline int x86_pmu_rdpmc_index(int index)
957 {
958 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
959 }
960
961 int x86_add_exclusive(unsigned int what);
962
963 void x86_del_exclusive(unsigned int what);
964
965 int x86_reserve_hardware(void);
966
967 void x86_release_hardware(void);
968
969 int x86_pmu_max_precise(void);
970
971 void hw_perf_lbr_event_destroy(struct perf_event *event);
972
973 int x86_setup_perfctr(struct perf_event *event);
974
975 int x86_pmu_hw_config(struct perf_event *event);
976
977 void x86_pmu_disable_all(void);
978
is_counter_pair(struct hw_perf_event * hwc)979 static inline bool is_counter_pair(struct hw_perf_event *hwc)
980 {
981 return hwc->flags & PERF_X86_EVENT_PAIR;
982 }
983
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)984 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
985 u64 enable_mask)
986 {
987 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
988
989 if (hwc->extra_reg.reg)
990 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
991
992 /*
993 * Add enabled Merge event on next counter
994 * if large increment event being enabled on this counter
995 */
996 if (is_counter_pair(hwc))
997 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
998
999 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1000 }
1001
1002 void x86_pmu_enable_all(int added);
1003
1004 int perf_assign_events(struct event_constraint **constraints, int n,
1005 int wmin, int wmax, int gpmax, int *assign);
1006 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1007
1008 void x86_pmu_stop(struct perf_event *event, int flags);
1009
x86_pmu_disable_event(struct perf_event * event)1010 static inline void x86_pmu_disable_event(struct perf_event *event)
1011 {
1012 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1013 struct hw_perf_event *hwc = &event->hw;
1014
1015 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
1016
1017 if (is_counter_pair(hwc))
1018 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1019 }
1020
1021 void x86_pmu_enable_event(struct perf_event *event);
1022
1023 int x86_pmu_handle_irq(struct pt_regs *regs);
1024
1025 extern struct event_constraint emptyconstraint;
1026
1027 extern struct event_constraint unconstrained;
1028
kernel_ip(unsigned long ip)1029 static inline bool kernel_ip(unsigned long ip)
1030 {
1031 #ifdef CONFIG_X86_32
1032 return ip > PAGE_OFFSET;
1033 #else
1034 return (long)ip < 0;
1035 #endif
1036 }
1037
1038 /*
1039 * Not all PMUs provide the right context information to place the reported IP
1040 * into full context. Specifically segment registers are typically not
1041 * supplied.
1042 *
1043 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1044 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1045 * to reflect this.
1046 *
1047 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1048 * much we can do about that but pray and treat it like a linear address.
1049 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)1050 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1051 {
1052 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1053 if (regs->flags & X86_VM_MASK)
1054 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1055 regs->ip = ip;
1056 }
1057
1058 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1059 ssize_t intel_event_sysfs_show(char *page, u64 config);
1060
1061 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1062 char *page);
1063 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1064 char *page);
1065
1066 #ifdef CONFIG_CPU_SUP_AMD
1067
1068 int amd_pmu_init(void);
1069
1070 #else /* CONFIG_CPU_SUP_AMD */
1071
amd_pmu_init(void)1072 static inline int amd_pmu_init(void)
1073 {
1074 return 0;
1075 }
1076
1077 #endif /* CONFIG_CPU_SUP_AMD */
1078
is_pebs_pt(struct perf_event * event)1079 static inline int is_pebs_pt(struct perf_event *event)
1080 {
1081 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1082 }
1083
1084 #ifdef CONFIG_CPU_SUP_INTEL
1085
intel_pmu_has_bts_period(struct perf_event * event,u64 period)1086 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1087 {
1088 struct hw_perf_event *hwc = &event->hw;
1089 unsigned int hw_event, bts_event;
1090
1091 if (event->attr.freq)
1092 return false;
1093
1094 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1095 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1096
1097 return hw_event == bts_event && period == 1;
1098 }
1099
intel_pmu_has_bts(struct perf_event * event)1100 static inline bool intel_pmu_has_bts(struct perf_event *event)
1101 {
1102 struct hw_perf_event *hwc = &event->hw;
1103
1104 return intel_pmu_has_bts_period(event, hwc->sample_period);
1105 }
1106
1107 int intel_pmu_save_and_restart(struct perf_event *event);
1108
1109 struct event_constraint *
1110 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1111 struct perf_event *event);
1112
1113 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1114 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1115
1116 int intel_pmu_init(void);
1117
1118 void init_debug_store_on_cpu(int cpu);
1119
1120 void fini_debug_store_on_cpu(int cpu);
1121
1122 void release_ds_buffers(void);
1123
1124 void reserve_ds_buffers(void);
1125
1126 void release_lbr_buffers(void);
1127
1128 void reserve_lbr_buffers(void);
1129
1130 extern struct event_constraint bts_constraint;
1131 extern struct event_constraint vlbr_constraint;
1132
1133 void intel_pmu_enable_bts(u64 config);
1134
1135 void intel_pmu_disable_bts(void);
1136
1137 int intel_pmu_drain_bts_buffer(void);
1138
1139 extern struct event_constraint intel_core2_pebs_event_constraints[];
1140
1141 extern struct event_constraint intel_atom_pebs_event_constraints[];
1142
1143 extern struct event_constraint intel_slm_pebs_event_constraints[];
1144
1145 extern struct event_constraint intel_glm_pebs_event_constraints[];
1146
1147 extern struct event_constraint intel_glp_pebs_event_constraints[];
1148
1149 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1150
1151 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1152
1153 extern struct event_constraint intel_snb_pebs_event_constraints[];
1154
1155 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1156
1157 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1158
1159 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1160
1161 extern struct event_constraint intel_skl_pebs_event_constraints[];
1162
1163 extern struct event_constraint intel_icl_pebs_event_constraints[];
1164
1165 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1166
1167 void intel_pmu_pebs_add(struct perf_event *event);
1168
1169 void intel_pmu_pebs_del(struct perf_event *event);
1170
1171 void intel_pmu_pebs_enable(struct perf_event *event);
1172
1173 void intel_pmu_pebs_disable(struct perf_event *event);
1174
1175 void intel_pmu_pebs_enable_all(void);
1176
1177 void intel_pmu_pebs_disable_all(void);
1178
1179 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1180
1181 void intel_pmu_auto_reload_read(struct perf_event *event);
1182
1183 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1184
1185 void intel_ds_init(void);
1186
1187 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1188 struct perf_event_context *next);
1189
1190 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1191
1192 u64 lbr_from_signext_quirk_wr(u64 val);
1193
1194 void intel_pmu_lbr_reset(void);
1195
1196 void intel_pmu_lbr_reset_32(void);
1197
1198 void intel_pmu_lbr_reset_64(void);
1199
1200 void intel_pmu_lbr_add(struct perf_event *event);
1201
1202 void intel_pmu_lbr_del(struct perf_event *event);
1203
1204 void intel_pmu_lbr_enable_all(bool pmi);
1205
1206 void intel_pmu_lbr_disable_all(void);
1207
1208 void intel_pmu_lbr_read(void);
1209
1210 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1211
1212 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1213
1214 void intel_pmu_lbr_save(void *ctx);
1215
1216 void intel_pmu_lbr_restore(void *ctx);
1217
1218 void intel_pmu_lbr_init_core(void);
1219
1220 void intel_pmu_lbr_init_nhm(void);
1221
1222 void intel_pmu_lbr_init_atom(void);
1223
1224 void intel_pmu_lbr_init_slm(void);
1225
1226 void intel_pmu_lbr_init_snb(void);
1227
1228 void intel_pmu_lbr_init_hsw(void);
1229
1230 void intel_pmu_lbr_init_skl(void);
1231
1232 void intel_pmu_lbr_init_knl(void);
1233
1234 void intel_pmu_arch_lbr_init(void);
1235
1236 void intel_pmu_pebs_data_source_nhm(void);
1237
1238 void intel_pmu_pebs_data_source_skl(bool pmem);
1239
1240 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1241
1242 void intel_pt_interrupt(void);
1243
1244 int intel_bts_interrupt(void);
1245
1246 void intel_bts_enable_local(void);
1247
1248 void intel_bts_disable_local(void);
1249
1250 int p4_pmu_init(void);
1251
1252 int p6_pmu_init(void);
1253
1254 int knc_pmu_init(void);
1255
is_ht_workaround_enabled(void)1256 static inline int is_ht_workaround_enabled(void)
1257 {
1258 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1259 }
1260
1261 #else /* CONFIG_CPU_SUP_INTEL */
1262
reserve_ds_buffers(void)1263 static inline void reserve_ds_buffers(void)
1264 {
1265 }
1266
release_ds_buffers(void)1267 static inline void release_ds_buffers(void)
1268 {
1269 }
1270
release_lbr_buffers(void)1271 static inline void release_lbr_buffers(void)
1272 {
1273 }
1274
reserve_lbr_buffers(void)1275 static inline void reserve_lbr_buffers(void)
1276 {
1277 }
1278
intel_pmu_init(void)1279 static inline int intel_pmu_init(void)
1280 {
1281 return 0;
1282 }
1283
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1284 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1285 {
1286 return 0;
1287 }
1288
intel_cpuc_finish(struct cpu_hw_events * cpuc)1289 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1290 {
1291 }
1292
is_ht_workaround_enabled(void)1293 static inline int is_ht_workaround_enabled(void)
1294 {
1295 return 0;
1296 }
1297 #endif /* CONFIG_CPU_SUP_INTEL */
1298
1299 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1300 int zhaoxin_pmu_init(void);
1301 #else
zhaoxin_pmu_init(void)1302 static inline int zhaoxin_pmu_init(void)
1303 {
1304 return 0;
1305 }
1306 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/
1307