1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef RVU_H
12 #define RVU_H
13
14 #include <linux/pci.h>
15 #include "rvu_struct.h"
16 #include "common.h"
17 #include "mbox.h"
18
19 /* PCI device IDs */
20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
21
22 /* Subsystem Device ID */
23 #define PCI_SUBSYS_DEVID_96XX 0xB200
24
25 /* PCI BAR nos */
26 #define PCI_AF_REG_BAR_NUM 0
27 #define PCI_PF_REG_BAR_NUM 2
28 #define PCI_MBOX_BAR_NUM 4
29
30 #define NAME_SIZE 32
31
32 /* PF_FUNC */
33 #define RVU_PFVF_PF_SHIFT 10
34 #define RVU_PFVF_PF_MASK 0x3F
35 #define RVU_PFVF_FUNC_SHIFT 0
36 #define RVU_PFVF_FUNC_MASK 0x3FF
37
38 #ifdef CONFIG_DEBUG_FS
39 struct dump_ctx {
40 int lf;
41 int id;
42 bool all;
43 };
44
45 struct rvu_debugfs {
46 struct dentry *root;
47 struct dentry *cgx_root;
48 struct dentry *cgx;
49 struct dentry *lmac;
50 struct dentry *npa;
51 struct dentry *nix;
52 struct dentry *npc;
53 struct dump_ctx npa_aura_ctx;
54 struct dump_ctx npa_pool_ctx;
55 struct dump_ctx nix_cq_ctx;
56 struct dump_ctx nix_rq_ctx;
57 struct dump_ctx nix_sq_ctx;
58 int npa_qsize_id;
59 int nix_qsize_id;
60 };
61 #endif
62
63 struct rvu_work {
64 struct work_struct work;
65 struct rvu *rvu;
66 int num_msgs;
67 int up_num_msgs;
68 };
69
70 struct rsrc_bmap {
71 unsigned long *bmap; /* Pointer to resource bitmap */
72 u16 max; /* Max resource id or count */
73 };
74
75 struct rvu_block {
76 struct rsrc_bmap lf;
77 struct admin_queue *aq; /* NIX/NPA AQ */
78 u16 *fn_map; /* LF to pcifunc mapping */
79 bool multislot;
80 bool implemented;
81 u8 addr; /* RVU_BLOCK_ADDR_E */
82 u8 type; /* RVU_BLOCK_TYPE_E */
83 u8 lfshift;
84 u64 lookup_reg;
85 u64 pf_lfcnt_reg;
86 u64 vf_lfcnt_reg;
87 u64 lfcfg_reg;
88 u64 msixcfg_reg;
89 u64 lfreset_reg;
90 unsigned char name[NAME_SIZE];
91 };
92
93 struct nix_mcast {
94 struct qmem *mce_ctx;
95 struct qmem *mcast_buf;
96 int replay_pkind;
97 int next_free_mce;
98 struct mutex mce_lock; /* Serialize MCE updates */
99 };
100
101 struct nix_mce_list {
102 struct hlist_head head;
103 int count;
104 int max;
105 };
106
107 struct npc_mcam {
108 struct rsrc_bmap counters;
109 struct mutex lock; /* MCAM entries and counters update lock */
110 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
111 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
112 u16 bmap_entries; /* Number of unreserved MCAM entries */
113 u16 bmap_fcnt; /* MCAM entries free count */
114 u16 *entry2pfvf_map;
115 u16 *entry2cntr_map;
116 u16 *cntr2pfvf_map;
117 u16 *cntr_refcnt;
118 u8 keysize; /* MCAM keysize 112/224/448 bits */
119 u8 banks; /* Number of MCAM banks */
120 u8 banks_per_entry;/* Number of keywords in key */
121 u16 banksize; /* Number of MCAM entries in each bank */
122 u16 total_entries; /* Total number of MCAM entries */
123 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
124 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
125 u16 lprio_count;
126 u16 lprio_start;
127 u16 hprio_count;
128 u16 hprio_end;
129 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
130 };
131
132 /* Structure for per RVU func info ie PF/VF */
133 struct rvu_pfvf {
134 bool npalf; /* Only one NPALF per RVU_FUNC */
135 bool nixlf; /* Only one NIXLF per RVU_FUNC */
136 u16 sso;
137 u16 ssow;
138 u16 cptlfs;
139 u16 timlfs;
140 u16 cpt1_lfs;
141 u8 cgx_lmac;
142
143 /* Block LF's MSIX vector info */
144 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
145 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
146 u16 *msix_lfmap; /* Vector to block LF mapping */
147
148 /* NPA contexts */
149 struct qmem *aura_ctx;
150 struct qmem *pool_ctx;
151 struct qmem *npa_qints_ctx;
152 unsigned long *aura_bmap;
153 unsigned long *pool_bmap;
154
155 /* NIX contexts */
156 struct qmem *rq_ctx;
157 struct qmem *sq_ctx;
158 struct qmem *cq_ctx;
159 struct qmem *rss_ctx;
160 struct qmem *cq_ints_ctx;
161 struct qmem *nix_qints_ctx;
162 unsigned long *sq_bmap;
163 unsigned long *rq_bmap;
164 unsigned long *cq_bmap;
165
166 u16 rx_chan_base;
167 u16 tx_chan_base;
168 u8 rx_chan_cnt; /* total number of RX channels */
169 u8 tx_chan_cnt; /* total number of TX channels */
170 u16 maxlen;
171 u16 minlen;
172
173 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
174
175 /* Broadcast pkt replication info */
176 u16 bcast_mce_idx;
177 struct nix_mce_list bcast_mce_list;
178
179 /* VLAN offload */
180 struct mcam_entry entry;
181 int rxvlan_index;
182 bool rxvlan;
183
184 bool cgx_in_use; /* this PF/VF using CGX? */
185 int cgx_users; /* number of cgx users - used only by PFs */
186
187 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
188 };
189
190 struct nix_txsch {
191 struct rsrc_bmap schq;
192 u8 lvl;
193 #define NIX_TXSCHQ_FREE BIT_ULL(1)
194 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
195 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
196 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
197 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
198 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
199 u32 *pfvf_map;
200 };
201
202 struct nix_mark_format {
203 u8 total;
204 u8 in_use;
205 u32 *cfg;
206 };
207
208 struct npc_pkind {
209 struct rsrc_bmap rsrc;
210 u32 *pfchan_map;
211 };
212
213 struct nix_flowkey {
214 #define NIX_FLOW_KEY_ALG_MAX 32
215 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
216 int in_use;
217 };
218
219 struct nix_lso {
220 u8 total;
221 u8 in_use;
222 };
223
224 struct nix_hw {
225 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
226 struct nix_mcast mcast;
227 struct nix_flowkey flowkey;
228 struct nix_mark_format mark_format;
229 struct nix_lso lso;
230 };
231
232 /* RVU block's capabilities or functionality,
233 * which vary by silicon version/skew.
234 */
235 struct hw_cap {
236 /* Transmit side supported functionality */
237 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
238 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
239 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
240 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
241 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
242 bool nix_shaping; /* Is shaping and coloring supported */
243 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
244 bool nix_rx_multicast; /* Rx packet replication support */
245 };
246
247 struct rvu_hwinfo {
248 u8 total_pfs; /* MAX RVU PFs HW supports */
249 u16 total_vfs; /* Max RVU VFs HW supports */
250 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
251 u8 cgx;
252 u8 lmac_per_cgx;
253 u8 cgx_links;
254 u8 lbk_links;
255 u8 sdp_links;
256 u8 npc_kpus; /* No of parser units */
257
258 struct hw_cap cap;
259 struct rvu_block block[BLK_COUNT]; /* Block info */
260 struct nix_hw *nix0;
261 struct npc_pkind pkind;
262 struct npc_mcam mcam;
263 };
264
265 struct mbox_wq_info {
266 struct otx2_mbox mbox;
267 struct rvu_work *mbox_wrk;
268
269 struct otx2_mbox mbox_up;
270 struct rvu_work *mbox_wrk_up;
271
272 struct workqueue_struct *mbox_wq;
273 };
274
275 struct rvu_fwdata {
276 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
277 #define RVU_FWDATA_VERSION 0x0001
278 u32 header_magic;
279 u32 version; /* version id */
280
281 /* MAC address */
282 #define PF_MACNUM_MAX 32
283 #define VF_MACNUM_MAX 256
284 u64 pf_macs[PF_MACNUM_MAX];
285 u64 vf_macs[VF_MACNUM_MAX];
286 u64 sclk;
287 u64 rclk;
288 u64 mcam_addr;
289 u64 mcam_sz;
290 u64 msixtr_base;
291 #define FWDATA_RESERVED_MEM 1023
292 u64 reserved[FWDATA_RESERVED_MEM];
293 };
294
295 struct ptp;
296
297 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
298 * source where it came from.
299 */
300 struct npc_kpu_profile_adapter {
301 const char *name;
302 u64 version;
303 const struct npc_lt_def_cfg *lt_def;
304 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
305 const struct npc_kpu_profile *kpu; /* array[kpus] */
306 const struct npc_mcam_kex *mkex;
307 size_t pkinds;
308 size_t kpus;
309 };
310
311 struct rvu {
312 void __iomem *afreg_base;
313 void __iomem *pfreg_base;
314 struct pci_dev *pdev;
315 struct device *dev;
316 struct rvu_hwinfo *hw;
317 struct rvu_pfvf *pf;
318 struct rvu_pfvf *hwvf;
319 struct mutex rsrc_lock; /* Serialize resource alloc/free */
320 int vfs; /* Number of VFs attached to RVU */
321
322 /* Mbox */
323 struct mbox_wq_info afpf_wq_info;
324 struct mbox_wq_info afvf_wq_info;
325
326 /* PF FLR */
327 struct rvu_work *flr_wrk;
328 struct workqueue_struct *flr_wq;
329 struct mutex flr_lock; /* Serialize FLRs */
330
331 /* MSI-X */
332 u16 num_vec;
333 char *irq_name;
334 bool *irq_allocated;
335 dma_addr_t msix_base_iova;
336 u64 msixtr_base_phy; /* Register reset value */
337
338 /* CGX */
339 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
340 u8 cgx_mapped_pfs;
341 u8 cgx_cnt_max; /* CGX port count max */
342 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
343 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
344 * every cgx lmac port
345 */
346 unsigned long pf_notify_bmap; /* Flags for PF notification */
347 void **cgx_idmap; /* cgx id to cgx data map table */
348 struct work_struct cgx_evh_work;
349 struct workqueue_struct *cgx_evh_wq;
350 spinlock_t cgx_evq_lock; /* cgx event queue lock */
351 struct list_head cgx_evq_head; /* cgx event queue head */
352 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
353
354 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
355
356 /* Firmware data */
357 struct rvu_fwdata *fwdata;
358
359 /* NPC KPU data */
360 struct npc_kpu_profile_adapter kpu;
361
362 struct ptp *ptp;
363
364 #ifdef CONFIG_DEBUG_FS
365 struct rvu_debugfs rvu_dbg;
366 #endif
367 };
368
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)369 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
370 {
371 writeq(val, rvu->afreg_base + ((block << 28) | offset));
372 }
373
rvu_read64(struct rvu * rvu,u64 block,u64 offset)374 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
375 {
376 return readq(rvu->afreg_base + ((block << 28) | offset));
377 }
378
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)379 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
380 {
381 writeq(val, rvu->pfreg_base + offset);
382 }
383
rvupf_read64(struct rvu * rvu,u64 offset)384 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
385 {
386 return readq(rvu->pfreg_base + offset);
387 }
388
389 /* Silicon revisions */
is_rvu_96xx_A0(struct rvu * rvu)390 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
391 {
392 struct pci_dev *pdev = rvu->pdev;
393
394 return (pdev->revision == 0x00) &&
395 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
396 }
397
is_rvu_96xx_B0(struct rvu * rvu)398 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
399 {
400 struct pci_dev *pdev = rvu->pdev;
401
402 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) &&
403 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
404 }
405
406 /* Function Prototypes
407 * RVU
408 */
is_afvf(u16 pcifunc)409 static inline int is_afvf(u16 pcifunc)
410 {
411 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
412 }
413
is_rvu_fwdata_valid(struct rvu * rvu)414 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
415 {
416 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
417 (rvu->fwdata->version == RVU_FWDATA_VERSION);
418 }
419
420 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
421 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
422 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
423 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
424 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
425 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
426 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
427 int rvu_get_pf(u16 pcifunc);
428 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
429 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
430 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
431 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
432 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
433 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
434 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
435 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
436
437 /* RVU HW reg validation */
438 enum regmap_block {
439 TXSCHQ_HWREGMAP = 0,
440 MAX_HWREGMAP,
441 };
442
443 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
444
445 /* NPA/NIX AQ APIs */
446 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
447 int qsize, int inst_size, int res_size);
448 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
449
450 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)451 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
452 {
453 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
454 }
455
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)456 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
457 {
458 *cgx_id = (map >> 4) & 0xF;
459 *lmac_id = (map & 0xF);
460 }
461
462 #define M(_name, _id, fn_name, req, rsp) \
463 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
464 MBOX_MESSAGES
465 #undef M
466
467 int rvu_cgx_init(struct rvu *rvu);
468 int rvu_cgx_exit(struct rvu *rvu);
469 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
470 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
471 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
472 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
473 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
474 int rxtxflag, u64 *stat);
475 /* NPA APIs */
476 int rvu_npa_init(struct rvu *rvu);
477 void rvu_npa_freemem(struct rvu *rvu);
478 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
479 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
480 struct npa_aq_enq_rsp *rsp);
481
482 /* NIX APIs */
483 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
484 int rvu_nix_init(struct rvu *rvu);
485 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
486 int blkaddr, u32 cfg);
487 void rvu_nix_freemem(struct rvu *rvu);
488 int rvu_get_nixlf_count(struct rvu *rvu);
489 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
490 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
491 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
492
493 /* NPC APIs */
494 int rvu_npc_init(struct rvu *rvu);
495 void rvu_npc_freemem(struct rvu *rvu);
496 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
497 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
498 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
499 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
500 int nixlf, u64 chan, u8 *mac_addr);
501 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
502 int nixlf, u64 chan, bool allmulti);
503 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
504 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
505 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
506 int nixlf, u64 chan);
507 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable);
508 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf);
509 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
510 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
511 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
512 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
513 int group, int alg_idx, int mcam_index);
514 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
515 int blkaddr, int *alloc_cnt,
516 int *enable_cnt);
517 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
518 int blkaddr, int *alloc_cnt,
519 int *enable_cnt);
520
521 #ifdef CONFIG_DEBUG_FS
522 void rvu_dbg_init(struct rvu *rvu);
523 void rvu_dbg_exit(struct rvu *rvu);
524 #else
rvu_dbg_init(struct rvu * rvu)525 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)526 static inline void rvu_dbg_exit(struct rvu *rvu) {}
527 #endif
528 #endif /* RVU_H */
529