1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/vmalloc.h>
18 #include <linux/wait.h>
19 #include "internal.h"
20
21 const char * const mhi_ee_str[MHI_EE_MAX] = {
22 [MHI_EE_PBL] = "PBL",
23 [MHI_EE_SBL] = "SBL",
24 [MHI_EE_AMSS] = "AMSS",
25 [MHI_EE_RDDM] = "RDDM",
26 [MHI_EE_WFW] = "WFW",
27 [MHI_EE_PTHRU] = "PASS THRU",
28 [MHI_EE_EDL] = "EDL",
29 [MHI_EE_DISABLE_TRANSITION] = "DISABLE",
30 [MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED",
31 };
32
33 const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
34 [DEV_ST_TRANSITION_PBL] = "PBL",
35 [DEV_ST_TRANSITION_READY] = "READY",
36 [DEV_ST_TRANSITION_SBL] = "SBL",
37 [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION_MODE",
38 [DEV_ST_TRANSITION_SYS_ERR] = "SYS_ERR",
39 [DEV_ST_TRANSITION_DISABLE] = "DISABLE",
40 };
41
42 const char * const mhi_state_str[MHI_STATE_MAX] = {
43 [MHI_STATE_RESET] = "RESET",
44 [MHI_STATE_READY] = "READY",
45 [MHI_STATE_M0] = "M0",
46 [MHI_STATE_M1] = "M1",
47 [MHI_STATE_M2] = "M2",
48 [MHI_STATE_M3] = "M3",
49 [MHI_STATE_M3_FAST] = "M3_FAST",
50 [MHI_STATE_BHI] = "BHI",
51 [MHI_STATE_SYS_ERR] = "SYS_ERR",
52 };
53
54 static const char * const mhi_pm_state_str[] = {
55 [MHI_PM_STATE_DISABLE] = "DISABLE",
56 [MHI_PM_STATE_POR] = "POR",
57 [MHI_PM_STATE_M0] = "M0",
58 [MHI_PM_STATE_M2] = "M2",
59 [MHI_PM_STATE_M3_ENTER] = "M?->M3",
60 [MHI_PM_STATE_M3] = "M3",
61 [MHI_PM_STATE_M3_EXIT] = "M3->M0",
62 [MHI_PM_STATE_FW_DL_ERR] = "FW DL Error",
63 [MHI_PM_STATE_SYS_ERR_DETECT] = "SYS_ERR Detect",
64 [MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS_ERR Process",
65 [MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process",
66 [MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "LD or Error Fatal Detect",
67 };
68
to_mhi_pm_state_str(enum mhi_pm_state state)69 const char *to_mhi_pm_state_str(enum mhi_pm_state state)
70 {
71 int index = find_last_bit((unsigned long *)&state, 32);
72
73 if (index >= ARRAY_SIZE(mhi_pm_state_str))
74 return "Invalid State";
75
76 return mhi_pm_state_str[index];
77 }
78
serial_number_show(struct device * dev,struct device_attribute * attr,char * buf)79 static ssize_t serial_number_show(struct device *dev,
80 struct device_attribute *attr,
81 char *buf)
82 {
83 struct mhi_device *mhi_dev = to_mhi_device(dev);
84 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
85
86 return snprintf(buf, PAGE_SIZE, "Serial Number: %u\n",
87 mhi_cntrl->serial_number);
88 }
89 static DEVICE_ATTR_RO(serial_number);
90
oem_pk_hash_show(struct device * dev,struct device_attribute * attr,char * buf)91 static ssize_t oem_pk_hash_show(struct device *dev,
92 struct device_attribute *attr,
93 char *buf)
94 {
95 struct mhi_device *mhi_dev = to_mhi_device(dev);
96 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
97 int i, cnt = 0;
98
99 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++)
100 cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
101 "OEMPKHASH[%d]: 0x%x\n", i,
102 mhi_cntrl->oem_pk_hash[i]);
103
104 return cnt;
105 }
106 static DEVICE_ATTR_RO(oem_pk_hash);
107
108 static struct attribute *mhi_dev_attrs[] = {
109 &dev_attr_serial_number.attr,
110 &dev_attr_oem_pk_hash.attr,
111 NULL,
112 };
113 ATTRIBUTE_GROUPS(mhi_dev);
114
115 /* MHI protocol requires the transfer ring to be aligned with ring length */
mhi_alloc_aligned_ring(struct mhi_controller * mhi_cntrl,struct mhi_ring * ring,u64 len)116 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,
117 struct mhi_ring *ring,
118 u64 len)
119 {
120 ring->alloc_size = len + (len - 1);
121 ring->pre_aligned = mhi_alloc_coherent(mhi_cntrl, ring->alloc_size,
122 &ring->dma_handle, GFP_KERNEL);
123 if (!ring->pre_aligned)
124 return -ENOMEM;
125
126 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1);
127 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle);
128
129 return 0;
130 }
131
mhi_deinit_free_irq(struct mhi_controller * mhi_cntrl)132 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)
133 {
134 int i;
135 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
136
137 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
138 if (mhi_event->offload_ev)
139 continue;
140
141 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
142 }
143
144 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
145 }
146
mhi_init_irq_setup(struct mhi_controller * mhi_cntrl)147 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
148 {
149 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
150 struct device *dev = &mhi_cntrl->mhi_dev->dev;
151 int i, ret;
152
153 /* Setup BHI_INTVEC IRQ */
154 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,
155 mhi_intvec_threaded_handler,
156 IRQF_SHARED | IRQF_NO_SUSPEND,
157 "bhi", mhi_cntrl);
158 if (ret)
159 return ret;
160
161 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
162 if (mhi_event->offload_ev)
163 continue;
164
165 if (mhi_event->irq >= mhi_cntrl->nr_irqs) {
166 dev_err(dev, "irq %d not available for event ring\n",
167 mhi_event->irq);
168 ret = -EINVAL;
169 goto error_request;
170 }
171
172 ret = request_irq(mhi_cntrl->irq[mhi_event->irq],
173 mhi_irq_handler,
174 IRQF_SHARED | IRQF_NO_SUSPEND,
175 "mhi", mhi_event);
176 if (ret) {
177 dev_err(dev, "Error requesting irq:%d for ev:%d\n",
178 mhi_cntrl->irq[mhi_event->irq], i);
179 goto error_request;
180 }
181 }
182
183 return 0;
184
185 error_request:
186 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
187 if (mhi_event->offload_ev)
188 continue;
189
190 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
191 }
192 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
193
194 return ret;
195 }
196
mhi_deinit_dev_ctxt(struct mhi_controller * mhi_cntrl)197 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)
198 {
199 int i;
200 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;
201 struct mhi_cmd *mhi_cmd;
202 struct mhi_event *mhi_event;
203 struct mhi_ring *ring;
204
205 mhi_cmd = mhi_cntrl->mhi_cmd;
206 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) {
207 ring = &mhi_cmd->ring;
208 mhi_free_coherent(mhi_cntrl, ring->alloc_size,
209 ring->pre_aligned, ring->dma_handle);
210 ring->base = NULL;
211 ring->iommu_base = 0;
212 }
213
214 mhi_free_coherent(mhi_cntrl,
215 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
216 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
217
218 mhi_event = mhi_cntrl->mhi_event;
219 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
220 if (mhi_event->offload_ev)
221 continue;
222
223 ring = &mhi_event->ring;
224 mhi_free_coherent(mhi_cntrl, ring->alloc_size,
225 ring->pre_aligned, ring->dma_handle);
226 ring->base = NULL;
227 ring->iommu_base = 0;
228 }
229
230 mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->er_ctxt) *
231 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
232 mhi_ctxt->er_ctxt_addr);
233
234 mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->chan_ctxt) *
235 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
236 mhi_ctxt->chan_ctxt_addr);
237
238 kfree(mhi_ctxt);
239 mhi_cntrl->mhi_ctxt = NULL;
240 }
241
mhi_init_dev_ctxt(struct mhi_controller * mhi_cntrl)242 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
243 {
244 struct mhi_ctxt *mhi_ctxt;
245 struct mhi_chan_ctxt *chan_ctxt;
246 struct mhi_event_ctxt *er_ctxt;
247 struct mhi_cmd_ctxt *cmd_ctxt;
248 struct mhi_chan *mhi_chan;
249 struct mhi_event *mhi_event;
250 struct mhi_cmd *mhi_cmd;
251 u32 tmp;
252 int ret = -ENOMEM, i;
253
254 atomic_set(&mhi_cntrl->dev_wake, 0);
255 atomic_set(&mhi_cntrl->pending_pkts, 0);
256
257 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL);
258 if (!mhi_ctxt)
259 return -ENOMEM;
260
261 /* Setup channel ctxt */
262 mhi_ctxt->chan_ctxt = mhi_alloc_coherent(mhi_cntrl,
263 sizeof(*mhi_ctxt->chan_ctxt) *
264 mhi_cntrl->max_chan,
265 &mhi_ctxt->chan_ctxt_addr,
266 GFP_KERNEL);
267 if (!mhi_ctxt->chan_ctxt)
268 goto error_alloc_chan_ctxt;
269
270 mhi_chan = mhi_cntrl->mhi_chan;
271 chan_ctxt = mhi_ctxt->chan_ctxt;
272 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {
273 /* Skip if it is an offload channel */
274 if (mhi_chan->offload_ch)
275 continue;
276
277 tmp = chan_ctxt->chcfg;
278 tmp &= ~CHAN_CTX_CHSTATE_MASK;
279 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
280 tmp &= ~CHAN_CTX_BRSTMODE_MASK;
281 tmp |= (mhi_chan->db_cfg.brstmode << CHAN_CTX_BRSTMODE_SHIFT);
282 tmp &= ~CHAN_CTX_POLLCFG_MASK;
283 tmp |= (mhi_chan->db_cfg.pollcfg << CHAN_CTX_POLLCFG_SHIFT);
284 chan_ctxt->chcfg = tmp;
285
286 chan_ctxt->chtype = mhi_chan->type;
287 chan_ctxt->erindex = mhi_chan->er_index;
288
289 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
290 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;
291 }
292
293 /* Setup event context */
294 mhi_ctxt->er_ctxt = mhi_alloc_coherent(mhi_cntrl,
295 sizeof(*mhi_ctxt->er_ctxt) *
296 mhi_cntrl->total_ev_rings,
297 &mhi_ctxt->er_ctxt_addr,
298 GFP_KERNEL);
299 if (!mhi_ctxt->er_ctxt)
300 goto error_alloc_er_ctxt;
301
302 er_ctxt = mhi_ctxt->er_ctxt;
303 mhi_event = mhi_cntrl->mhi_event;
304 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
305 mhi_event++) {
306 struct mhi_ring *ring = &mhi_event->ring;
307
308 /* Skip if it is an offload event */
309 if (mhi_event->offload_ev)
310 continue;
311
312 tmp = er_ctxt->intmod;
313 tmp &= ~EV_CTX_INTMODC_MASK;
314 tmp &= ~EV_CTX_INTMODT_MASK;
315 tmp |= (mhi_event->intmod << EV_CTX_INTMODT_SHIFT);
316 er_ctxt->intmod = tmp;
317
318 er_ctxt->ertype = MHI_ER_TYPE_VALID;
319 er_ctxt->msivec = mhi_event->irq;
320 mhi_event->db_cfg.db_mode = true;
321
322 ring->el_size = sizeof(struct mhi_tre);
323 ring->len = ring->el_size * ring->elements;
324 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
325 if (ret)
326 goto error_alloc_er;
327
328 /*
329 * If the read pointer equals to the write pointer, then the
330 * ring is empty
331 */
332 ring->rp = ring->wp = ring->base;
333 er_ctxt->rbase = ring->iommu_base;
334 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;
335 er_ctxt->rlen = ring->len;
336 ring->ctxt_wp = &er_ctxt->wp;
337 }
338
339 /* Setup cmd context */
340 ret = -ENOMEM;
341 mhi_ctxt->cmd_ctxt = mhi_alloc_coherent(mhi_cntrl,
342 sizeof(*mhi_ctxt->cmd_ctxt) *
343 NR_OF_CMD_RINGS,
344 &mhi_ctxt->cmd_ctxt_addr,
345 GFP_KERNEL);
346 if (!mhi_ctxt->cmd_ctxt)
347 goto error_alloc_er;
348
349 mhi_cmd = mhi_cntrl->mhi_cmd;
350 cmd_ctxt = mhi_ctxt->cmd_ctxt;
351 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
352 struct mhi_ring *ring = &mhi_cmd->ring;
353
354 ring->el_size = sizeof(struct mhi_tre);
355 ring->elements = CMD_EL_PER_RING;
356 ring->len = ring->el_size * ring->elements;
357 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
358 if (ret)
359 goto error_alloc_cmd;
360
361 ring->rp = ring->wp = ring->base;
362 cmd_ctxt->rbase = ring->iommu_base;
363 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;
364 cmd_ctxt->rlen = ring->len;
365 ring->ctxt_wp = &cmd_ctxt->wp;
366 }
367
368 mhi_cntrl->mhi_ctxt = mhi_ctxt;
369
370 return 0;
371
372 error_alloc_cmd:
373 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) {
374 struct mhi_ring *ring = &mhi_cmd->ring;
375
376 mhi_free_coherent(mhi_cntrl, ring->alloc_size,
377 ring->pre_aligned, ring->dma_handle);
378 }
379 mhi_free_coherent(mhi_cntrl,
380 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
381 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
382 i = mhi_cntrl->total_ev_rings;
383 mhi_event = mhi_cntrl->mhi_event + i;
384
385 error_alloc_er:
386 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
387 struct mhi_ring *ring = &mhi_event->ring;
388
389 if (mhi_event->offload_ev)
390 continue;
391
392 mhi_free_coherent(mhi_cntrl, ring->alloc_size,
393 ring->pre_aligned, ring->dma_handle);
394 }
395 mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->er_ctxt) *
396 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
397 mhi_ctxt->er_ctxt_addr);
398
399 error_alloc_er_ctxt:
400 mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->chan_ctxt) *
401 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
402 mhi_ctxt->chan_ctxt_addr);
403
404 error_alloc_chan_ctxt:
405 kfree(mhi_ctxt);
406
407 return ret;
408 }
409
mhi_init_mmio(struct mhi_controller * mhi_cntrl)410 int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
411 {
412 u32 val;
413 int i, ret;
414 struct mhi_chan *mhi_chan;
415 struct mhi_event *mhi_event;
416 void __iomem *base = mhi_cntrl->regs;
417 struct device *dev = &mhi_cntrl->mhi_dev->dev;
418 struct {
419 u32 offset;
420 u32 mask;
421 u32 shift;
422 u32 val;
423 } reg_info[] = {
424 {
425 CCABAP_HIGHER, U32_MAX, 0,
426 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
427 },
428 {
429 CCABAP_LOWER, U32_MAX, 0,
430 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
431 },
432 {
433 ECABAP_HIGHER, U32_MAX, 0,
434 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
435 },
436 {
437 ECABAP_LOWER, U32_MAX, 0,
438 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
439 },
440 {
441 CRCBAP_HIGHER, U32_MAX, 0,
442 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
443 },
444 {
445 CRCBAP_LOWER, U32_MAX, 0,
446 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
447 },
448 {
449 MHICFG, MHICFG_NER_MASK, MHICFG_NER_SHIFT,
450 mhi_cntrl->total_ev_rings,
451 },
452 {
453 MHICFG, MHICFG_NHWER_MASK, MHICFG_NHWER_SHIFT,
454 mhi_cntrl->hw_ev_rings,
455 },
456 {
457 MHICTRLBASE_HIGHER, U32_MAX, 0,
458 upper_32_bits(mhi_cntrl->iova_start),
459 },
460 {
461 MHICTRLBASE_LOWER, U32_MAX, 0,
462 lower_32_bits(mhi_cntrl->iova_start),
463 },
464 {
465 MHIDATABASE_HIGHER, U32_MAX, 0,
466 upper_32_bits(mhi_cntrl->iova_start),
467 },
468 {
469 MHIDATABASE_LOWER, U32_MAX, 0,
470 lower_32_bits(mhi_cntrl->iova_start),
471 },
472 {
473 MHICTRLLIMIT_HIGHER, U32_MAX, 0,
474 upper_32_bits(mhi_cntrl->iova_stop),
475 },
476 {
477 MHICTRLLIMIT_LOWER, U32_MAX, 0,
478 lower_32_bits(mhi_cntrl->iova_stop),
479 },
480 {
481 MHIDATALIMIT_HIGHER, U32_MAX, 0,
482 upper_32_bits(mhi_cntrl->iova_stop),
483 },
484 {
485 MHIDATALIMIT_LOWER, U32_MAX, 0,
486 lower_32_bits(mhi_cntrl->iova_stop),
487 },
488 { 0, 0, 0 }
489 };
490
491 dev_dbg(dev, "Initializing MHI registers\n");
492
493 /* Read channel db offset */
494 ret = mhi_read_reg_field(mhi_cntrl, base, CHDBOFF, CHDBOFF_CHDBOFF_MASK,
495 CHDBOFF_CHDBOFF_SHIFT, &val);
496 if (ret) {
497 dev_err(dev, "Unable to read CHDBOFF register\n");
498 return -EIO;
499 }
500
501 /* Setup wake db */
502 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
503 mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
504 mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);
505 mhi_cntrl->wake_set = false;
506
507 /* Setup channel db address for each channel in tre_ring */
508 mhi_chan = mhi_cntrl->mhi_chan;
509 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
510 mhi_chan->tre_ring.db_addr = base + val;
511
512 /* Read event ring db offset */
513 ret = mhi_read_reg_field(mhi_cntrl, base, ERDBOFF, ERDBOFF_ERDBOFF_MASK,
514 ERDBOFF_ERDBOFF_SHIFT, &val);
515 if (ret) {
516 dev_err(dev, "Unable to read ERDBOFF register\n");
517 return -EIO;
518 }
519
520 /* Setup event db address for each ev_ring */
521 mhi_event = mhi_cntrl->mhi_event;
522 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
523 if (mhi_event->offload_ev)
524 continue;
525
526 mhi_event->ring.db_addr = base + val;
527 }
528
529 /* Setup DB register for primary CMD rings */
530 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
531
532 /* Write to MMIO registers */
533 for (i = 0; reg_info[i].offset; i++)
534 mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
535 reg_info[i].mask, reg_info[i].shift,
536 reg_info[i].val);
537
538 return 0;
539 }
540
mhi_deinit_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)541 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
542 struct mhi_chan *mhi_chan)
543 {
544 struct mhi_ring *buf_ring;
545 struct mhi_ring *tre_ring;
546 struct mhi_chan_ctxt *chan_ctxt;
547 u32 tmp;
548
549 buf_ring = &mhi_chan->buf_ring;
550 tre_ring = &mhi_chan->tre_ring;
551 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
552
553 mhi_free_coherent(mhi_cntrl, tre_ring->alloc_size,
554 tre_ring->pre_aligned, tre_ring->dma_handle);
555 vfree(buf_ring->base);
556
557 buf_ring->base = tre_ring->base = NULL;
558 tre_ring->ctxt_wp = NULL;
559 chan_ctxt->rbase = 0;
560 chan_ctxt->rlen = 0;
561 chan_ctxt->rp = 0;
562 chan_ctxt->wp = 0;
563
564 tmp = chan_ctxt->chcfg;
565 tmp &= ~CHAN_CTX_CHSTATE_MASK;
566 tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
567 chan_ctxt->chcfg = tmp;
568
569 /* Update to all cores */
570 smp_wmb();
571 }
572
mhi_init_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)573 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
574 struct mhi_chan *mhi_chan)
575 {
576 struct mhi_ring *buf_ring;
577 struct mhi_ring *tre_ring;
578 struct mhi_chan_ctxt *chan_ctxt;
579 u32 tmp;
580 int ret;
581
582 buf_ring = &mhi_chan->buf_ring;
583 tre_ring = &mhi_chan->tre_ring;
584 tre_ring->el_size = sizeof(struct mhi_tre);
585 tre_ring->len = tre_ring->el_size * tre_ring->elements;
586 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
587 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);
588 if (ret)
589 return -ENOMEM;
590
591 buf_ring->el_size = sizeof(struct mhi_buf_info);
592 buf_ring->len = buf_ring->el_size * buf_ring->elements;
593 buf_ring->base = vzalloc(buf_ring->len);
594
595 if (!buf_ring->base) {
596 mhi_free_coherent(mhi_cntrl, tre_ring->alloc_size,
597 tre_ring->pre_aligned, tre_ring->dma_handle);
598 return -ENOMEM;
599 }
600
601 tmp = chan_ctxt->chcfg;
602 tmp &= ~CHAN_CTX_CHSTATE_MASK;
603 tmp |= (MHI_CH_STATE_ENABLED << CHAN_CTX_CHSTATE_SHIFT);
604 chan_ctxt->chcfg = tmp;
605
606 chan_ctxt->rbase = tre_ring->iommu_base;
607 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
608 chan_ctxt->rlen = tre_ring->len;
609 tre_ring->ctxt_wp = &chan_ctxt->wp;
610
611 tre_ring->rp = tre_ring->wp = tre_ring->base;
612 buf_ring->rp = buf_ring->wp = buf_ring->base;
613 mhi_chan->db_cfg.db_mode = 1;
614
615 /* Update to all cores */
616 smp_wmb();
617
618 return 0;
619 }
620
parse_ev_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)621 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
622 const struct mhi_controller_config *config)
623 {
624 struct mhi_event *mhi_event;
625 const struct mhi_event_config *event_cfg;
626 struct device *dev = mhi_cntrl->cntrl_dev;
627 int i, num;
628
629 num = config->num_events;
630 mhi_cntrl->total_ev_rings = num;
631 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event),
632 GFP_KERNEL);
633 if (!mhi_cntrl->mhi_event)
634 return -ENOMEM;
635
636 /* Populate event ring */
637 mhi_event = mhi_cntrl->mhi_event;
638 for (i = 0; i < num; i++) {
639 event_cfg = &config->event_cfg[i];
640
641 mhi_event->er_index = i;
642 mhi_event->ring.elements = event_cfg->num_elements;
643 mhi_event->intmod = event_cfg->irq_moderation_ms;
644 mhi_event->irq = event_cfg->irq;
645
646 if (event_cfg->channel != U32_MAX) {
647 /* This event ring has a dedicated channel */
648 mhi_event->chan = event_cfg->channel;
649 if (mhi_event->chan >= mhi_cntrl->max_chan) {
650 dev_err(dev,
651 "Event Ring channel not available\n");
652 goto error_ev_cfg;
653 }
654
655 mhi_event->mhi_chan =
656 &mhi_cntrl->mhi_chan[mhi_event->chan];
657 }
658
659 /* Priority is fixed to 1 for now */
660 mhi_event->priority = 1;
661
662 mhi_event->db_cfg.brstmode = event_cfg->mode;
663 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
664 goto error_ev_cfg;
665
666 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
667 mhi_event->db_cfg.process_db = mhi_db_brstmode;
668 else
669 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
670
671 mhi_event->data_type = event_cfg->data_type;
672
673 switch (mhi_event->data_type) {
674 case MHI_ER_DATA:
675 mhi_event->process_event = mhi_process_data_event_ring;
676 break;
677 case MHI_ER_CTRL:
678 mhi_event->process_event = mhi_process_ctrl_ev_ring;
679 break;
680 default:
681 dev_err(dev, "Event Ring type not supported\n");
682 goto error_ev_cfg;
683 }
684
685 mhi_event->hw_ring = event_cfg->hardware_event;
686 if (mhi_event->hw_ring)
687 mhi_cntrl->hw_ev_rings++;
688 else
689 mhi_cntrl->sw_ev_rings++;
690
691 mhi_event->cl_manage = event_cfg->client_managed;
692 mhi_event->offload_ev = event_cfg->offload_channel;
693 mhi_event++;
694 }
695
696 return 0;
697
698 error_ev_cfg:
699
700 kfree(mhi_cntrl->mhi_event);
701 return -EINVAL;
702 }
703
parse_ch_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)704 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,
705 const struct mhi_controller_config *config)
706 {
707 const struct mhi_channel_config *ch_cfg;
708 struct device *dev = mhi_cntrl->cntrl_dev;
709 int i;
710 u32 chan;
711
712 mhi_cntrl->max_chan = config->max_channels;
713
714 /*
715 * The allocation of MHI channels can exceed 32KB in some scenarios,
716 * so to avoid any memory possible allocation failures, vzalloc is
717 * used here
718 */
719 mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan *
720 sizeof(*mhi_cntrl->mhi_chan));
721 if (!mhi_cntrl->mhi_chan)
722 return -ENOMEM;
723
724 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);
725
726 /* Populate channel configurations */
727 for (i = 0; i < config->num_channels; i++) {
728 struct mhi_chan *mhi_chan;
729
730 ch_cfg = &config->ch_cfg[i];
731
732 chan = ch_cfg->num;
733 if (chan >= mhi_cntrl->max_chan) {
734 dev_err(dev, "Channel %d not available\n", chan);
735 goto error_chan_cfg;
736 }
737
738 mhi_chan = &mhi_cntrl->mhi_chan[chan];
739 mhi_chan->name = ch_cfg->name;
740 mhi_chan->chan = chan;
741
742 mhi_chan->tre_ring.elements = ch_cfg->num_elements;
743 if (!mhi_chan->tre_ring.elements)
744 goto error_chan_cfg;
745
746 /*
747 * For some channels, local ring length should be bigger than
748 * the transfer ring length due to internal logical channels
749 * in device. So host can queue much more buffers than transfer
750 * ring length. Example, RSC channels should have a larger local
751 * channel length than transfer ring length.
752 */
753 mhi_chan->buf_ring.elements = ch_cfg->local_elements;
754 if (!mhi_chan->buf_ring.elements)
755 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements;
756 mhi_chan->er_index = ch_cfg->event_ring;
757 mhi_chan->dir = ch_cfg->dir;
758
759 /*
760 * For most channels, chtype is identical to channel directions.
761 * So, if it is not defined then assign channel direction to
762 * chtype
763 */
764 mhi_chan->type = ch_cfg->type;
765 if (!mhi_chan->type)
766 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir;
767
768 mhi_chan->ee_mask = ch_cfg->ee_mask;
769 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg;
770 mhi_chan->lpm_notify = ch_cfg->lpm_notify;
771 mhi_chan->offload_ch = ch_cfg->offload_channel;
772 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch;
773 mhi_chan->pre_alloc = ch_cfg->auto_queue;
774 mhi_chan->auto_start = ch_cfg->auto_start;
775
776 /*
777 * If MHI host allocates buffers, then the channel direction
778 * should be DMA_FROM_DEVICE
779 */
780 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) {
781 dev_err(dev, "Invalid channel configuration\n");
782 goto error_chan_cfg;
783 }
784
785 /*
786 * Bi-directional and direction less channel must be an
787 * offload channel
788 */
789 if ((mhi_chan->dir == DMA_BIDIRECTIONAL ||
790 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) {
791 dev_err(dev, "Invalid channel configuration\n");
792 goto error_chan_cfg;
793 }
794
795 if (!mhi_chan->offload_ch) {
796 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell;
797 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) {
798 dev_err(dev, "Invalid Door bell mode\n");
799 goto error_chan_cfg;
800 }
801 }
802
803 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
804 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
805 else
806 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
807
808 mhi_chan->configured = true;
809
810 if (mhi_chan->lpm_notify)
811 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);
812 }
813
814 return 0;
815
816 error_chan_cfg:
817 vfree(mhi_cntrl->mhi_chan);
818
819 return -EINVAL;
820 }
821
parse_config(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)822 static int parse_config(struct mhi_controller *mhi_cntrl,
823 const struct mhi_controller_config *config)
824 {
825 int ret;
826
827 /* Parse MHI channel configuration */
828 ret = parse_ch_cfg(mhi_cntrl, config);
829 if (ret)
830 return ret;
831
832 /* Parse MHI event configuration */
833 ret = parse_ev_cfg(mhi_cntrl, config);
834 if (ret)
835 goto error_ev_cfg;
836
837 mhi_cntrl->timeout_ms = config->timeout_ms;
838 if (!mhi_cntrl->timeout_ms)
839 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
840
841 mhi_cntrl->bounce_buf = config->use_bounce_buf;
842 mhi_cntrl->buffer_len = config->buf_len;
843 if (!mhi_cntrl->buffer_len)
844 mhi_cntrl->buffer_len = MHI_MAX_MTU;
845
846 /* By default, host is allowed to ring DB in both M0 and M2 states */
847 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
848 if (config->m2_no_db)
849 mhi_cntrl->db_access &= ~MHI_PM_M2;
850
851 return 0;
852
853 error_ev_cfg:
854 vfree(mhi_cntrl->mhi_chan);
855
856 return ret;
857 }
858
mhi_register_controller(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)859 int mhi_register_controller(struct mhi_controller *mhi_cntrl,
860 const struct mhi_controller_config *config)
861 {
862 struct mhi_event *mhi_event;
863 struct mhi_chan *mhi_chan;
864 struct mhi_cmd *mhi_cmd;
865 struct mhi_device *mhi_dev;
866 u32 soc_info;
867 int ret, i;
868
869 if (!mhi_cntrl)
870 return -EINVAL;
871
872 if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
873 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
874 !mhi_cntrl->write_reg)
875 return -EINVAL;
876
877 ret = parse_config(mhi_cntrl, config);
878 if (ret)
879 return -EINVAL;
880
881 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS,
882 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);
883 if (!mhi_cntrl->mhi_cmd) {
884 ret = -ENOMEM;
885 goto error_alloc_cmd;
886 }
887
888 INIT_LIST_HEAD(&mhi_cntrl->transition_list);
889 mutex_init(&mhi_cntrl->pm_mutex);
890 rwlock_init(&mhi_cntrl->pm_lock);
891 spin_lock_init(&mhi_cntrl->transition_lock);
892 spin_lock_init(&mhi_cntrl->wlock);
893 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
894 init_waitqueue_head(&mhi_cntrl->state_event);
895
896 mhi_cmd = mhi_cntrl->mhi_cmd;
897 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++)
898 spin_lock_init(&mhi_cmd->lock);
899
900 mhi_event = mhi_cntrl->mhi_event;
901 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
902 /* Skip for offload events */
903 if (mhi_event->offload_ev)
904 continue;
905
906 mhi_event->mhi_cntrl = mhi_cntrl;
907 spin_lock_init(&mhi_event->lock);
908 if (mhi_event->data_type == MHI_ER_CTRL)
909 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task,
910 (ulong)mhi_event);
911 else
912 tasklet_init(&mhi_event->task, mhi_ev_task,
913 (ulong)mhi_event);
914 }
915
916 mhi_chan = mhi_cntrl->mhi_chan;
917 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
918 mutex_init(&mhi_chan->mutex);
919 init_completion(&mhi_chan->completion);
920 rwlock_init(&mhi_chan->lock);
921
922 /* used in setting bei field of TRE */
923 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
924 mhi_chan->intmod = mhi_event->intmod;
925 }
926
927 if (mhi_cntrl->bounce_buf) {
928 mhi_cntrl->map_single = mhi_map_single_use_bb;
929 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;
930 } else {
931 mhi_cntrl->map_single = mhi_map_single_no_bb;
932 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
933 }
934
935 /* Read the MHI device info */
936 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,
937 SOC_HW_VERSION_OFFS, &soc_info);
938 if (ret)
939 goto error_alloc_dev;
940
941 mhi_cntrl->family_number = (soc_info & SOC_HW_VERSION_FAM_NUM_BMSK) >>
942 SOC_HW_VERSION_FAM_NUM_SHFT;
943 mhi_cntrl->device_number = (soc_info & SOC_HW_VERSION_DEV_NUM_BMSK) >>
944 SOC_HW_VERSION_DEV_NUM_SHFT;
945 mhi_cntrl->major_version = (soc_info & SOC_HW_VERSION_MAJOR_VER_BMSK) >>
946 SOC_HW_VERSION_MAJOR_VER_SHFT;
947 mhi_cntrl->minor_version = (soc_info & SOC_HW_VERSION_MINOR_VER_BMSK) >>
948 SOC_HW_VERSION_MINOR_VER_SHFT;
949
950 /* Register controller with MHI bus */
951 mhi_dev = mhi_alloc_device(mhi_cntrl);
952 if (IS_ERR(mhi_dev)) {
953 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
954 ret = PTR_ERR(mhi_dev);
955 goto error_alloc_dev;
956 }
957
958 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
959 mhi_dev->mhi_cntrl = mhi_cntrl;
960 dev_set_name(&mhi_dev->dev, "%s", dev_name(mhi_cntrl->cntrl_dev));
961 mhi_dev->name = dev_name(mhi_cntrl->cntrl_dev);
962
963 /* Init wakeup source */
964 device_init_wakeup(&mhi_dev->dev, true);
965
966 ret = device_add(&mhi_dev->dev);
967 if (ret)
968 goto error_add_dev;
969
970 mhi_cntrl->mhi_dev = mhi_dev;
971
972 mhi_create_debugfs(mhi_cntrl);
973
974 return 0;
975
976 error_add_dev:
977 put_device(&mhi_dev->dev);
978
979 error_alloc_dev:
980 kfree(mhi_cntrl->mhi_cmd);
981
982 error_alloc_cmd:
983 vfree(mhi_cntrl->mhi_chan);
984 kfree(mhi_cntrl->mhi_event);
985
986 return ret;
987 }
988 EXPORT_SYMBOL_GPL(mhi_register_controller);
989
mhi_unregister_controller(struct mhi_controller * mhi_cntrl)990 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
991 {
992 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;
993 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
994 unsigned int i;
995
996 mhi_destroy_debugfs(mhi_cntrl);
997
998 kfree(mhi_cntrl->mhi_cmd);
999 kfree(mhi_cntrl->mhi_event);
1000
1001 /* Drop the references to MHI devices created for channels */
1002 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
1003 if (!mhi_chan->mhi_dev)
1004 continue;
1005
1006 put_device(&mhi_chan->mhi_dev->dev);
1007 }
1008 vfree(mhi_cntrl->mhi_chan);
1009
1010 device_del(&mhi_dev->dev);
1011 put_device(&mhi_dev->dev);
1012 }
1013 EXPORT_SYMBOL_GPL(mhi_unregister_controller);
1014
mhi_alloc_controller(void)1015 struct mhi_controller *mhi_alloc_controller(void)
1016 {
1017 struct mhi_controller *mhi_cntrl;
1018
1019 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL);
1020
1021 return mhi_cntrl;
1022 }
1023 EXPORT_SYMBOL_GPL(mhi_alloc_controller);
1024
mhi_free_controller(struct mhi_controller * mhi_cntrl)1025 void mhi_free_controller(struct mhi_controller *mhi_cntrl)
1026 {
1027 kfree(mhi_cntrl);
1028 }
1029 EXPORT_SYMBOL_GPL(mhi_free_controller);
1030
mhi_prepare_for_power_up(struct mhi_controller * mhi_cntrl)1031 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
1032 {
1033 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1034 u32 bhie_off;
1035 int ret;
1036
1037 mutex_lock(&mhi_cntrl->pm_mutex);
1038
1039 ret = mhi_init_dev_ctxt(mhi_cntrl);
1040 if (ret)
1041 goto error_dev_ctxt;
1042
1043 /*
1044 * Allocate RDDM table if specified, this table is for debugging purpose
1045 */
1046 if (mhi_cntrl->rddm_size) {
1047 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
1048 mhi_cntrl->rddm_size);
1049
1050 /*
1051 * This controller supports RDDM, so we need to manually clear
1052 * BHIE RX registers since POR values are undefined.
1053 */
1054 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
1055 &bhie_off);
1056 if (ret) {
1057 dev_err(dev, "Error getting BHIE offset\n");
1058 goto bhie_error;
1059 }
1060
1061 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
1062 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
1063 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
1064 4);
1065
1066 if (mhi_cntrl->rddm_image)
1067 mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
1068 }
1069
1070 mhi_cntrl->pre_init = true;
1071
1072 mutex_unlock(&mhi_cntrl->pm_mutex);
1073
1074 return 0;
1075
1076 bhie_error:
1077 if (mhi_cntrl->rddm_image) {
1078 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1079 mhi_cntrl->rddm_image = NULL;
1080 }
1081
1082 error_dev_ctxt:
1083 mutex_unlock(&mhi_cntrl->pm_mutex);
1084
1085 return ret;
1086 }
1087 EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up);
1088
mhi_unprepare_after_power_down(struct mhi_controller * mhi_cntrl)1089 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
1090 {
1091 if (mhi_cntrl->fbc_image) {
1092 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1093 mhi_cntrl->fbc_image = NULL;
1094 }
1095
1096 if (mhi_cntrl->rddm_image) {
1097 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1098 mhi_cntrl->rddm_image = NULL;
1099 }
1100
1101 mhi_deinit_dev_ctxt(mhi_cntrl);
1102 mhi_cntrl->pre_init = false;
1103 }
1104 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
1105
mhi_release_device(struct device * dev)1106 static void mhi_release_device(struct device *dev)
1107 {
1108 struct mhi_device *mhi_dev = to_mhi_device(dev);
1109
1110 /*
1111 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI
1112 * devices for the channels will only get created if the mhi_dev
1113 * associated with it is NULL. This scenario will happen during the
1114 * controller suspend and resume.
1115 */
1116 if (mhi_dev->ul_chan)
1117 mhi_dev->ul_chan->mhi_dev = NULL;
1118
1119 if (mhi_dev->dl_chan)
1120 mhi_dev->dl_chan->mhi_dev = NULL;
1121
1122 kfree(mhi_dev);
1123 }
1124
mhi_alloc_device(struct mhi_controller * mhi_cntrl)1125 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)
1126 {
1127 struct mhi_device *mhi_dev;
1128 struct device *dev;
1129
1130 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL);
1131 if (!mhi_dev)
1132 return ERR_PTR(-ENOMEM);
1133
1134 dev = &mhi_dev->dev;
1135 device_initialize(dev);
1136 dev->bus = &mhi_bus_type;
1137 dev->release = mhi_release_device;
1138 dev->parent = mhi_cntrl->cntrl_dev;
1139 mhi_dev->mhi_cntrl = mhi_cntrl;
1140 mhi_dev->dev_wake = 0;
1141
1142 return mhi_dev;
1143 }
1144
mhi_driver_probe(struct device * dev)1145 static int mhi_driver_probe(struct device *dev)
1146 {
1147 struct mhi_device *mhi_dev = to_mhi_device(dev);
1148 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1149 struct device_driver *drv = dev->driver;
1150 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1151 struct mhi_event *mhi_event;
1152 struct mhi_chan *ul_chan = mhi_dev->ul_chan;
1153 struct mhi_chan *dl_chan = mhi_dev->dl_chan;
1154 int ret;
1155
1156 /* Bring device out of LPM */
1157 ret = mhi_device_get_sync(mhi_dev);
1158 if (ret)
1159 return ret;
1160
1161 ret = -EINVAL;
1162
1163 if (ul_chan) {
1164 /*
1165 * If channel supports LPM notifications then status_cb should
1166 * be provided
1167 */
1168 if (ul_chan->lpm_notify && !mhi_drv->status_cb)
1169 goto exit_probe;
1170
1171 /* For non-offload channels then xfer_cb should be provided */
1172 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb)
1173 goto exit_probe;
1174
1175 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1176 if (ul_chan->auto_start) {
1177 ret = mhi_prepare_channel(mhi_cntrl, ul_chan);
1178 if (ret)
1179 goto exit_probe;
1180 }
1181 }
1182
1183 ret = -EINVAL;
1184 if (dl_chan) {
1185 /*
1186 * If channel supports LPM notifications then status_cb should
1187 * be provided
1188 */
1189 if (dl_chan->lpm_notify && !mhi_drv->status_cb)
1190 goto exit_probe;
1191
1192 /* For non-offload channels then xfer_cb should be provided */
1193 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb)
1194 goto exit_probe;
1195
1196 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];
1197
1198 /*
1199 * If the channel event ring is managed by client, then
1200 * status_cb must be provided so that the framework can
1201 * notify pending data
1202 */
1203 if (mhi_event->cl_manage && !mhi_drv->status_cb)
1204 goto exit_probe;
1205
1206 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1207 }
1208
1209 /* Call the user provided probe function */
1210 ret = mhi_drv->probe(mhi_dev, mhi_dev->id);
1211 if (ret)
1212 goto exit_probe;
1213
1214 if (dl_chan && dl_chan->auto_start)
1215 mhi_prepare_channel(mhi_cntrl, dl_chan);
1216
1217 mhi_device_put(mhi_dev);
1218
1219 return ret;
1220
1221 exit_probe:
1222 mhi_unprepare_from_transfer(mhi_dev);
1223
1224 mhi_device_put(mhi_dev);
1225
1226 return ret;
1227 }
1228
mhi_driver_remove(struct device * dev)1229 static int mhi_driver_remove(struct device *dev)
1230 {
1231 struct mhi_device *mhi_dev = to_mhi_device(dev);
1232 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver);
1233 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1234 struct mhi_chan *mhi_chan;
1235 enum mhi_ch_state ch_state[] = {
1236 MHI_CH_STATE_DISABLED,
1237 MHI_CH_STATE_DISABLED
1238 };
1239 int dir;
1240
1241 /* Skip if it is a controller device */
1242 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1243 return 0;
1244
1245 /* Reset both channels */
1246 for (dir = 0; dir < 2; dir++) {
1247 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1248
1249 if (!mhi_chan)
1250 continue;
1251
1252 /* Wake all threads waiting for completion */
1253 write_lock_irq(&mhi_chan->lock);
1254 mhi_chan->ccs = MHI_EV_CC_INVALID;
1255 complete_all(&mhi_chan->completion);
1256 write_unlock_irq(&mhi_chan->lock);
1257
1258 /* Set the channel state to disabled */
1259 mutex_lock(&mhi_chan->mutex);
1260 write_lock_irq(&mhi_chan->lock);
1261 ch_state[dir] = mhi_chan->ch_state;
1262 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED;
1263 write_unlock_irq(&mhi_chan->lock);
1264
1265 /* Reset the non-offload channel */
1266 if (!mhi_chan->offload_ch)
1267 mhi_reset_chan(mhi_cntrl, mhi_chan);
1268
1269 mutex_unlock(&mhi_chan->mutex);
1270 }
1271
1272 mhi_drv->remove(mhi_dev);
1273
1274 /* De-init channel if it was enabled */
1275 for (dir = 0; dir < 2; dir++) {
1276 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1277
1278 if (!mhi_chan)
1279 continue;
1280
1281 mutex_lock(&mhi_chan->mutex);
1282
1283 if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
1284 ch_state[dir] == MHI_CH_STATE_STOP) &&
1285 !mhi_chan->offload_ch)
1286 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
1287
1288 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
1289
1290 mutex_unlock(&mhi_chan->mutex);
1291 }
1292
1293 while (mhi_dev->dev_wake)
1294 mhi_device_put(mhi_dev);
1295
1296 return 0;
1297 }
1298
__mhi_driver_register(struct mhi_driver * mhi_drv,struct module * owner)1299 int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner)
1300 {
1301 struct device_driver *driver = &mhi_drv->driver;
1302
1303 if (!mhi_drv->probe || !mhi_drv->remove)
1304 return -EINVAL;
1305
1306 driver->bus = &mhi_bus_type;
1307 driver->owner = owner;
1308 driver->probe = mhi_driver_probe;
1309 driver->remove = mhi_driver_remove;
1310
1311 return driver_register(driver);
1312 }
1313 EXPORT_SYMBOL_GPL(__mhi_driver_register);
1314
mhi_driver_unregister(struct mhi_driver * mhi_drv)1315 void mhi_driver_unregister(struct mhi_driver *mhi_drv)
1316 {
1317 driver_unregister(&mhi_drv->driver);
1318 }
1319 EXPORT_SYMBOL_GPL(mhi_driver_unregister);
1320
mhi_uevent(struct device * dev,struct kobj_uevent_env * env)1321 static int mhi_uevent(struct device *dev, struct kobj_uevent_env *env)
1322 {
1323 struct mhi_device *mhi_dev = to_mhi_device(dev);
1324
1325 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT,
1326 mhi_dev->name);
1327 }
1328
mhi_match(struct device * dev,struct device_driver * drv)1329 static int mhi_match(struct device *dev, struct device_driver *drv)
1330 {
1331 struct mhi_device *mhi_dev = to_mhi_device(dev);
1332 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1333 const struct mhi_device_id *id;
1334
1335 /*
1336 * If the device is a controller type then there is no client driver
1337 * associated with it
1338 */
1339 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1340 return 0;
1341
1342 for (id = mhi_drv->id_table; id->chan[0]; id++)
1343 if (!strcmp(mhi_dev->name, id->chan)) {
1344 mhi_dev->id = id;
1345 return 1;
1346 }
1347
1348 return 0;
1349 };
1350
1351 struct bus_type mhi_bus_type = {
1352 .name = "mhi",
1353 .dev_name = "mhi",
1354 .match = mhi_match,
1355 .uevent = mhi_uevent,
1356 .dev_groups = mhi_dev_groups,
1357 };
1358
mhi_init(void)1359 static int __init mhi_init(void)
1360 {
1361 mhi_debugfs_init();
1362 return bus_register(&mhi_bus_type);
1363 }
1364
mhi_exit(void)1365 static void __exit mhi_exit(void)
1366 {
1367 mhi_debugfs_exit();
1368 bus_unregister(&mhi_bus_type);
1369 }
1370
1371 postcore_initcall(mhi_init);
1372 module_exit(mhi_exit);
1373
1374 MODULE_LICENSE("GPL v2");
1375 MODULE_DESCRIPTION("MHI Host Interface");
1376