1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/wait.h>
17 #include "internal.h"
18
19 /*
20 * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22 * transition to a new state only if we're allowed to.
23 *
24 * Priority increases as we go down. For instance, from any state in L0, the
25 * transition can be made to states in L1, L2 and L3. A notable exception to
26 * this rule is state DISABLE. From DISABLE state we can only transition to
27 * POR state. Also, while in L2 state, user cannot jump back to previous
28 * L1 or L0 states.
29 *
30 * Valid transitions:
31 * L0: DISABLE <--> POR
32 * POR <--> POR
33 * POR -> M0 -> M2 --> M0
34 * POR -> FW_DL_ERR
35 * FW_DL_ERR <--> FW_DL_ERR
36 * M0 <--> M0
37 * M0 -> FW_DL_ERR
38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR
40 * L2: SHUTDOWN_PROCESS -> DISABLE
41 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
42 * LD_ERR_FATAL_DETECT -> SHUTDOWN_PROCESS
43 */
44 static struct mhi_pm_transitions const dev_state_transitions[] = {
45 /* L0 States */
46 {
47 MHI_PM_DISABLE,
48 MHI_PM_POR
49 },
50 {
51 MHI_PM_POR,
52 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
53 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
54 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
55 },
56 {
57 MHI_PM_M0,
58 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
59 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
60 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
61 },
62 {
63 MHI_PM_M2,
64 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
65 MHI_PM_LD_ERR_FATAL_DETECT
66 },
67 {
68 MHI_PM_M3_ENTER,
69 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
70 MHI_PM_LD_ERR_FATAL_DETECT
71 },
72 {
73 MHI_PM_M3,
74 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
75 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
76 },
77 {
78 MHI_PM_M3_EXIT,
79 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
80 MHI_PM_LD_ERR_FATAL_DETECT
81 },
82 {
83 MHI_PM_FW_DL_ERR,
84 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
85 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
86 },
87 /* L1 States */
88 {
89 MHI_PM_SYS_ERR_DETECT,
90 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
91 MHI_PM_LD_ERR_FATAL_DETECT
92 },
93 {
94 MHI_PM_SYS_ERR_PROCESS,
95 MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS |
96 MHI_PM_LD_ERR_FATAL_DETECT
97 },
98 /* L2 States */
99 {
100 MHI_PM_SHUTDOWN_PROCESS,
101 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
102 },
103 /* L3 States */
104 {
105 MHI_PM_LD_ERR_FATAL_DETECT,
106 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_SHUTDOWN_PROCESS
107 },
108 };
109
mhi_tryset_pm_state(struct mhi_controller * mhi_cntrl,enum mhi_pm_state state)110 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
111 enum mhi_pm_state state)
112 {
113 unsigned long cur_state = mhi_cntrl->pm_state;
114 int index = find_last_bit(&cur_state, 32);
115
116 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
117 return cur_state;
118
119 if (unlikely(dev_state_transitions[index].from_state != cur_state))
120 return cur_state;
121
122 if (unlikely(!(dev_state_transitions[index].to_states & state)))
123 return cur_state;
124
125 mhi_cntrl->pm_state = state;
126 return mhi_cntrl->pm_state;
127 }
128
mhi_set_mhi_state(struct mhi_controller * mhi_cntrl,enum mhi_state state)129 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
130 {
131 if (state == MHI_STATE_RESET) {
132 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
133 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 1);
134 } else {
135 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
136 MHICTRL_MHISTATE_MASK,
137 MHICTRL_MHISTATE_SHIFT, state);
138 }
139 }
140
141 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
mhi_toggle_dev_wake_nop(struct mhi_controller * mhi_cntrl)142 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
143 {
144 }
145
mhi_toggle_dev_wake(struct mhi_controller * mhi_cntrl)146 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
147 {
148 mhi_cntrl->wake_get(mhi_cntrl, false);
149 mhi_cntrl->wake_put(mhi_cntrl, true);
150 }
151
152 /* Handle device ready state transition */
mhi_ready_state_transition(struct mhi_controller * mhi_cntrl)153 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
154 {
155 void __iomem *base = mhi_cntrl->regs;
156 struct mhi_event *mhi_event;
157 enum mhi_pm_state cur_state;
158 struct device *dev = &mhi_cntrl->mhi_dev->dev;
159 u32 reset = 1, ready = 0;
160 int ret, i;
161
162 /* Wait for RESET to be cleared and READY bit to be set by the device */
163 wait_event_timeout(mhi_cntrl->state_event,
164 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
165 mhi_read_reg_field(mhi_cntrl, base, MHICTRL,
166 MHICTRL_RESET_MASK,
167 MHICTRL_RESET_SHIFT, &reset) ||
168 mhi_read_reg_field(mhi_cntrl, base, MHISTATUS,
169 MHISTATUS_READY_MASK,
170 MHISTATUS_READY_SHIFT, &ready) ||
171 (!reset && ready),
172 msecs_to_jiffies(mhi_cntrl->timeout_ms));
173
174 /* Check if device entered error state */
175 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
176 dev_err(dev, "Device link is not accessible\n");
177 return -EIO;
178 }
179
180 /* Timeout if device did not transition to ready state */
181 if (reset || !ready) {
182 dev_err(dev, "Device Ready timeout\n");
183 return -ETIMEDOUT;
184 }
185
186 dev_dbg(dev, "Device in READY State\n");
187 write_lock_irq(&mhi_cntrl->pm_lock);
188 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
189 mhi_cntrl->dev_state = MHI_STATE_READY;
190 write_unlock_irq(&mhi_cntrl->pm_lock);
191
192 if (cur_state != MHI_PM_POR) {
193 dev_err(dev, "Error moving to state %s from %s\n",
194 to_mhi_pm_state_str(MHI_PM_POR),
195 to_mhi_pm_state_str(cur_state));
196 return -EIO;
197 }
198
199 read_lock_bh(&mhi_cntrl->pm_lock);
200 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
201 dev_err(dev, "Device registers not accessible\n");
202 goto error_mmio;
203 }
204
205 /* Configure MMIO registers */
206 ret = mhi_init_mmio(mhi_cntrl);
207 if (ret) {
208 dev_err(dev, "Error configuring MMIO registers\n");
209 goto error_mmio;
210 }
211
212 /* Add elements to all SW event rings */
213 mhi_event = mhi_cntrl->mhi_event;
214 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
215 struct mhi_ring *ring = &mhi_event->ring;
216
217 /* Skip if this is an offload or HW event */
218 if (mhi_event->offload_ev || mhi_event->hw_ring)
219 continue;
220
221 ring->wp = ring->base + ring->len - ring->el_size;
222 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
223 /* Update all cores */
224 smp_wmb();
225
226 /* Ring the event ring db */
227 spin_lock_irq(&mhi_event->lock);
228 mhi_ring_er_db(mhi_event);
229 spin_unlock_irq(&mhi_event->lock);
230 }
231
232 /* Set MHI to M0 state */
233 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
234 read_unlock_bh(&mhi_cntrl->pm_lock);
235
236 return 0;
237
238 error_mmio:
239 read_unlock_bh(&mhi_cntrl->pm_lock);
240
241 return -EIO;
242 }
243
mhi_pm_m0_transition(struct mhi_controller * mhi_cntrl)244 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
245 {
246 enum mhi_pm_state cur_state;
247 struct mhi_chan *mhi_chan;
248 struct device *dev = &mhi_cntrl->mhi_dev->dev;
249 int i;
250
251 write_lock_irq(&mhi_cntrl->pm_lock);
252 mhi_cntrl->dev_state = MHI_STATE_M0;
253 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
254 write_unlock_irq(&mhi_cntrl->pm_lock);
255 if (unlikely(cur_state != MHI_PM_M0)) {
256 dev_err(dev, "Unable to transition to M0 state\n");
257 return -EIO;
258 }
259 mhi_cntrl->M0++;
260
261 /* Wake up the device */
262 read_lock_bh(&mhi_cntrl->pm_lock);
263 mhi_cntrl->wake_get(mhi_cntrl, true);
264
265 /* Ring all event rings and CMD ring only if we're in mission mode */
266 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
267 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
268 struct mhi_cmd *mhi_cmd =
269 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
270
271 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
272 if (mhi_event->offload_ev)
273 continue;
274
275 spin_lock_irq(&mhi_event->lock);
276 mhi_ring_er_db(mhi_event);
277 spin_unlock_irq(&mhi_event->lock);
278 }
279
280 /* Only ring primary cmd ring if ring is not empty */
281 spin_lock_irq(&mhi_cmd->lock);
282 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
283 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
284 spin_unlock_irq(&mhi_cmd->lock);
285 }
286
287 /* Ring channel DB registers */
288 mhi_chan = mhi_cntrl->mhi_chan;
289 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
290 struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
291
292 if (mhi_chan->db_cfg.reset_req) {
293 write_lock_irq(&mhi_chan->lock);
294 mhi_chan->db_cfg.db_mode = true;
295 write_unlock_irq(&mhi_chan->lock);
296 }
297
298 read_lock_irq(&mhi_chan->lock);
299
300 /* Only ring DB if ring is not empty */
301 if (tre_ring->base && tre_ring->wp != tre_ring->rp &&
302 mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
303 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
304 read_unlock_irq(&mhi_chan->lock);
305 }
306
307 mhi_cntrl->wake_put(mhi_cntrl, false);
308 read_unlock_bh(&mhi_cntrl->pm_lock);
309 wake_up_all(&mhi_cntrl->state_event);
310
311 return 0;
312 }
313
314 /*
315 * After receiving the MHI state change event from the device indicating the
316 * transition to M1 state, the host can transition the device to M2 state
317 * for keeping it in low power state.
318 */
mhi_pm_m1_transition(struct mhi_controller * mhi_cntrl)319 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
320 {
321 enum mhi_pm_state state;
322 struct device *dev = &mhi_cntrl->mhi_dev->dev;
323
324 write_lock_irq(&mhi_cntrl->pm_lock);
325 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
326 if (state == MHI_PM_M2) {
327 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
328 mhi_cntrl->dev_state = MHI_STATE_M2;
329
330 write_unlock_irq(&mhi_cntrl->pm_lock);
331
332 mhi_cntrl->M2++;
333 wake_up_all(&mhi_cntrl->state_event);
334
335 /* If there are any pending resources, exit M2 immediately */
336 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
337 atomic_read(&mhi_cntrl->dev_wake))) {
338 dev_dbg(dev,
339 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
340 atomic_read(&mhi_cntrl->pending_pkts),
341 atomic_read(&mhi_cntrl->dev_wake));
342 read_lock_bh(&mhi_cntrl->pm_lock);
343 mhi_cntrl->wake_get(mhi_cntrl, true);
344 mhi_cntrl->wake_put(mhi_cntrl, true);
345 read_unlock_bh(&mhi_cntrl->pm_lock);
346 } else {
347 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
348 }
349 } else {
350 write_unlock_irq(&mhi_cntrl->pm_lock);
351 }
352 }
353
354 /* MHI M3 completion handler */
mhi_pm_m3_transition(struct mhi_controller * mhi_cntrl)355 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
356 {
357 enum mhi_pm_state state;
358 struct device *dev = &mhi_cntrl->mhi_dev->dev;
359
360 write_lock_irq(&mhi_cntrl->pm_lock);
361 mhi_cntrl->dev_state = MHI_STATE_M3;
362 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
363 write_unlock_irq(&mhi_cntrl->pm_lock);
364 if (state != MHI_PM_M3) {
365 dev_err(dev, "Unable to transition to M3 state\n");
366 return -EIO;
367 }
368
369 mhi_cntrl->M3++;
370 wake_up_all(&mhi_cntrl->state_event);
371
372 return 0;
373 }
374
375 /* Handle device Mission Mode transition */
mhi_pm_mission_mode_transition(struct mhi_controller * mhi_cntrl)376 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
377 {
378 struct mhi_event *mhi_event;
379 struct device *dev = &mhi_cntrl->mhi_dev->dev;
380 enum mhi_ee_type current_ee = mhi_cntrl->ee;
381 int i, ret;
382
383 dev_dbg(dev, "Processing Mission Mode transition\n");
384
385 write_lock_irq(&mhi_cntrl->pm_lock);
386 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
387 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
388 write_unlock_irq(&mhi_cntrl->pm_lock);
389
390 if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee))
391 return -EIO;
392
393 wake_up_all(&mhi_cntrl->state_event);
394
395 device_for_each_child(&mhi_cntrl->mhi_dev->dev, ¤t_ee,
396 mhi_destroy_device);
397 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
398
399 /* Force MHI to be in M0 state before continuing */
400 ret = __mhi_device_get_sync(mhi_cntrl);
401 if (ret)
402 return ret;
403
404 read_lock_bh(&mhi_cntrl->pm_lock);
405
406 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
407 ret = -EIO;
408 goto error_mission_mode;
409 }
410
411 /* Add elements to all HW event rings */
412 mhi_event = mhi_cntrl->mhi_event;
413 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
414 struct mhi_ring *ring = &mhi_event->ring;
415
416 if (mhi_event->offload_ev || !mhi_event->hw_ring)
417 continue;
418
419 ring->wp = ring->base + ring->len - ring->el_size;
420 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
421 /* Update to all cores */
422 smp_wmb();
423
424 spin_lock_irq(&mhi_event->lock);
425 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
426 mhi_ring_er_db(mhi_event);
427 spin_unlock_irq(&mhi_event->lock);
428 }
429
430 read_unlock_bh(&mhi_cntrl->pm_lock);
431
432 /*
433 * The MHI devices are only created when the client device switches its
434 * Execution Environment (EE) to either SBL or AMSS states
435 */
436 mhi_create_devices(mhi_cntrl);
437
438 read_lock_bh(&mhi_cntrl->pm_lock);
439
440 error_mission_mode:
441 mhi_cntrl->wake_put(mhi_cntrl, false);
442 read_unlock_bh(&mhi_cntrl->pm_lock);
443
444 return ret;
445 }
446
447 /* Handle SYS_ERR and Shutdown transitions */
mhi_pm_disable_transition(struct mhi_controller * mhi_cntrl,enum mhi_pm_state transition_state)448 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl,
449 enum mhi_pm_state transition_state)
450 {
451 enum mhi_pm_state cur_state, prev_state;
452 struct mhi_event *mhi_event;
453 struct mhi_cmd_ctxt *cmd_ctxt;
454 struct mhi_cmd *mhi_cmd;
455 struct mhi_event_ctxt *er_ctxt;
456 struct device *dev = &mhi_cntrl->mhi_dev->dev;
457 int ret, i;
458
459 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
460 to_mhi_pm_state_str(mhi_cntrl->pm_state),
461 to_mhi_pm_state_str(transition_state));
462
463 /* We must notify MHI control driver so it can clean up first */
464 if (transition_state == MHI_PM_SYS_ERR_PROCESS)
465 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
466
467 mutex_lock(&mhi_cntrl->pm_mutex);
468 write_lock_irq(&mhi_cntrl->pm_lock);
469 prev_state = mhi_cntrl->pm_state;
470 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
471 if (cur_state == transition_state) {
472 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
473 mhi_cntrl->dev_state = MHI_STATE_RESET;
474 }
475 write_unlock_irq(&mhi_cntrl->pm_lock);
476
477 /* Wake up threads waiting for state transition */
478 wake_up_all(&mhi_cntrl->state_event);
479
480 if (cur_state != transition_state) {
481 dev_err(dev, "Failed to transition to state: %s from: %s\n",
482 to_mhi_pm_state_str(transition_state),
483 to_mhi_pm_state_str(cur_state));
484 mutex_unlock(&mhi_cntrl->pm_mutex);
485 return;
486 }
487
488 /* Trigger MHI RESET so that the device will not access host memory */
489 if (MHI_REG_ACCESS_VALID(prev_state)) {
490 u32 in_reset = -1;
491 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
492
493 dev_dbg(dev, "Triggering MHI Reset in device\n");
494 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
495
496 /* Wait for the reset bit to be cleared by the device */
497 ret = wait_event_timeout(mhi_cntrl->state_event,
498 mhi_read_reg_field(mhi_cntrl,
499 mhi_cntrl->regs,
500 MHICTRL,
501 MHICTRL_RESET_MASK,
502 MHICTRL_RESET_SHIFT,
503 &in_reset) ||
504 !in_reset, timeout);
505 if ((!ret || in_reset) && cur_state == MHI_PM_SYS_ERR_PROCESS) {
506 dev_err(dev, "Device failed to exit MHI Reset state\n");
507 mutex_unlock(&mhi_cntrl->pm_mutex);
508 return;
509 }
510
511 /*
512 * Device will clear BHI_INTVEC as a part of RESET processing,
513 * hence re-program it
514 */
515 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
516 }
517
518 dev_dbg(dev,
519 "Waiting for all pending event ring processing to complete\n");
520 mhi_event = mhi_cntrl->mhi_event;
521 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
522 if (mhi_event->offload_ev)
523 continue;
524 tasklet_kill(&mhi_event->task);
525 }
526
527 /* Release lock and wait for all pending threads to complete */
528 mutex_unlock(&mhi_cntrl->pm_mutex);
529 dev_dbg(dev, "Waiting for all pending threads to complete\n");
530 wake_up_all(&mhi_cntrl->state_event);
531
532 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
533 device_for_each_child(mhi_cntrl->cntrl_dev, NULL, mhi_destroy_device);
534
535 mutex_lock(&mhi_cntrl->pm_mutex);
536
537 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
538 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
539
540 /* Reset the ev rings and cmd rings */
541 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
542 mhi_cmd = mhi_cntrl->mhi_cmd;
543 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
544 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
545 struct mhi_ring *ring = &mhi_cmd->ring;
546
547 ring->rp = ring->base;
548 ring->wp = ring->base;
549 cmd_ctxt->rp = cmd_ctxt->rbase;
550 cmd_ctxt->wp = cmd_ctxt->rbase;
551 }
552
553 mhi_event = mhi_cntrl->mhi_event;
554 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
555 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
556 mhi_event++) {
557 struct mhi_ring *ring = &mhi_event->ring;
558
559 /* Skip offload events */
560 if (mhi_event->offload_ev)
561 continue;
562
563 ring->rp = ring->base;
564 ring->wp = ring->base;
565 er_ctxt->rp = er_ctxt->rbase;
566 er_ctxt->wp = er_ctxt->rbase;
567 }
568
569 if (cur_state == MHI_PM_SYS_ERR_PROCESS) {
570 mhi_ready_state_transition(mhi_cntrl);
571 } else {
572 /* Move to disable state */
573 write_lock_irq(&mhi_cntrl->pm_lock);
574 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
575 write_unlock_irq(&mhi_cntrl->pm_lock);
576 if (unlikely(cur_state != MHI_PM_DISABLE))
577 dev_err(dev, "Error moving from PM state: %s to: %s\n",
578 to_mhi_pm_state_str(cur_state),
579 to_mhi_pm_state_str(MHI_PM_DISABLE));
580 }
581
582 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
583 to_mhi_pm_state_str(mhi_cntrl->pm_state),
584 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
585
586 mutex_unlock(&mhi_cntrl->pm_mutex);
587 }
588
589 /* Queue a new work item and schedule work */
mhi_queue_state_transition(struct mhi_controller * mhi_cntrl,enum dev_st_transition state)590 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
591 enum dev_st_transition state)
592 {
593 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
594 unsigned long flags;
595
596 if (!item)
597 return -ENOMEM;
598
599 item->state = state;
600 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
601 list_add_tail(&item->node, &mhi_cntrl->transition_list);
602 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
603
604 schedule_work(&mhi_cntrl->st_worker);
605
606 return 0;
607 }
608
609 /* SYS_ERR worker */
mhi_pm_sys_err_handler(struct mhi_controller * mhi_cntrl)610 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
611 {
612 struct device *dev = &mhi_cntrl->mhi_dev->dev;
613
614 /* skip if controller supports RDDM */
615 if (mhi_cntrl->rddm_image) {
616 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
617 return;
618 }
619
620 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
621 }
622
623 /* Device State Transition worker */
mhi_pm_st_worker(struct work_struct * work)624 void mhi_pm_st_worker(struct work_struct *work)
625 {
626 struct state_transition *itr, *tmp;
627 LIST_HEAD(head);
628 struct mhi_controller *mhi_cntrl = container_of(work,
629 struct mhi_controller,
630 st_worker);
631 struct device *dev = &mhi_cntrl->mhi_dev->dev;
632
633 spin_lock_irq(&mhi_cntrl->transition_lock);
634 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
635 spin_unlock_irq(&mhi_cntrl->transition_lock);
636
637 list_for_each_entry_safe(itr, tmp, &head, node) {
638 list_del(&itr->node);
639 dev_dbg(dev, "Handling state transition: %s\n",
640 TO_DEV_STATE_TRANS_STR(itr->state));
641
642 switch (itr->state) {
643 case DEV_ST_TRANSITION_PBL:
644 write_lock_irq(&mhi_cntrl->pm_lock);
645 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
646 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
647 write_unlock_irq(&mhi_cntrl->pm_lock);
648 if (MHI_IN_PBL(mhi_cntrl->ee))
649 mhi_fw_load_handler(mhi_cntrl);
650 break;
651 case DEV_ST_TRANSITION_SBL:
652 write_lock_irq(&mhi_cntrl->pm_lock);
653 mhi_cntrl->ee = MHI_EE_SBL;
654 write_unlock_irq(&mhi_cntrl->pm_lock);
655 /*
656 * The MHI devices are only created when the client
657 * device switches its Execution Environment (EE) to
658 * either SBL or AMSS states
659 */
660 mhi_create_devices(mhi_cntrl);
661 break;
662 case DEV_ST_TRANSITION_MISSION_MODE:
663 mhi_pm_mission_mode_transition(mhi_cntrl);
664 break;
665 case DEV_ST_TRANSITION_READY:
666 mhi_ready_state_transition(mhi_cntrl);
667 break;
668 case DEV_ST_TRANSITION_SYS_ERR:
669 mhi_pm_disable_transition
670 (mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
671 break;
672 case DEV_ST_TRANSITION_DISABLE:
673 mhi_pm_disable_transition
674 (mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS);
675 break;
676 default:
677 break;
678 }
679 kfree(itr);
680 }
681 }
682
mhi_pm_suspend(struct mhi_controller * mhi_cntrl)683 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
684 {
685 struct mhi_chan *itr, *tmp;
686 struct device *dev = &mhi_cntrl->mhi_dev->dev;
687 enum mhi_pm_state new_state;
688 int ret;
689
690 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
691 return -EINVAL;
692
693 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
694 return -EIO;
695
696 /* Return busy if there are any pending resources */
697 if (atomic_read(&mhi_cntrl->dev_wake) ||
698 atomic_read(&mhi_cntrl->pending_pkts))
699 return -EBUSY;
700
701 /* Take MHI out of M2 state */
702 read_lock_bh(&mhi_cntrl->pm_lock);
703 mhi_cntrl->wake_get(mhi_cntrl, false);
704 read_unlock_bh(&mhi_cntrl->pm_lock);
705
706 ret = wait_event_timeout(mhi_cntrl->state_event,
707 mhi_cntrl->dev_state == MHI_STATE_M0 ||
708 mhi_cntrl->dev_state == MHI_STATE_M1 ||
709 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
710 msecs_to_jiffies(mhi_cntrl->timeout_ms));
711
712 read_lock_bh(&mhi_cntrl->pm_lock);
713 mhi_cntrl->wake_put(mhi_cntrl, false);
714 read_unlock_bh(&mhi_cntrl->pm_lock);
715
716 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
717 dev_err(dev,
718 "Could not enter M0/M1 state");
719 return -EIO;
720 }
721
722 write_lock_irq(&mhi_cntrl->pm_lock);
723
724 if (atomic_read(&mhi_cntrl->dev_wake) ||
725 atomic_read(&mhi_cntrl->pending_pkts)) {
726 write_unlock_irq(&mhi_cntrl->pm_lock);
727 return -EBUSY;
728 }
729
730 dev_info(dev, "Allowing M3 transition\n");
731 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
732 if (new_state != MHI_PM_M3_ENTER) {
733 write_unlock_irq(&mhi_cntrl->pm_lock);
734 dev_err(dev,
735 "Error setting to PM state: %s from: %s\n",
736 to_mhi_pm_state_str(MHI_PM_M3_ENTER),
737 to_mhi_pm_state_str(mhi_cntrl->pm_state));
738 return -EIO;
739 }
740
741 /* Set MHI to M3 and wait for completion */
742 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
743 write_unlock_irq(&mhi_cntrl->pm_lock);
744 dev_info(dev, "Wait for M3 completion\n");
745
746 ret = wait_event_timeout(mhi_cntrl->state_event,
747 mhi_cntrl->dev_state == MHI_STATE_M3 ||
748 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
749 msecs_to_jiffies(mhi_cntrl->timeout_ms));
750
751 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
752 dev_err(dev,
753 "Did not enter M3 state, MHI state: %s, PM state: %s\n",
754 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
755 to_mhi_pm_state_str(mhi_cntrl->pm_state));
756 return -EIO;
757 }
758
759 /* Notify clients about entering LPM */
760 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
761 mutex_lock(&itr->mutex);
762 if (itr->mhi_dev)
763 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
764 mutex_unlock(&itr->mutex);
765 }
766
767 return 0;
768 }
769 EXPORT_SYMBOL_GPL(mhi_pm_suspend);
770
mhi_pm_resume(struct mhi_controller * mhi_cntrl)771 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
772 {
773 struct mhi_chan *itr, *tmp;
774 struct device *dev = &mhi_cntrl->mhi_dev->dev;
775 enum mhi_pm_state cur_state;
776 int ret;
777
778 dev_info(dev, "Entered with PM state: %s, MHI state: %s\n",
779 to_mhi_pm_state_str(mhi_cntrl->pm_state),
780 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
781
782 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
783 return 0;
784
785 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
786 return -EIO;
787
788 /* Notify clients about exiting LPM */
789 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
790 mutex_lock(&itr->mutex);
791 if (itr->mhi_dev)
792 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
793 mutex_unlock(&itr->mutex);
794 }
795
796 write_lock_irq(&mhi_cntrl->pm_lock);
797 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
798 if (cur_state != MHI_PM_M3_EXIT) {
799 write_unlock_irq(&mhi_cntrl->pm_lock);
800 dev_info(dev,
801 "Error setting to PM state: %s from: %s\n",
802 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
803 to_mhi_pm_state_str(mhi_cntrl->pm_state));
804 return -EIO;
805 }
806
807 /* Set MHI to M0 and wait for completion */
808 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
809 write_unlock_irq(&mhi_cntrl->pm_lock);
810
811 ret = wait_event_timeout(mhi_cntrl->state_event,
812 mhi_cntrl->dev_state == MHI_STATE_M0 ||
813 mhi_cntrl->dev_state == MHI_STATE_M2 ||
814 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
815 msecs_to_jiffies(mhi_cntrl->timeout_ms));
816
817 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
818 dev_err(dev,
819 "Did not enter M0 state, MHI state: %s, PM state: %s\n",
820 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
821 to_mhi_pm_state_str(mhi_cntrl->pm_state));
822 return -EIO;
823 }
824
825 return 0;
826 }
827 EXPORT_SYMBOL_GPL(mhi_pm_resume);
828
__mhi_device_get_sync(struct mhi_controller * mhi_cntrl)829 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
830 {
831 int ret;
832
833 /* Wake up the device */
834 read_lock_bh(&mhi_cntrl->pm_lock);
835 mhi_cntrl->wake_get(mhi_cntrl, true);
836 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
837 mhi_trigger_resume(mhi_cntrl);
838 read_unlock_bh(&mhi_cntrl->pm_lock);
839
840 ret = wait_event_timeout(mhi_cntrl->state_event,
841 mhi_cntrl->pm_state == MHI_PM_M0 ||
842 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
843 msecs_to_jiffies(mhi_cntrl->timeout_ms));
844
845 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
846 read_lock_bh(&mhi_cntrl->pm_lock);
847 mhi_cntrl->wake_put(mhi_cntrl, false);
848 read_unlock_bh(&mhi_cntrl->pm_lock);
849 return -EIO;
850 }
851
852 return 0;
853 }
854
855 /* Assert device wake db */
mhi_assert_dev_wake(struct mhi_controller * mhi_cntrl,bool force)856 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
857 {
858 unsigned long flags;
859
860 /*
861 * If force flag is set, then increment the wake count value and
862 * ring wake db
863 */
864 if (unlikely(force)) {
865 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
866 atomic_inc(&mhi_cntrl->dev_wake);
867 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
868 !mhi_cntrl->wake_set) {
869 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
870 mhi_cntrl->wake_set = true;
871 }
872 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
873 } else {
874 /*
875 * If resources are already requested, then just increment
876 * the wake count value and return
877 */
878 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
879 return;
880
881 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
882 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
883 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
884 !mhi_cntrl->wake_set) {
885 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
886 mhi_cntrl->wake_set = true;
887 }
888 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
889 }
890 }
891
892 /* De-assert device wake db */
mhi_deassert_dev_wake(struct mhi_controller * mhi_cntrl,bool override)893 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
894 bool override)
895 {
896 unsigned long flags;
897
898 /*
899 * Only continue if there is a single resource, else just decrement
900 * and return
901 */
902 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
903 return;
904
905 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
906 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
907 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
908 mhi_cntrl->wake_set) {
909 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
910 mhi_cntrl->wake_set = false;
911 }
912 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
913 }
914
mhi_async_power_up(struct mhi_controller * mhi_cntrl)915 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
916 {
917 enum mhi_state state;
918 enum mhi_ee_type current_ee;
919 enum dev_st_transition next_state;
920 struct device *dev = &mhi_cntrl->mhi_dev->dev;
921 u32 val;
922 int ret;
923
924 dev_info(dev, "Requested to power ON\n");
925
926 if (mhi_cntrl->nr_irqs < 1)
927 return -EINVAL;
928
929 /* Supply default wake routines if not provided by controller driver */
930 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
931 !mhi_cntrl->wake_toggle) {
932 mhi_cntrl->wake_get = mhi_assert_dev_wake;
933 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
934 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
935 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
936 }
937
938 mutex_lock(&mhi_cntrl->pm_mutex);
939 mhi_cntrl->pm_state = MHI_PM_DISABLE;
940
941 if (!mhi_cntrl->pre_init) {
942 /* Setup device context */
943 ret = mhi_init_dev_ctxt(mhi_cntrl);
944 if (ret)
945 goto error_dev_ctxt;
946 }
947
948 ret = mhi_init_irq_setup(mhi_cntrl);
949 if (ret)
950 goto error_setup_irq;
951
952 /* Setup BHI offset & INTVEC */
953 write_lock_irq(&mhi_cntrl->pm_lock);
954 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
955 if (ret) {
956 write_unlock_irq(&mhi_cntrl->pm_lock);
957 goto error_bhi_offset;
958 }
959
960 mhi_cntrl->bhi = mhi_cntrl->regs + val;
961
962 /* Setup BHIE offset */
963 if (mhi_cntrl->fbc_download) {
964 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
965 if (ret) {
966 write_unlock_irq(&mhi_cntrl->pm_lock);
967 dev_err(dev, "Error reading BHIE offset\n");
968 goto error_bhi_offset;
969 }
970
971 mhi_cntrl->bhie = mhi_cntrl->regs + val;
972 }
973
974 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
975 mhi_cntrl->pm_state = MHI_PM_POR;
976 mhi_cntrl->ee = MHI_EE_MAX;
977 current_ee = mhi_get_exec_env(mhi_cntrl);
978 write_unlock_irq(&mhi_cntrl->pm_lock);
979
980 /* Confirm that the device is in valid exec env */
981 if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
982 dev_err(dev, "Not a valid EE for power on\n");
983 ret = -EIO;
984 goto error_bhi_offset;
985 }
986
987 state = mhi_get_mhi_state(mhi_cntrl);
988 if (state == MHI_STATE_SYS_ERR) {
989 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
990 ret = wait_event_timeout(mhi_cntrl->state_event,
991 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
992 mhi_read_reg_field(mhi_cntrl,
993 mhi_cntrl->regs,
994 MHICTRL,
995 MHICTRL_RESET_MASK,
996 MHICTRL_RESET_SHIFT,
997 &val) ||
998 !val,
999 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1000 if (!ret) {
1001 ret = -EIO;
1002 dev_info(dev, "Failed to reset MHI due to syserr state\n");
1003 goto error_bhi_offset;
1004 }
1005
1006 /*
1007 * device cleares INTVEC as part of RESET processing,
1008 * re-program it
1009 */
1010 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1011 }
1012
1013 /* Transition to next state */
1014 next_state = MHI_IN_PBL(current_ee) ?
1015 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1016
1017 mhi_queue_state_transition(mhi_cntrl, next_state);
1018
1019 mutex_unlock(&mhi_cntrl->pm_mutex);
1020
1021 dev_info(dev, "Power on setup success\n");
1022
1023 return 0;
1024
1025 error_bhi_offset:
1026 mhi_deinit_free_irq(mhi_cntrl);
1027
1028 error_setup_irq:
1029 if (!mhi_cntrl->pre_init)
1030 mhi_deinit_dev_ctxt(mhi_cntrl);
1031
1032 error_dev_ctxt:
1033 mutex_unlock(&mhi_cntrl->pm_mutex);
1034
1035 return ret;
1036 }
1037 EXPORT_SYMBOL_GPL(mhi_async_power_up);
1038
mhi_power_down(struct mhi_controller * mhi_cntrl,bool graceful)1039 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1040 {
1041 enum mhi_pm_state cur_state;
1042 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1043
1044 /* If it's not a graceful shutdown, force MHI to linkdown state */
1045 if (!graceful) {
1046 mutex_lock(&mhi_cntrl->pm_mutex);
1047 write_lock_irq(&mhi_cntrl->pm_lock);
1048 cur_state = mhi_tryset_pm_state(mhi_cntrl,
1049 MHI_PM_LD_ERR_FATAL_DETECT);
1050 write_unlock_irq(&mhi_cntrl->pm_lock);
1051 mutex_unlock(&mhi_cntrl->pm_mutex);
1052 if (cur_state != MHI_PM_LD_ERR_FATAL_DETECT)
1053 dev_dbg(dev, "Failed to move to state: %s from: %s\n",
1054 to_mhi_pm_state_str(MHI_PM_LD_ERR_FATAL_DETECT),
1055 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1056 }
1057
1058 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1059
1060 /* Wait for shutdown to complete */
1061 flush_work(&mhi_cntrl->st_worker);
1062
1063 mhi_deinit_free_irq(mhi_cntrl);
1064
1065 if (!mhi_cntrl->pre_init) {
1066 /* Free all allocated resources */
1067 if (mhi_cntrl->fbc_image) {
1068 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1069 mhi_cntrl->fbc_image = NULL;
1070 }
1071 mhi_deinit_dev_ctxt(mhi_cntrl);
1072 }
1073 }
1074 EXPORT_SYMBOL_GPL(mhi_power_down);
1075
mhi_sync_power_up(struct mhi_controller * mhi_cntrl)1076 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1077 {
1078 int ret = mhi_async_power_up(mhi_cntrl);
1079
1080 if (ret)
1081 return ret;
1082
1083 wait_event_timeout(mhi_cntrl->state_event,
1084 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1085 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1086 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1087
1088 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1089 if (ret)
1090 mhi_power_down(mhi_cntrl, false);
1091
1092 return ret;
1093 }
1094 EXPORT_SYMBOL(mhi_sync_power_up);
1095
mhi_force_rddm_mode(struct mhi_controller * mhi_cntrl)1096 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1097 {
1098 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1099 int ret;
1100
1101 /* Check if device is already in RDDM */
1102 if (mhi_cntrl->ee == MHI_EE_RDDM)
1103 return 0;
1104
1105 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1106 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1107
1108 /* Wait for RDDM event */
1109 ret = wait_event_timeout(mhi_cntrl->state_event,
1110 mhi_cntrl->ee == MHI_EE_RDDM,
1111 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1112 ret = ret ? 0 : -EIO;
1113
1114 return ret;
1115 }
1116 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
1117
mhi_device_get(struct mhi_device * mhi_dev)1118 void mhi_device_get(struct mhi_device *mhi_dev)
1119 {
1120 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1121
1122 mhi_dev->dev_wake++;
1123 read_lock_bh(&mhi_cntrl->pm_lock);
1124 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1125 mhi_trigger_resume(mhi_cntrl);
1126
1127 mhi_cntrl->wake_get(mhi_cntrl, true);
1128 read_unlock_bh(&mhi_cntrl->pm_lock);
1129 }
1130 EXPORT_SYMBOL_GPL(mhi_device_get);
1131
mhi_device_get_sync(struct mhi_device * mhi_dev)1132 int mhi_device_get_sync(struct mhi_device *mhi_dev)
1133 {
1134 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1135 int ret;
1136
1137 ret = __mhi_device_get_sync(mhi_cntrl);
1138 if (!ret)
1139 mhi_dev->dev_wake++;
1140
1141 return ret;
1142 }
1143 EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1144
mhi_device_put(struct mhi_device * mhi_dev)1145 void mhi_device_put(struct mhi_device *mhi_dev)
1146 {
1147 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1148
1149 mhi_dev->dev_wake--;
1150 read_lock_bh(&mhi_cntrl->pm_lock);
1151 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1152 mhi_trigger_resume(mhi_cntrl);
1153
1154 mhi_cntrl->wake_put(mhi_cntrl, false);
1155 read_unlock_bh(&mhi_cntrl->pm_lock);
1156 }
1157 EXPORT_SYMBOL_GPL(mhi_device_put);
1158