1 /*
2 * Copyright (C) 2019 Collabora, Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef __MDG_QUIRKS_H
25 #define __MDG_QUIRKS_H
26
27 /* Model-specific quirks requiring compiler workarounds/etc. Quirks
28 * may be errata requiring a workaround, or features. We're trying to be
29 * quirk-positive here; quirky is the best! */
30
31 /* Typed loads are broken on this Midgard GPU due to issue #10607 and #10632 and
32 * should use software unpacks instead.
33 */
34 #define MIDGARD_BROKEN_BLEND_LOADS (1 << 0)
35
36 /* Whether output texture registers (normally r28/r29) overlap with work
37 * registers r0/r1 and input texture registers (also normally r28/r29) overlap
38 * with load/store registers r26/r27. This constrains register allocation
39 * considerably but is a space-saving measure on small Midgards. It's worth
40 * noting if you try to access r28/r29, it may still work, but you'll mess up
41 * the interference. Corresponds to BASE_HW_FEATURE_INTERPIPE_REG_ALIASING in
42 * kbase. */
43
44 #define MIDGARD_INTERPIPE_REG_ALIASING (1 << 1)
45
46 /* Whether we should use old-style blend opcodes */
47
48 #define MIDGARD_OLD_BLEND (1 << 2)
49
50 /* Errata causing the LOD clamps and bias in the sampler descriptor to be
51 * ignored. This errata affects the command stream but uses a compiler
52 * workaround (applying the clamps/bias manually in the shader. Corresponds in
53 * BASE_HW_ISSUE_10471 in kbase, described as "TEXGRD doesn't honor Sampler
54 * Descriptor LOD clamps nor bias". (I'm assuming TEXGRD is what we call
55 * textureLod) */
56
57 #define MIDGARD_BROKEN_LOD (1 << 3)
58
59 /* Don't use upper ALU tags for writeout (if you do, you'll get a
60 * INSTR_INVALID_ENC). It's not clear to me what these tags are for. */
61
62 #define MIDGARD_NO_UPPER_ALU (1 << 4)
63
64 /* Whether (texture) out-of-order execution support is missing on early
65 * Midgards. For these just set the OoO bits to 0. */
66
67 #define MIDGARD_NO_OOO (1 << 5)
68
69 static inline unsigned
midgard_get_quirks(unsigned gpu_id)70 midgard_get_quirks(unsigned gpu_id)
71 {
72 switch (gpu_id) {
73 case 0x600:
74 case 0x620:
75 return MIDGARD_OLD_BLEND |
76 MIDGARD_BROKEN_BLEND_LOADS |
77 MIDGARD_BROKEN_LOD |
78 MIDGARD_NO_UPPER_ALU |
79 MIDGARD_NO_OOO;
80
81 case 0x720:
82 return MIDGARD_INTERPIPE_REG_ALIASING |
83 MIDGARD_OLD_BLEND |
84 MIDGARD_BROKEN_LOD |
85 MIDGARD_NO_UPPER_ALU |
86 MIDGARD_NO_OOO;
87
88 case 0x820:
89 case 0x830:
90 return MIDGARD_INTERPIPE_REG_ALIASING;
91
92 case 0x750:
93 return MIDGARD_NO_UPPER_ALU;
94
95 case 0x860:
96 case 0x880:
97 return 0;
98
99 default:
100 unreachable("Invalid Midgard GPU ID");
101 }
102 }
103
104 #endif
105