1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 */
10
11 #include <linux/dma-mapping.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17
18 #include "mtu3.h"
19 #include "mtu3_dr.h"
20 #include "mtu3_debug.h"
21 #include "mtu3_trace.h"
22
ep_fifo_alloc(struct mtu3_ep * mep,u32 seg_size)23 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
24 {
25 struct mtu3_fifo_info *fifo = mep->fifo;
26 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
27 u32 start_bit;
28
29 /* ensure that @mep->fifo_seg_size is power of two */
30 num_bits = roundup_pow_of_two(num_bits);
31 if (num_bits > fifo->limit)
32 return -EINVAL;
33
34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
35 num_bits = num_bits * (mep->slot + 1);
36 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
37 fifo->limit, 0, num_bits, 0);
38 if (start_bit >= fifo->limit)
39 return -EOVERFLOW;
40
41 bitmap_set(fifo->bitmap, start_bit, num_bits);
42 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
43 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
44
45 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
46 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
47
48 return mep->fifo_addr;
49 }
50
ep_fifo_free(struct mtu3_ep * mep)51 static void ep_fifo_free(struct mtu3_ep *mep)
52 {
53 struct mtu3_fifo_info *fifo = mep->fifo;
54 u32 addr = mep->fifo_addr;
55 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
56 u32 start_bit;
57
58 if (unlikely(addr < fifo->base || bits > fifo->limit))
59 return;
60
61 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
62 bitmap_clear(fifo->bitmap, start_bit, bits);
63 mep->fifo_size = 0;
64 mep->fifo_seg_size = 0;
65
66 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
67 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
68 }
69
70 /* enable/disable U3D SS function */
mtu3_ss_func_set(struct mtu3 * mtu,bool enable)71 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
72 {
73 /* If usb3_en==0, LTSSM will go to SS.Disable state */
74 if (enable)
75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
76 else
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
78
79 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
80 }
81
82 /* set/clear U3D HS device soft connect */
mtu3_hs_softconn_set(struct mtu3 * mtu,bool enable)83 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
84 {
85 if (enable) {
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
88 } else {
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
90 SOFT_CONN | SUSPENDM_ENABLE);
91 }
92 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
93 }
94
95 /* only port0 of U2/U3 supports device mode */
mtu3_device_enable(struct mtu3 * mtu)96 static int mtu3_device_enable(struct mtu3 *mtu)
97 {
98 void __iomem *ibase = mtu->ippc_base;
99 u32 check_clk = 0;
100
101 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
102
103 if (mtu->is_u3_ip) {
104 check_clk = SSUSB_U3_MAC_RST_B_STS;
105 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
106 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
107 SSUSB_U3_PORT_HOST_SEL));
108 }
109 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
110 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
111 SSUSB_U2_PORT_HOST_SEL));
112
113 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
114 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
115 if (mtu->is_u3_ip)
116 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
117 SSUSB_U3_PORT_DUAL_MODE);
118 }
119
120 return ssusb_check_clocks(mtu->ssusb, check_clk);
121 }
122
mtu3_device_disable(struct mtu3 * mtu)123 static void mtu3_device_disable(struct mtu3 *mtu)
124 {
125 void __iomem *ibase = mtu->ippc_base;
126
127 if (mtu->is_u3_ip)
128 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
129 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
130
131 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
132 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
133
134 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
135 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
136 if (mtu->is_u3_ip)
137 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
138 SSUSB_U3_PORT_DUAL_MODE);
139 }
140
141 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
142 }
143
144 /* reset U3D's device module. */
mtu3_device_reset(struct mtu3 * mtu)145 static void mtu3_device_reset(struct mtu3 *mtu)
146 {
147 void __iomem *ibase = mtu->ippc_base;
148
149 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
150 udelay(1);
151 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
152 }
153
mtu3_intr_status_clear(struct mtu3 * mtu)154 static void mtu3_intr_status_clear(struct mtu3 *mtu)
155 {
156 void __iomem *mbase = mtu->mac_base;
157
158 /* Clear EP0 and Tx/Rx EPn interrupts status */
159 mtu3_writel(mbase, U3D_EPISR, ~0x0);
160 /* Clear U2 USB common interrupts status */
161 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
162 /* Clear U3 LTSSM interrupts status */
163 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
164 /* Clear speed change interrupt status */
165 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
166 /* Clear QMU interrupt status */
167 mtu3_writel(mbase, U3D_QISAR0, ~0x0);
168 }
169
170 /* disable all interrupts */
mtu3_intr_disable(struct mtu3 * mtu)171 static void mtu3_intr_disable(struct mtu3 *mtu)
172 {
173 /* Disable level 1 interrupts */
174 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
175 /* Disable endpoint interrupts */
176 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
177 mtu3_intr_status_clear(mtu);
178 }
179
180 /* enable system global interrupt */
mtu3_intr_enable(struct mtu3 * mtu)181 static void mtu3_intr_enable(struct mtu3 *mtu)
182 {
183 void __iomem *mbase = mtu->mac_base;
184 u32 value;
185
186 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
187 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
188 mtu3_writel(mbase, U3D_LV1IESR, value);
189
190 /* Enable U2 common USB interrupts */
191 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
192 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
193
194 if (mtu->is_u3_ip) {
195 /* Enable U3 LTSSM interrupts */
196 value = HOT_RST_INTR | WARM_RST_INTR |
197 ENTER_U3_INTR | EXIT_U3_INTR;
198 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
199 }
200
201 /* Enable QMU interrupts. */
202 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
203 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
204 mtu3_writel(mbase, U3D_QIESR1, value);
205
206 /* Enable speed change interrupt */
207 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
208 }
209
mtu3_set_speed(struct mtu3 * mtu,enum usb_device_speed speed)210 void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
211 {
212 void __iomem *mbase = mtu->mac_base;
213
214 if (speed > mtu->max_speed)
215 speed = mtu->max_speed;
216
217 switch (speed) {
218 case USB_SPEED_FULL:
219 /* disable U3 SS function */
220 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
221 /* disable HS function */
222 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
223 break;
224 case USB_SPEED_HIGH:
225 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
226 /* HS/FS detected by HW */
227 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
228 break;
229 case USB_SPEED_SUPER:
230 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
231 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
232 SSUSB_U3_PORT_SSP_SPEED);
233 break;
234 case USB_SPEED_SUPER_PLUS:
235 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
236 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
237 SSUSB_U3_PORT_SSP_SPEED);
238 break;
239 default:
240 dev_err(mtu->dev, "invalid speed: %s\n",
241 usb_speed_string(speed));
242 return;
243 }
244
245 mtu->speed = speed;
246 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
247 }
248
249 /* CSR registers will be reset to default value if port is disabled */
mtu3_csr_init(struct mtu3 * mtu)250 static void mtu3_csr_init(struct mtu3 *mtu)
251 {
252 void __iomem *mbase = mtu->mac_base;
253
254 if (mtu->is_u3_ip) {
255 /* disable LGO_U1/U2 by default */
256 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
257 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
258 /* enable accept LGO_U1/U2 link command from host */
259 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
260 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
261 /* device responses to u3_exit from host automatically */
262 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
263 /* automatically build U2 link when U3 detect fail */
264 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
265 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
266 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
267 }
268
269 /* delay about 0.1us from detecting reset to send chirp-K */
270 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
271 /* enable automatical HWRW from L1 */
272 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
273 }
274
275 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
mtu3_ep_reset(struct mtu3_ep * mep)276 static void mtu3_ep_reset(struct mtu3_ep *mep)
277 {
278 struct mtu3 *mtu = mep->mtu;
279 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
280
281 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
282 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
283 }
284
285 /* set/clear the stall and toggle bits for non-ep0 */
mtu3_ep_stall_set(struct mtu3_ep * mep,bool set)286 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
287 {
288 struct mtu3 *mtu = mep->mtu;
289 void __iomem *mbase = mtu->mac_base;
290 u8 epnum = mep->epnum;
291 u32 csr;
292
293 if (mep->is_in) { /* TX */
294 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
295 if (set)
296 csr |= TX_SENDSTALL;
297 else
298 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
299 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
300 } else { /* RX */
301 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
302 if (set)
303 csr |= RX_SENDSTALL;
304 else
305 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
306 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
307 }
308
309 if (!set) {
310 mtu3_ep_reset(mep);
311 mep->flags &= ~MTU3_EP_STALL;
312 } else {
313 mep->flags |= MTU3_EP_STALL;
314 }
315
316 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
317 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
318 }
319
mtu3_dev_on_off(struct mtu3 * mtu,int is_on)320 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
321 {
322 if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
323 mtu3_ss_func_set(mtu, is_on);
324 else
325 mtu3_hs_softconn_set(mtu, is_on);
326
327 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
328 usb_speed_string(mtu->speed), is_on ? "+" : "-");
329 }
330
mtu3_start(struct mtu3 * mtu)331 void mtu3_start(struct mtu3 *mtu)
332 {
333 void __iomem *mbase = mtu->mac_base;
334
335 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
336 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
337
338 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
339
340 mtu3_csr_init(mtu);
341 mtu3_set_speed(mtu, mtu->speed);
342
343 /* Initialize the default interrupts */
344 mtu3_intr_enable(mtu);
345 mtu->is_active = 1;
346
347 if (mtu->softconnect)
348 mtu3_dev_on_off(mtu, 1);
349 }
350
mtu3_stop(struct mtu3 * mtu)351 void mtu3_stop(struct mtu3 *mtu)
352 {
353 dev_dbg(mtu->dev, "%s\n", __func__);
354
355 mtu3_intr_disable(mtu);
356
357 if (mtu->softconnect)
358 mtu3_dev_on_off(mtu, 0);
359
360 mtu->is_active = 0;
361 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
362 }
363
364 /* for non-ep0 */
mtu3_config_ep(struct mtu3 * mtu,struct mtu3_ep * mep,int interval,int burst,int mult)365 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
366 int interval, int burst, int mult)
367 {
368 void __iomem *mbase = mtu->mac_base;
369 bool gen2cp = mtu->gen2cp;
370 int epnum = mep->epnum;
371 u32 csr0, csr1, csr2;
372 int fifo_sgsz, fifo_addr;
373 int num_pkts;
374
375 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
376 if (fifo_addr < 0) {
377 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
378 return -ENOMEM;
379 }
380 fifo_sgsz = ilog2(mep->fifo_seg_size);
381 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
382 mep->fifo_seg_size, mep->fifo_size);
383
384 if (mep->is_in) {
385 csr0 = TX_TXMAXPKTSZ(mep->maxp);
386 csr0 |= TX_DMAREQEN;
387
388 num_pkts = (burst + 1) * (mult + 1) - 1;
389 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
390 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
391
392 csr2 = TX_FIFOADDR(fifo_addr >> 4);
393 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
394
395 switch (mep->type) {
396 case USB_ENDPOINT_XFER_BULK:
397 csr1 |= TX_TYPE(TYPE_BULK);
398 break;
399 case USB_ENDPOINT_XFER_ISOC:
400 csr1 |= TX_TYPE(TYPE_ISO);
401 csr2 |= TX_BINTERVAL(interval);
402 break;
403 case USB_ENDPOINT_XFER_INT:
404 csr1 |= TX_TYPE(TYPE_INT);
405 csr2 |= TX_BINTERVAL(interval);
406 break;
407 }
408
409 /* Enable QMU Done interrupt */
410 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
411
412 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
413 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
414 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
415
416 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
417 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
418 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
419 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
420 } else {
421 csr0 = RX_RXMAXPKTSZ(mep->maxp);
422 csr0 |= RX_DMAREQEN;
423
424 num_pkts = (burst + 1) * (mult + 1) - 1;
425 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
426 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
427
428 csr2 = RX_FIFOADDR(fifo_addr >> 4);
429 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
430
431 switch (mep->type) {
432 case USB_ENDPOINT_XFER_BULK:
433 csr1 |= RX_TYPE(TYPE_BULK);
434 break;
435 case USB_ENDPOINT_XFER_ISOC:
436 csr1 |= RX_TYPE(TYPE_ISO);
437 csr2 |= RX_BINTERVAL(interval);
438 break;
439 case USB_ENDPOINT_XFER_INT:
440 csr1 |= RX_TYPE(TYPE_INT);
441 csr2 |= RX_BINTERVAL(interval);
442 break;
443 }
444
445 /*Enable QMU Done interrupt */
446 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
447
448 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
449 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
450 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
451
452 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
453 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
454 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
455 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
456 }
457
458 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
459 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
460 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
461 fifo_sgsz, mep->fifo_seg_size);
462
463 return 0;
464 }
465
466 /* for non-ep0 */
mtu3_deconfig_ep(struct mtu3 * mtu,struct mtu3_ep * mep)467 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
468 {
469 void __iomem *mbase = mtu->mac_base;
470 int epnum = mep->epnum;
471
472 if (mep->is_in) {
473 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
474 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
475 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
476 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
477 } else {
478 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
479 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
480 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
481 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
482 }
483
484 mtu3_ep_reset(mep);
485 ep_fifo_free(mep);
486
487 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
488 }
489
490 /*
491 * Two scenarios:
492 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
493 * are separated;
494 * 2. when supports only HS, the fifo is shared for all EPs, and
495 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
496 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
497 * so the total fifo size is 64B + @EPNTXFFSZ;
498 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
499 * starts from offset 64 and are divided into two equal parts for
500 * TX or RX EPs for simplification.
501 */
get_ep_fifo_config(struct mtu3 * mtu)502 static void get_ep_fifo_config(struct mtu3 *mtu)
503 {
504 struct mtu3_fifo_info *tx_fifo;
505 struct mtu3_fifo_info *rx_fifo;
506 u32 fifosize;
507
508 if (mtu->is_u3_ip) {
509 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
510 tx_fifo = &mtu->tx_fifo;
511 tx_fifo->base = 0;
512 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
513 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
514
515 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
516 rx_fifo = &mtu->rx_fifo;
517 rx_fifo->base = 0;
518 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
519 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
520 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
521 } else {
522 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
523 tx_fifo = &mtu->tx_fifo;
524 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
525 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
526 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
527
528 rx_fifo = &mtu->rx_fifo;
529 rx_fifo->base =
530 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
531 rx_fifo->limit = tx_fifo->limit;
532 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
533 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
534 }
535
536 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
537 __func__, tx_fifo->base, tx_fifo->limit,
538 rx_fifo->base, rx_fifo->limit);
539 }
540
mtu3_ep0_setup(struct mtu3 * mtu)541 void mtu3_ep0_setup(struct mtu3 *mtu)
542 {
543 u32 maxpacket = mtu->g.ep0->maxpacket;
544 u32 csr;
545
546 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
547
548 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
549 csr &= ~EP0_MAXPKTSZ_MSK;
550 csr |= EP0_MAXPKTSZ(maxpacket);
551 csr &= EP0_W1C_BITS;
552 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
553
554 /* Enable EP0 interrupt */
555 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
556 }
557
mtu3_mem_alloc(struct mtu3 * mtu)558 static int mtu3_mem_alloc(struct mtu3 *mtu)
559 {
560 void __iomem *mbase = mtu->mac_base;
561 struct mtu3_ep *ep_array;
562 int in_ep_num, out_ep_num;
563 u32 cap_epinfo;
564 int ret;
565 int i;
566
567 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
568 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
569 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
570
571 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
572 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
573 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
574
575 /* one for ep0, another is reserved */
576 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
577 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
578 if (ep_array == NULL)
579 return -ENOMEM;
580
581 mtu->ep_array = ep_array;
582 mtu->in_eps = ep_array;
583 mtu->out_eps = &ep_array[mtu->num_eps];
584 /* ep0 uses in_eps[0], out_eps[0] is reserved */
585 mtu->ep0 = mtu->in_eps;
586 mtu->ep0->mtu = mtu;
587 mtu->ep0->epnum = 0;
588
589 for (i = 1; i < mtu->num_eps; i++) {
590 struct mtu3_ep *mep = mtu->in_eps + i;
591
592 mep->fifo = &mtu->tx_fifo;
593 mep = mtu->out_eps + i;
594 mep->fifo = &mtu->rx_fifo;
595 }
596
597 get_ep_fifo_config(mtu);
598
599 ret = mtu3_qmu_init(mtu);
600 if (ret)
601 kfree(mtu->ep_array);
602
603 return ret;
604 }
605
mtu3_mem_free(struct mtu3 * mtu)606 static void mtu3_mem_free(struct mtu3 *mtu)
607 {
608 mtu3_qmu_exit(mtu);
609 kfree(mtu->ep_array);
610 }
611
mtu3_regs_init(struct mtu3 * mtu)612 static void mtu3_regs_init(struct mtu3 *mtu)
613 {
614 void __iomem *mbase = mtu->mac_base;
615
616 /* be sure interrupts are disabled before registration of ISR */
617 mtu3_intr_disable(mtu);
618
619 mtu3_csr_init(mtu);
620
621 /* U2/U3 detected by HW */
622 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
623 /* vbus detected by HW */
624 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
625 /* use new QMU format when HW version >= 0x1003 */
626 if (mtu->gen2cp)
627 mtu3_writel(mbase, U3D_QFCR, ~0x0);
628 }
629
mtu3_link_isr(struct mtu3 * mtu)630 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
631 {
632 void __iomem *mbase = mtu->mac_base;
633 enum usb_device_speed udev_speed;
634 u32 maxpkt = 64;
635 u32 link;
636 u32 speed;
637
638 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
639 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
640 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
641 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
642
643 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
644 return IRQ_NONE;
645
646 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
647
648 switch (speed) {
649 case MTU3_SPEED_FULL:
650 udev_speed = USB_SPEED_FULL;
651 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
652 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
653 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
654 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
655 LPM_BESL_STALL | LPM_BESLD_STALL);
656 break;
657 case MTU3_SPEED_HIGH:
658 udev_speed = USB_SPEED_HIGH;
659 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
660 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
661 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
662 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
663 LPM_BESL_STALL | LPM_BESLD_STALL);
664 break;
665 case MTU3_SPEED_SUPER:
666 udev_speed = USB_SPEED_SUPER;
667 maxpkt = 512;
668 break;
669 case MTU3_SPEED_SUPER_PLUS:
670 udev_speed = USB_SPEED_SUPER_PLUS;
671 maxpkt = 512;
672 break;
673 default:
674 udev_speed = USB_SPEED_UNKNOWN;
675 break;
676 }
677 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
678 mtu3_dbg_trace(mtu->dev, "link speed %s",
679 usb_speed_string(udev_speed));
680
681 mtu->g.speed = udev_speed;
682 mtu->g.ep0->maxpacket = maxpkt;
683 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
684
685 if (udev_speed == USB_SPEED_UNKNOWN)
686 mtu3_gadget_disconnect(mtu);
687 else
688 mtu3_ep0_setup(mtu);
689
690 return IRQ_HANDLED;
691 }
692
mtu3_u3_ltssm_isr(struct mtu3 * mtu)693 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
694 {
695 void __iomem *mbase = mtu->mac_base;
696 u32 ltssm;
697
698 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
699 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
700 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
701 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
702 trace_mtu3_u3_ltssm_isr(ltssm);
703
704 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
705 mtu3_gadget_reset(mtu);
706
707 if (ltssm & VBUS_FALL_INTR) {
708 mtu3_ss_func_set(mtu, false);
709 mtu3_gadget_reset(mtu);
710 }
711
712 if (ltssm & VBUS_RISE_INTR)
713 mtu3_ss_func_set(mtu, true);
714
715 if (ltssm & EXIT_U3_INTR)
716 mtu3_gadget_resume(mtu);
717
718 if (ltssm & ENTER_U3_INTR)
719 mtu3_gadget_suspend(mtu);
720
721 return IRQ_HANDLED;
722 }
723
mtu3_u2_common_isr(struct mtu3 * mtu)724 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
725 {
726 void __iomem *mbase = mtu->mac_base;
727 u32 u2comm;
728
729 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
730 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
731 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
732 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
733 trace_mtu3_u2_common_isr(u2comm);
734
735 if (u2comm & SUSPEND_INTR)
736 mtu3_gadget_suspend(mtu);
737
738 if (u2comm & RESUME_INTR)
739 mtu3_gadget_resume(mtu);
740
741 if (u2comm & RESET_INTR)
742 mtu3_gadget_reset(mtu);
743
744 return IRQ_HANDLED;
745 }
746
mtu3_irq(int irq,void * data)747 static irqreturn_t mtu3_irq(int irq, void *data)
748 {
749 struct mtu3 *mtu = (struct mtu3 *)data;
750 unsigned long flags;
751 u32 level1;
752
753 spin_lock_irqsave(&mtu->lock, flags);
754
755 /* U3D_LV1ISR is RU */
756 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
757 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
758
759 if (level1 & EP_CTRL_INTR)
760 mtu3_link_isr(mtu);
761
762 if (level1 & MAC2_INTR)
763 mtu3_u2_common_isr(mtu);
764
765 if (level1 & MAC3_INTR)
766 mtu3_u3_ltssm_isr(mtu);
767
768 if (level1 & BMU_INTR)
769 mtu3_ep0_isr(mtu);
770
771 if (level1 & QMU_INTR)
772 mtu3_qmu_isr(mtu);
773
774 spin_unlock_irqrestore(&mtu->lock, flags);
775
776 return IRQ_HANDLED;
777 }
778
mtu3_check_params(struct mtu3 * mtu)779 static void mtu3_check_params(struct mtu3 *mtu)
780 {
781 /* check the max_speed parameter */
782 switch (mtu->max_speed) {
783 case USB_SPEED_FULL:
784 case USB_SPEED_HIGH:
785 case USB_SPEED_SUPER:
786 case USB_SPEED_SUPER_PLUS:
787 break;
788 default:
789 dev_err(mtu->dev, "invalid max_speed: %s\n",
790 usb_speed_string(mtu->max_speed));
791 fallthrough;
792 case USB_SPEED_UNKNOWN:
793 /* default as SSP */
794 mtu->max_speed = USB_SPEED_SUPER_PLUS;
795 break;
796 }
797
798 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
799 mtu->max_speed = USB_SPEED_HIGH;
800
801 mtu->speed = mtu->max_speed;
802
803 dev_info(mtu->dev, "max_speed: %s\n",
804 usb_speed_string(mtu->max_speed));
805 }
806
mtu3_hw_init(struct mtu3 * mtu)807 static int mtu3_hw_init(struct mtu3 *mtu)
808 {
809 u32 value;
810 int ret;
811
812 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
813 mtu->hw_version = IP_TRUNK_VERS(value);
814 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
815
816 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
817 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
818
819 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
820 mtu->is_u3_ip ? "U3" : "U2");
821
822 mtu3_check_params(mtu);
823
824 mtu3_device_reset(mtu);
825
826 ret = mtu3_device_enable(mtu);
827 if (ret) {
828 dev_err(mtu->dev, "device enable failed %d\n", ret);
829 return ret;
830 }
831
832 ret = mtu3_mem_alloc(mtu);
833 if (ret)
834 return -ENOMEM;
835
836 mtu3_regs_init(mtu);
837
838 return 0;
839 }
840
mtu3_hw_exit(struct mtu3 * mtu)841 static void mtu3_hw_exit(struct mtu3 *mtu)
842 {
843 mtu3_device_disable(mtu);
844 mtu3_mem_free(mtu);
845 }
846
847 /*
848 * we set 32-bit DMA mask by default, here check whether the controller
849 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
850 */
mtu3_set_dma_mask(struct mtu3 * mtu)851 static int mtu3_set_dma_mask(struct mtu3 *mtu)
852 {
853 struct device *dev = mtu->dev;
854 bool is_36bit = false;
855 int ret = 0;
856 u32 value;
857
858 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
859 if (value & DMA_ADDR_36BIT) {
860 is_36bit = true;
861 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
862 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
863 if (ret) {
864 is_36bit = false;
865 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
866 }
867 }
868 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
869
870 return ret;
871 }
872
ssusb_gadget_init(struct ssusb_mtk * ssusb)873 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
874 {
875 struct device *dev = ssusb->dev;
876 struct platform_device *pdev = to_platform_device(dev);
877 struct mtu3 *mtu = NULL;
878 int ret = -ENOMEM;
879
880 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
881 if (mtu == NULL)
882 return -ENOMEM;
883
884 mtu->irq = platform_get_irq(pdev, 0);
885 if (mtu->irq < 0)
886 return mtu->irq;
887 dev_info(dev, "irq %d\n", mtu->irq);
888
889 mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
890 if (IS_ERR(mtu->mac_base)) {
891 dev_err(dev, "error mapping memory for dev mac\n");
892 return PTR_ERR(mtu->mac_base);
893 }
894
895 spin_lock_init(&mtu->lock);
896 mtu->dev = dev;
897 mtu->ippc_base = ssusb->ippc_base;
898 ssusb->mac_base = mtu->mac_base;
899 ssusb->u3d = mtu;
900 mtu->ssusb = ssusb;
901 mtu->max_speed = usb_get_maximum_speed(dev);
902
903 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
904 mtu->mac_base, mtu->ippc_base);
905
906 ret = mtu3_hw_init(mtu);
907 if (ret) {
908 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
909 return ret;
910 }
911
912 ret = mtu3_set_dma_mask(mtu);
913 if (ret) {
914 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
915 goto dma_mask_err;
916 }
917
918 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
919 if (ret) {
920 dev_err(dev, "request irq %d failed!\n", mtu->irq);
921 goto irq_err;
922 }
923
924 device_init_wakeup(dev, true);
925
926 ret = mtu3_gadget_setup(mtu);
927 if (ret) {
928 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
929 goto gadget_err;
930 }
931
932 /* init as host mode, power down device IP for power saving */
933 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
934 mtu3_stop(mtu);
935
936 ssusb_dev_debugfs_init(ssusb);
937
938 dev_dbg(dev, " %s() done...\n", __func__);
939
940 return 0;
941
942 gadget_err:
943 device_init_wakeup(dev, false);
944
945 dma_mask_err:
946 irq_err:
947 mtu3_hw_exit(mtu);
948 ssusb->u3d = NULL;
949 dev_err(dev, " %s() fail...\n", __func__);
950
951 return ret;
952 }
953
ssusb_gadget_exit(struct ssusb_mtk * ssusb)954 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
955 {
956 struct mtu3 *mtu = ssusb->u3d;
957
958 mtu3_gadget_cleanup(mtu);
959 device_init_wakeup(ssusb->dev, false);
960 mtu3_hw_exit(mtu);
961 }
962