1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #include <linux/bitfield.h>
12
13 #include "chip.h"
14 #include "global1.h"
15
mv88e6xxx_g1_read(struct mv88e6xxx_chip * chip,int reg,u16 * val)16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17 {
18 int addr = chip->info->global1_addr;
19
20 return mv88e6xxx_read(chip, addr, reg, val);
21 }
22
mv88e6xxx_g1_write(struct mv88e6xxx_chip * chip,int reg,u16 val)23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24 {
25 int addr = chip->info->global1_addr;
26
27 return mv88e6xxx_write(chip, addr, reg, val);
28 }
29
mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip * chip,int reg,int bit,int val)30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 bit, int val)
32 {
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 bit, val);
35 }
36
mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip * chip,int reg,u16 mask,u16 val)37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 u16 mask, u16 val)
39 {
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 mask, val);
42 }
43
44 /* Offset 0x00: Switch Global Status Register */
45
mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip * chip)46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47 {
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
51 }
52
mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54 {
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
58 }
59
mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61 {
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65 }
66
mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip * chip)67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68 {
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
74 */
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76 }
77
mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip * chip)78 void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
79 {
80 const unsigned long timeout = jiffies + 1 * HZ;
81 u16 val;
82 int err;
83
84 /* Wait up to 1 second for the switch to finish reading the
85 * EEPROM.
86 */
87 while (time_before(jiffies, timeout)) {
88 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
89 if (err) {
90 dev_err(chip->dev, "Error reading status");
91 return;
92 }
93
94 /* If the switch is still resetting, it may not
95 * respond on the bus, and so MDIO read returns
96 * 0xffff. Differentiate between that, and waiting for
97 * the EEPROM to be done by bit 0 being set.
98 */
99 if (val != 0xffff &&
100 val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE))
101 return;
102
103 usleep_range(1000, 2000);
104 }
105
106 dev_err(chip->dev, "Timeout waiting for EEPROM done");
107 }
108
109 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
110 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
111 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
112 */
mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip * chip,u8 * addr)113 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
114 {
115 u16 reg;
116 int err;
117
118 reg = (addr[0] << 8) | addr[1];
119 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
120 if (err)
121 return err;
122
123 reg = (addr[2] << 8) | addr[3];
124 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
125 if (err)
126 return err;
127
128 reg = (addr[4] << 8) | addr[5];
129 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
130 if (err)
131 return err;
132
133 return 0;
134 }
135
136 /* Offset 0x04: Switch Global Control Register */
137
mv88e6185_g1_reset(struct mv88e6xxx_chip * chip)138 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
139 {
140 u16 val;
141 int err;
142
143 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
144 * the PPU, including re-doing PHY detection and initialization
145 */
146 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
147 if (err)
148 return err;
149
150 val |= MV88E6XXX_G1_CTL1_SW_RESET;
151 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
152
153 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
154 if (err)
155 return err;
156
157 err = mv88e6xxx_g1_wait_init_ready(chip);
158 if (err)
159 return err;
160
161 return mv88e6185_g1_wait_ppu_polling(chip);
162 }
163
mv88e6250_g1_reset(struct mv88e6xxx_chip * chip)164 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
165 {
166 u16 val;
167 int err;
168
169 /* Set the SWReset bit 15 */
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
171 if (err)
172 return err;
173
174 val |= MV88E6XXX_G1_CTL1_SW_RESET;
175
176 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
177 if (err)
178 return err;
179
180 return mv88e6xxx_g1_wait_init_ready(chip);
181 }
182
mv88e6352_g1_reset(struct mv88e6xxx_chip * chip)183 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
184 {
185 int err;
186
187 err = mv88e6250_g1_reset(chip);
188 if (err)
189 return err;
190
191 return mv88e6352_g1_wait_ppu_polling(chip);
192 }
193
mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip * chip)194 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
195 {
196 u16 val;
197 int err;
198
199 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
200 if (err)
201 return err;
202
203 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
204
205 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
206 if (err)
207 return err;
208
209 return mv88e6185_g1_wait_ppu_polling(chip);
210 }
211
mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip * chip)212 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
213 {
214 u16 val;
215 int err;
216
217 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
218 if (err)
219 return err;
220
221 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
222
223 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
224 if (err)
225 return err;
226
227 return mv88e6185_g1_wait_ppu_disabled(chip);
228 }
229
mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip * chip,int mtu)230 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
231 {
232 u16 val;
233 int err;
234
235 mtu += ETH_HLEN + ETH_FCS_LEN;
236
237 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
238 if (err)
239 return err;
240
241 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
242
243 if (mtu > 1518)
244 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
245
246 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
247 }
248
249 /* Offset 0x10: IP-PRI Mapping Register 0
250 * Offset 0x11: IP-PRI Mapping Register 1
251 * Offset 0x12: IP-PRI Mapping Register 2
252 * Offset 0x13: IP-PRI Mapping Register 3
253 * Offset 0x14: IP-PRI Mapping Register 4
254 * Offset 0x15: IP-PRI Mapping Register 5
255 * Offset 0x16: IP-PRI Mapping Register 6
256 * Offset 0x17: IP-PRI Mapping Register 7
257 */
258
mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip * chip)259 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
260 {
261 int err;
262
263 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
264 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
265 if (err)
266 return err;
267
268 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
269 if (err)
270 return err;
271
272 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
273 if (err)
274 return err;
275
276 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
277 if (err)
278 return err;
279
280 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
281 if (err)
282 return err;
283
284 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
285 if (err)
286 return err;
287
288 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
289 if (err)
290 return err;
291
292 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
293 if (err)
294 return err;
295
296 return 0;
297 }
298
299 /* Offset 0x18: IEEE-PRI Register */
300
mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)301 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
302 {
303 /* Reset the IEEE Tag priorities to defaults */
304 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
305 }
306
mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)307 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
308 {
309 /* Reset the IEEE Tag priorities to defaults */
310 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
311 }
312
313 /* Offset 0x1a: Monitor Control */
314 /* Offset 0x1a: Monitor & MGMT Control on some devices */
315
mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)316 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
317 enum mv88e6xxx_egress_direction direction,
318 int port)
319 {
320 int *dest_port_chip;
321 u16 reg;
322 int err;
323
324 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
325 if (err)
326 return err;
327
328 switch (direction) {
329 case MV88E6XXX_EGRESS_DIR_INGRESS:
330 dest_port_chip = &chip->ingress_dest_port;
331 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
332 reg |= port <<
333 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
334 break;
335 case MV88E6XXX_EGRESS_DIR_EGRESS:
336 dest_port_chip = &chip->egress_dest_port;
337 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
338 reg |= port <<
339 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
340 break;
341 default:
342 return -EINVAL;
343 }
344
345 err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
346 if (!err)
347 *dest_port_chip = port;
348
349 return err;
350 }
351
352 /* Older generations also call this the ARP destination. It has been
353 * generalized in more modern devices such that more than ARP can
354 * egress it
355 */
mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)356 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
357 {
358 u16 reg;
359 int err;
360
361 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
362 if (err)
363 return err;
364
365 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
366 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
367
368 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
369 }
370
mv88e6390_g1_monitor_write(struct mv88e6xxx_chip * chip,u16 pointer,u8 data)371 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
372 u16 pointer, u8 data)
373 {
374 u16 reg;
375
376 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
377
378 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
379 }
380
mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)381 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
382 enum mv88e6xxx_egress_direction direction,
383 int port)
384 {
385 int *dest_port_chip;
386 u16 ptr;
387 int err;
388
389 switch (direction) {
390 case MV88E6XXX_EGRESS_DIR_INGRESS:
391 dest_port_chip = &chip->ingress_dest_port;
392 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
393 break;
394 case MV88E6XXX_EGRESS_DIR_EGRESS:
395 dest_port_chip = &chip->egress_dest_port;
396 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
397 break;
398 default:
399 return -EINVAL;
400 }
401
402 err = mv88e6390_g1_monitor_write(chip, ptr, port);
403 if (!err)
404 *dest_port_chip = port;
405
406 return err;
407 }
408
mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)409 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
410 {
411 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
412
413 /* Use the default high priority for management frames sent to
414 * the CPU.
415 */
416 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
417
418 return mv88e6390_g1_monitor_write(chip, ptr, port);
419 }
420
mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)421 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
422 {
423 u16 ptr;
424 int err;
425
426 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
427 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
428 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
429 if (err)
430 return err;
431
432 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
433 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
434 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
435 if (err)
436 return err;
437
438 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
439 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
440 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
441 if (err)
442 return err;
443
444 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
445 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
446 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
447 if (err)
448 return err;
449
450 return 0;
451 }
452
453 /* Offset 0x1c: Global Control 2 */
454
mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip * chip,u16 mask,u16 val)455 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
456 u16 val)
457 {
458 u16 reg;
459 int err;
460
461 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
462 if (err)
463 return err;
464
465 reg &= ~mask;
466 reg |= val & mask;
467
468 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
469 }
470
mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip * chip,int port)471 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
472 {
473 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
474
475 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
476 }
477
mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip * chip)478 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
479 {
480 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
481 MV88E6085_G1_CTL2_RM_ENABLE, 0);
482 }
483
mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip * chip)484 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
485 {
486 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
487 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
488 }
489
mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip * chip)490 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
491 {
492 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
493 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
494 }
495
mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)496 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
497 {
498 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
499 MV88E6390_G1_CTL2_HIST_MODE_RX |
500 MV88E6390_G1_CTL2_HIST_MODE_TX);
501 }
502
mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip * chip,int index)503 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
504 {
505 return mv88e6xxx_g1_ctl2_mask(chip,
506 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
507 index);
508 }
509
510 /* Offset 0x1d: Statistics Operation 2 */
511
mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip * chip)512 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
513 {
514 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
515
516 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
517 }
518
mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)519 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
520 {
521 u16 val;
522 int err;
523
524 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
525 if (err)
526 return err;
527
528 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
529
530 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
531
532 return err;
533 }
534
mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)535 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
536 {
537 int err;
538
539 /* Snapshot the hardware statistics counters for this port. */
540 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
541 MV88E6XXX_G1_STATS_OP_BUSY |
542 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
543 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
544 if (err)
545 return err;
546
547 /* Wait for the snapshotting to complete. */
548 return mv88e6xxx_g1_stats_wait(chip);
549 }
550
mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)551 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
552 {
553 port = (port + 1) << 5;
554
555 return mv88e6xxx_g1_stats_snapshot(chip, port);
556 }
557
mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)558 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
559 {
560 int err;
561
562 port = (port + 1) << 5;
563
564 /* Snapshot the hardware statistics counters for this port. */
565 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
566 MV88E6XXX_G1_STATS_OP_BUSY |
567 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
568 if (err)
569 return err;
570
571 /* Wait for the snapshotting to complete. */
572 return mv88e6xxx_g1_stats_wait(chip);
573 }
574
mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip * chip,int stat,u32 * val)575 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
576 {
577 u32 value;
578 u16 reg;
579 int err;
580
581 *val = 0;
582
583 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
584 MV88E6XXX_G1_STATS_OP_BUSY |
585 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
586 if (err)
587 return;
588
589 err = mv88e6xxx_g1_stats_wait(chip);
590 if (err)
591 return;
592
593 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
594 if (err)
595 return;
596
597 value = reg << 16;
598
599 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
600 if (err)
601 return;
602
603 *val = value | reg;
604 }
605
mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip * chip)606 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
607 {
608 int err;
609 u16 val;
610
611 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
612 if (err)
613 return err;
614
615 /* Keep the histogram mode bits */
616 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
617 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
618
619 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
620 if (err)
621 return err;
622
623 /* Wait for the flush to complete. */
624 return mv88e6xxx_g1_stats_wait(chip);
625 }
626