1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
32 #include <net/dsa.h>
33
34 #include "chip.h"
35 #include "devlink.h"
36 #include "global1.h"
37 #include "global2.h"
38 #include "hwtstamp.h"
39 #include "phy.h"
40 #include "port.h"
41 #include "ptp.h"
42 #include "serdes.h"
43 #include "smi.h"
44
assert_reg_lock(struct mv88e6xxx_chip * chip)45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46 {
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
49 dump_stack();
50 }
51 }
52
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
54 {
55 int err;
56
57 assert_reg_lock(chip);
58
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
60 if (err)
61 return err;
62
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
64 addr, reg, *val);
65
66 return 0;
67 }
68
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
70 {
71 int err;
72
73 assert_reg_lock(chip);
74
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
76 if (err)
77 return err;
78
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
80 addr, reg, val);
81
82 return 0;
83 }
84
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87 {
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106 }
107
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110 {
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113 }
114
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
116 {
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125 }
126
mv88e6xxx_g1_irq_mask(struct irq_data * d)127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128 {
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133 }
134
mv88e6xxx_g1_irq_unmask(struct irq_data * d)135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136 {
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141 }
142
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
144 {
145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
149 u16 ctl1;
150 int err;
151
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
155
156 if (err)
157 goto out;
158
159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
167 }
168
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
174 unlock:
175 mv88e6xxx_reg_unlock(chip);
176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
181 out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183 }
184
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186 {
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190 }
191
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193 {
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
196 mv88e6xxx_reg_lock(chip);
197 }
198
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200 {
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
214 if (err)
215 goto out;
216
217 out:
218 mv88e6xxx_reg_unlock(chip);
219 }
220
221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227 };
228
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232 {
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240 }
241
242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245 };
246
247 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
249 {
250 int irq, virq;
251 u16 mask;
252
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
256
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
259 irq_dispose_mapping(virq);
260 }
261
262 irq_domain_remove(chip->g1_irq.domain);
263 }
264
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266 {
267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
271 free_irq(chip->irq, chip);
272
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
276 }
277
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
279 {
280 int err, irq, virq;
281 u16 reg, mask;
282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
297 if (err)
298 goto out_mapping;
299
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
301
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
303 if (err)
304 goto out_disable;
305
306 /* Reading the interrupt status clears (most of) them */
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
308 if (err)
309 goto out_disable;
310
311 return 0;
312
313 out_disable:
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
316
317 out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
324
325 return err;
326 }
327
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329 {
330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
350 IRQF_ONESHOT | IRQF_SHARED,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357 }
358
mv88e6xxx_irq_poll(struct kthread_work * work)359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
360 {
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368 }
369
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371 {
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389 }
390
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392 {
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
395
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
399 }
400
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403 {
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421 }
422
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
426 {
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
434 if (err)
435 return err;
436
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
454 restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
457
458 return err;
459 }
460
mv88e6xxx_phy_is_internal(struct dsa_switch * ds,int port)461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462 {
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466 }
467
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469 {
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482 }
483
mv88e6xxx_serdes_pcs_get_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486 {
487 struct mv88e6xxx_chip *chip = ds->priv;
488 u8 lane;
489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501 }
502
mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip * chip,int port,unsigned int mode,phy_interface_t interface,const unsigned long * advertise)503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507 {
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
509 u8 lane;
510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
513 if (lane)
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519 }
520
mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch * ds,int port)521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522 {
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
526 u8 lane;
527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
533 if (lane)
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540 }
541
mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip * chip,int port,unsigned int mode,int speed,int duplex)542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545 {
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
547 u8 lane;
548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane)
552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557 }
558
mv88e6065_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562 {
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570 }
571
mv88e6185_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575 {
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583 }
584
mv88e6341_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588 {
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597 }
598
mv88e6352_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602 {
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608 }
609
mv88e6390_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613 {
614 if (port >= 9) {
615 phylink_set(mask, 2500baseX_Full);
616 phylink_set(mask, 2500baseT_Full);
617 }
618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624 }
625
mv88e6390x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629 {
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636 }
637
mv88e6xxx_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
639 unsigned long *supported,
640 struct phylink_link_state *state)
641 {
642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
643 struct mv88e6xxx_chip *chip = ds->priv;
644
645 /* Allow all the expected bits */
646 phylink_set(mask, Autoneg);
647 phylink_set(mask, Pause);
648 phylink_set_port_modes(mask);
649
650 if (chip->info->ops->phylink_validate)
651 chip->info->ops->phylink_validate(chip, port, mask, state);
652
653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
654 bitmap_and(state->advertising, state->advertising, mask,
655 __ETHTOOL_LINK_MODE_MASK_NBITS);
656
657 /* We can only operate at 2500BaseX or 1000BaseX. If requested
658 * to advertise both, only report advertising at 2500BaseX.
659 */
660 phylink_helper_basex_speed(state);
661 }
662
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
664 unsigned int mode,
665 const struct phylink_link_state *state)
666 {
667 struct mv88e6xxx_chip *chip = ds->priv;
668 struct mv88e6xxx_port *p;
669 int err = 0;
670
671 p = &chip->ports[port];
672
673 mv88e6xxx_reg_lock(chip);
674
675 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
676 /* In inband mode, the link may come up at any time while the
677 * link is not forced down. Force the link down while we
678 * reconfigure the interface mode.
679 */
680 if (mode == MLO_AN_INBAND &&
681 p->interface != state->interface &&
682 chip->info->ops->port_set_link)
683 chip->info->ops->port_set_link(chip, port,
684 LINK_FORCED_DOWN);
685
686 err = mv88e6xxx_port_config_interface(chip, port,
687 state->interface);
688 if (err && err != -EOPNOTSUPP)
689 goto err_unlock;
690
691 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
692 state->interface,
693 state->advertising);
694 /* FIXME: we should restart negotiation if something changed -
695 * which is something we get if we convert to using phylinks
696 * PCS operations.
697 */
698 if (err > 0)
699 err = 0;
700 }
701
702 /* Undo the forced down state above after completing configuration
703 * irrespective of its state on entry, which allows the link to come
704 * up in the in-band case where there is no separate SERDES. Also
705 * ensure that the link can come up if the PPU is in use and we are
706 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
707 */
708 if (chip->info->ops->port_set_link &&
709 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
710 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
711 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
712
713 p->interface = state->interface;
714
715 err_unlock:
716 mv88e6xxx_reg_unlock(chip);
717
718 if (err && err != -EOPNOTSUPP)
719 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
720 }
721
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)722 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
723 unsigned int mode,
724 phy_interface_t interface)
725 {
726 struct mv88e6xxx_chip *chip = ds->priv;
727 const struct mv88e6xxx_ops *ops;
728 int err = 0;
729
730 ops = chip->info->ops;
731
732 mv88e6xxx_reg_lock(chip);
733 /* Internal PHYs propagate their configuration directly to the MAC.
734 * External PHYs depend on whether the PPU is enabled for this port.
735 */
736 if (((!mv88e6xxx_phy_is_internal(ds, port) &&
737 !mv88e6xxx_port_ppu_updates(chip, port)) ||
738 mode == MLO_AN_FIXED) && ops->port_set_link)
739 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
740 mv88e6xxx_reg_unlock(chip);
741
742 if (err)
743 dev_err(chip->dev,
744 "p%d: failed to force MAC link down\n", port);
745 }
746
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)747 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
748 unsigned int mode, phy_interface_t interface,
749 struct phy_device *phydev,
750 int speed, int duplex,
751 bool tx_pause, bool rx_pause)
752 {
753 struct mv88e6xxx_chip *chip = ds->priv;
754 const struct mv88e6xxx_ops *ops;
755 int err = 0;
756
757 ops = chip->info->ops;
758
759 mv88e6xxx_reg_lock(chip);
760 /* Internal PHYs propagate their configuration directly to the MAC.
761 * External PHYs depend on whether the PPU is enabled for this port.
762 */
763 if ((!mv88e6xxx_phy_is_internal(ds, port) &&
764 !mv88e6xxx_port_ppu_updates(chip, port)) ||
765 mode == MLO_AN_FIXED) {
766 /* FIXME: for an automedia port, should we force the link
767 * down here - what if the link comes up due to "other" media
768 * while we're bringing the port up, how is the exclusivity
769 * handled in the Marvell hardware? E.g. port 2 on 88E6390
770 * shared between internal PHY and Serdes.
771 */
772 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
773 duplex);
774 if (err)
775 goto error;
776
777 if (ops->port_set_speed_duplex) {
778 err = ops->port_set_speed_duplex(chip, port,
779 speed, duplex);
780 if (err && err != -EOPNOTSUPP)
781 goto error;
782 }
783
784 if (ops->port_set_link)
785 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
786 }
787 error:
788 mv88e6xxx_reg_unlock(chip);
789
790 if (err && err != -EOPNOTSUPP)
791 dev_err(ds->dev,
792 "p%d: failed to configure MAC link up\n", port);
793 }
794
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)795 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
796 {
797 if (!chip->info->ops->stats_snapshot)
798 return -EOPNOTSUPP;
799
800 return chip->info->ops->stats_snapshot(chip, port);
801 }
802
803 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
804 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
805 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
806 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
807 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
808 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
809 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
810 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
811 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
812 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
813 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
814 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
815 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
816 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
817 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
818 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
819 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
820 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
821 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
822 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
823 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
824 { "single", 4, 0x14, STATS_TYPE_BANK0, },
825 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
826 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
827 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
828 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
829 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
830 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
831 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
832 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
833 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
834 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
835 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
836 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
837 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
838 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
839 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
840 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
841 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
842 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
843 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
844 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
845 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
846 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
847 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
848 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
849 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
850 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
851 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
852 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
853 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
854 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
855 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
856 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
857 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
858 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
859 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
860 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
861 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
862 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
863 };
864
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)865 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
866 struct mv88e6xxx_hw_stat *s,
867 int port, u16 bank1_select,
868 u16 histogram)
869 {
870 u32 low;
871 u32 high = 0;
872 u16 reg = 0;
873 int err;
874 u64 value;
875
876 switch (s->type) {
877 case STATS_TYPE_PORT:
878 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
879 if (err)
880 return U64_MAX;
881
882 low = reg;
883 if (s->size == 4) {
884 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
885 if (err)
886 return U64_MAX;
887 low |= ((u32)reg) << 16;
888 }
889 break;
890 case STATS_TYPE_BANK1:
891 reg = bank1_select;
892 fallthrough;
893 case STATS_TYPE_BANK0:
894 reg |= s->reg | histogram;
895 mv88e6xxx_g1_stats_read(chip, reg, &low);
896 if (s->size == 8)
897 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
898 break;
899 default:
900 return U64_MAX;
901 }
902 value = (((u64)high) << 32) | low;
903 return value;
904 }
905
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)906 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
907 uint8_t *data, int types)
908 {
909 struct mv88e6xxx_hw_stat *stat;
910 int i, j;
911
912 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
913 stat = &mv88e6xxx_hw_stats[i];
914 if (stat->type & types) {
915 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
916 ETH_GSTRING_LEN);
917 j++;
918 }
919 }
920
921 return j;
922 }
923
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)924 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
925 uint8_t *data)
926 {
927 return mv88e6xxx_stats_get_strings(chip, data,
928 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
929 }
930
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)931 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
932 uint8_t *data)
933 {
934 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
935 }
936
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)937 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
938 uint8_t *data)
939 {
940 return mv88e6xxx_stats_get_strings(chip, data,
941 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
942 }
943
944 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
945 "atu_member_violation",
946 "atu_miss_violation",
947 "atu_full_violation",
948 "vtu_member_violation",
949 "vtu_miss_violation",
950 };
951
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)952 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
953 {
954 unsigned int i;
955
956 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
957 strlcpy(data + i * ETH_GSTRING_LEN,
958 mv88e6xxx_atu_vtu_stats_strings[i],
959 ETH_GSTRING_LEN);
960 }
961
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)962 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
963 u32 stringset, uint8_t *data)
964 {
965 struct mv88e6xxx_chip *chip = ds->priv;
966 int count = 0;
967
968 if (stringset != ETH_SS_STATS)
969 return;
970
971 mv88e6xxx_reg_lock(chip);
972
973 if (chip->info->ops->stats_get_strings)
974 count = chip->info->ops->stats_get_strings(chip, data);
975
976 if (chip->info->ops->serdes_get_strings) {
977 data += count * ETH_GSTRING_LEN;
978 count = chip->info->ops->serdes_get_strings(chip, port, data);
979 }
980
981 data += count * ETH_GSTRING_LEN;
982 mv88e6xxx_atu_vtu_get_strings(data);
983
984 mv88e6xxx_reg_unlock(chip);
985 }
986
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)987 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
988 int types)
989 {
990 struct mv88e6xxx_hw_stat *stat;
991 int i, j;
992
993 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
994 stat = &mv88e6xxx_hw_stats[i];
995 if (stat->type & types)
996 j++;
997 }
998 return j;
999 }
1000
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1001 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1002 {
1003 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1004 STATS_TYPE_PORT);
1005 }
1006
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1007 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1008 {
1009 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1010 }
1011
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1012 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1013 {
1014 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1015 STATS_TYPE_BANK1);
1016 }
1017
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1018 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1019 {
1020 struct mv88e6xxx_chip *chip = ds->priv;
1021 int serdes_count = 0;
1022 int count = 0;
1023
1024 if (sset != ETH_SS_STATS)
1025 return 0;
1026
1027 mv88e6xxx_reg_lock(chip);
1028 if (chip->info->ops->stats_get_sset_count)
1029 count = chip->info->ops->stats_get_sset_count(chip);
1030 if (count < 0)
1031 goto out;
1032
1033 if (chip->info->ops->serdes_get_sset_count)
1034 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1035 port);
1036 if (serdes_count < 0) {
1037 count = serdes_count;
1038 goto out;
1039 }
1040 count += serdes_count;
1041 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1042
1043 out:
1044 mv88e6xxx_reg_unlock(chip);
1045
1046 return count;
1047 }
1048
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1049 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1050 uint64_t *data, int types,
1051 u16 bank1_select, u16 histogram)
1052 {
1053 struct mv88e6xxx_hw_stat *stat;
1054 int i, j;
1055
1056 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1057 stat = &mv88e6xxx_hw_stats[i];
1058 if (stat->type & types) {
1059 mv88e6xxx_reg_lock(chip);
1060 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1061 bank1_select,
1062 histogram);
1063 mv88e6xxx_reg_unlock(chip);
1064
1065 j++;
1066 }
1067 }
1068 return j;
1069 }
1070
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1071 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1072 uint64_t *data)
1073 {
1074 return mv88e6xxx_stats_get_stats(chip, port, data,
1075 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1076 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1077 }
1078
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1079 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1080 uint64_t *data)
1081 {
1082 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1083 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1084 }
1085
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1086 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1087 uint64_t *data)
1088 {
1089 return mv88e6xxx_stats_get_stats(chip, port, data,
1090 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1091 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1092 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1093 }
1094
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1095 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1096 uint64_t *data)
1097 {
1098 return mv88e6xxx_stats_get_stats(chip, port, data,
1099 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1100 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1101 0);
1102 }
1103
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1104 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1105 uint64_t *data)
1106 {
1107 *data++ = chip->ports[port].atu_member_violation;
1108 *data++ = chip->ports[port].atu_miss_violation;
1109 *data++ = chip->ports[port].atu_full_violation;
1110 *data++ = chip->ports[port].vtu_member_violation;
1111 *data++ = chip->ports[port].vtu_miss_violation;
1112 }
1113
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1114 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116 {
1117 int count = 0;
1118
1119 if (chip->info->ops->stats_get_stats)
1120 count = chip->info->ops->stats_get_stats(chip, port, data);
1121
1122 mv88e6xxx_reg_lock(chip);
1123 if (chip->info->ops->serdes_get_stats) {
1124 data += count;
1125 count = chip->info->ops->serdes_get_stats(chip, port, data);
1126 }
1127 data += count;
1128 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1129 mv88e6xxx_reg_unlock(chip);
1130 }
1131
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1132 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1133 uint64_t *data)
1134 {
1135 struct mv88e6xxx_chip *chip = ds->priv;
1136 int ret;
1137
1138 mv88e6xxx_reg_lock(chip);
1139
1140 ret = mv88e6xxx_stats_snapshot(chip, port);
1141 mv88e6xxx_reg_unlock(chip);
1142
1143 if (ret < 0)
1144 return;
1145
1146 mv88e6xxx_get_stats(chip, port, data);
1147
1148 }
1149
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1150 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1151 {
1152 struct mv88e6xxx_chip *chip = ds->priv;
1153 int len;
1154
1155 len = 32 * sizeof(u16);
1156 if (chip->info->ops->serdes_get_regs_len)
1157 len += chip->info->ops->serdes_get_regs_len(chip, port);
1158
1159 return len;
1160 }
1161
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1162 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1163 struct ethtool_regs *regs, void *_p)
1164 {
1165 struct mv88e6xxx_chip *chip = ds->priv;
1166 int err;
1167 u16 reg;
1168 u16 *p = _p;
1169 int i;
1170
1171 regs->version = chip->info->prod_num;
1172
1173 memset(p, 0xff, 32 * sizeof(u16));
1174
1175 mv88e6xxx_reg_lock(chip);
1176
1177 for (i = 0; i < 32; i++) {
1178
1179 err = mv88e6xxx_port_read(chip, port, i, ®);
1180 if (!err)
1181 p[i] = reg;
1182 }
1183
1184 if (chip->info->ops->serdes_get_regs)
1185 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1186
1187 mv88e6xxx_reg_unlock(chip);
1188 }
1189
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1190 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1191 struct ethtool_eee *e)
1192 {
1193 /* Nothing to do on the port's MAC */
1194 return 0;
1195 }
1196
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1197 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1198 struct ethtool_eee *e)
1199 {
1200 /* Nothing to do on the port's MAC */
1201 return 0;
1202 }
1203
1204 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1205 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1206 {
1207 struct dsa_switch *ds = chip->ds;
1208 struct dsa_switch_tree *dst = ds->dst;
1209 struct net_device *br;
1210 struct dsa_port *dp;
1211 bool found = false;
1212 u16 pvlan;
1213
1214 list_for_each_entry(dp, &dst->ports, list) {
1215 if (dp->ds->index == dev && dp->index == port) {
1216 found = true;
1217 break;
1218 }
1219 }
1220
1221 /* Prevent frames from unknown switch or port */
1222 if (!found)
1223 return 0;
1224
1225 /* Frames from DSA links and CPU ports can egress any local port */
1226 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1227 return mv88e6xxx_port_mask(chip);
1228
1229 br = dp->bridge_dev;
1230 pvlan = 0;
1231
1232 /* Frames from user ports can egress any local DSA links and CPU ports,
1233 * as well as any local member of their bridge group.
1234 */
1235 list_for_each_entry(dp, &dst->ports, list)
1236 if (dp->ds == ds &&
1237 (dp->type == DSA_PORT_TYPE_CPU ||
1238 dp->type == DSA_PORT_TYPE_DSA ||
1239 (br && dp->bridge_dev == br)))
1240 pvlan |= BIT(dp->index);
1241
1242 return pvlan;
1243 }
1244
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1245 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1246 {
1247 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1248
1249 /* prevent frames from going back out of the port they came in on */
1250 output_ports &= ~BIT(port);
1251
1252 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1253 }
1254
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1255 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1256 u8 state)
1257 {
1258 struct mv88e6xxx_chip *chip = ds->priv;
1259 int err;
1260
1261 mv88e6xxx_reg_lock(chip);
1262 err = mv88e6xxx_port_set_state(chip, port, state);
1263 mv88e6xxx_reg_unlock(chip);
1264
1265 if (err)
1266 dev_err(ds->dev, "p%d: failed to update state\n", port);
1267 }
1268
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1269 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1270 {
1271 int err;
1272
1273 if (chip->info->ops->ieee_pri_map) {
1274 err = chip->info->ops->ieee_pri_map(chip);
1275 if (err)
1276 return err;
1277 }
1278
1279 if (chip->info->ops->ip_pri_map) {
1280 err = chip->info->ops->ip_pri_map(chip);
1281 if (err)
1282 return err;
1283 }
1284
1285 return 0;
1286 }
1287
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1288 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1289 {
1290 struct dsa_switch *ds = chip->ds;
1291 int target, port;
1292 int err;
1293
1294 if (!chip->info->global2_addr)
1295 return 0;
1296
1297 /* Initialize the routing port to the 32 possible target devices */
1298 for (target = 0; target < 32; target++) {
1299 port = dsa_routing_port(ds, target);
1300 if (port == ds->num_ports)
1301 port = 0x1f;
1302
1303 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1304 if (err)
1305 return err;
1306 }
1307
1308 if (chip->info->ops->set_cascade_port) {
1309 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1310 err = chip->info->ops->set_cascade_port(chip, port);
1311 if (err)
1312 return err;
1313 }
1314
1315 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1316 if (err)
1317 return err;
1318
1319 return 0;
1320 }
1321
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1322 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1323 {
1324 /* Clear all trunk masks and mapping */
1325 if (chip->info->global2_addr)
1326 return mv88e6xxx_g2_trunk_clear(chip);
1327
1328 return 0;
1329 }
1330
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1331 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1332 {
1333 if (chip->info->ops->rmu_disable)
1334 return chip->info->ops->rmu_disable(chip);
1335
1336 return 0;
1337 }
1338
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1339 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1340 {
1341 if (chip->info->ops->pot_clear)
1342 return chip->info->ops->pot_clear(chip);
1343
1344 return 0;
1345 }
1346
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1347 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1348 {
1349 if (chip->info->ops->mgmt_rsvd2cpu)
1350 return chip->info->ops->mgmt_rsvd2cpu(chip);
1351
1352 return 0;
1353 }
1354
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1355 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1356 {
1357 int err;
1358
1359 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1360 if (err)
1361 return err;
1362
1363 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1364 if (err)
1365 return err;
1366
1367 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1368 }
1369
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1370 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1371 {
1372 int port;
1373 int err;
1374
1375 if (!chip->info->ops->irl_init_all)
1376 return 0;
1377
1378 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1379 /* Disable ingress rate limiting by resetting all per port
1380 * ingress rate limit resources to their initial state.
1381 */
1382 err = chip->info->ops->irl_init_all(chip, port);
1383 if (err)
1384 return err;
1385 }
1386
1387 return 0;
1388 }
1389
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1390 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1391 {
1392 if (chip->info->ops->set_switch_mac) {
1393 u8 addr[ETH_ALEN];
1394
1395 eth_random_addr(addr);
1396
1397 return chip->info->ops->set_switch_mac(chip, addr);
1398 }
1399
1400 return 0;
1401 }
1402
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1403 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1404 {
1405 u16 pvlan = 0;
1406
1407 if (!mv88e6xxx_has_pvt(chip))
1408 return 0;
1409
1410 /* Skip the local source device, which uses in-chip port VLAN */
1411 if (dev != chip->ds->index)
1412 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1413
1414 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1415 }
1416
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1417 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1418 {
1419 int dev, port;
1420 int err;
1421
1422 if (!mv88e6xxx_has_pvt(chip))
1423 return 0;
1424
1425 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1426 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1427 */
1428 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1429 if (err)
1430 return err;
1431
1432 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1433 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1434 err = mv88e6xxx_pvt_map(chip, dev, port);
1435 if (err)
1436 return err;
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1443 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1444 {
1445 struct mv88e6xxx_chip *chip = ds->priv;
1446 int err;
1447
1448 mv88e6xxx_reg_lock(chip);
1449 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1450 mv88e6xxx_reg_unlock(chip);
1451
1452 if (err)
1453 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1454 }
1455
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1456 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1457 {
1458 if (!chip->info->max_vid)
1459 return 0;
1460
1461 return mv88e6xxx_g1_vtu_flush(chip);
1462 }
1463
mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1464 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1465 struct mv88e6xxx_vtu_entry *entry)
1466 {
1467 if (!chip->info->ops->vtu_getnext)
1468 return -EOPNOTSUPP;
1469
1470 return chip->info->ops->vtu_getnext(chip, entry);
1471 }
1472
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1473 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1474 struct mv88e6xxx_vtu_entry *entry)
1475 {
1476 if (!chip->info->ops->vtu_loadpurge)
1477 return -EOPNOTSUPP;
1478
1479 return chip->info->ops->vtu_loadpurge(chip, entry);
1480 }
1481
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1482 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1483 {
1484 struct mv88e6xxx_vtu_entry vlan;
1485 int i, err;
1486 u16 fid;
1487
1488 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1489
1490 /* Set every FID bit used by the (un)bridged ports */
1491 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1492 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1493 if (err)
1494 return err;
1495
1496 set_bit(fid, fid_bitmap);
1497 }
1498
1499 /* Set every FID bit used by the VLAN entries */
1500 vlan.vid = chip->info->max_vid;
1501 vlan.valid = false;
1502
1503 do {
1504 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1505 if (err)
1506 return err;
1507
1508 if (!vlan.valid)
1509 break;
1510
1511 set_bit(vlan.fid, fid_bitmap);
1512 } while (vlan.vid < chip->info->max_vid);
1513
1514 return 0;
1515 }
1516
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1517 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1518 {
1519 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1520 int err;
1521
1522 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1523 if (err)
1524 return err;
1525
1526 /* The reset value 0x000 is used to indicate that multiple address
1527 * databases are not needed. Return the next positive available.
1528 */
1529 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1530 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1531 return -ENOSPC;
1532
1533 /* Clear the database */
1534 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1535 }
1536
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid_begin,u16 vid_end)1537 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1538 u16 vid_begin, u16 vid_end)
1539 {
1540 struct mv88e6xxx_chip *chip = ds->priv;
1541 struct mv88e6xxx_vtu_entry vlan;
1542 int i, err;
1543
1544 /* DSA and CPU ports have to be members of multiple vlans */
1545 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1546 return 0;
1547
1548 if (!vid_begin)
1549 return -EOPNOTSUPP;
1550
1551 vlan.vid = vid_begin - 1;
1552 vlan.valid = false;
1553
1554 do {
1555 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1556 if (err)
1557 return err;
1558
1559 if (!vlan.valid)
1560 break;
1561
1562 if (vlan.vid > vid_end)
1563 break;
1564
1565 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1566 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1567 continue;
1568
1569 if (!dsa_to_port(ds, i)->slave)
1570 continue;
1571
1572 if (vlan.member[i] ==
1573 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1574 continue;
1575
1576 if (dsa_to_port(ds, i)->bridge_dev ==
1577 dsa_to_port(ds, port)->bridge_dev)
1578 break; /* same bridge, check next VLAN */
1579
1580 if (!dsa_to_port(ds, i)->bridge_dev)
1581 continue;
1582
1583 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1584 port, vlan.vid, i,
1585 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1586 return -EOPNOTSUPP;
1587 }
1588 } while (vlan.vid < vid_end);
1589
1590 return 0;
1591 }
1592
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct switchdev_trans * trans)1593 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1594 bool vlan_filtering,
1595 struct switchdev_trans *trans)
1596 {
1597 struct mv88e6xxx_chip *chip = ds->priv;
1598 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1599 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1600 int err;
1601
1602 if (switchdev_trans_ph_prepare(trans))
1603 return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1604
1605 mv88e6xxx_reg_lock(chip);
1606 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1607 mv88e6xxx_reg_unlock(chip);
1608
1609 return err;
1610 }
1611
1612 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1613 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1614 const struct switchdev_obj_port_vlan *vlan)
1615 {
1616 struct mv88e6xxx_chip *chip = ds->priv;
1617 int err;
1618
1619 if (!chip->info->max_vid)
1620 return -EOPNOTSUPP;
1621
1622 /* If the requested port doesn't belong to the same bridge as the VLAN
1623 * members, do not support it (yet) and fallback to software VLAN.
1624 */
1625 mv88e6xxx_reg_lock(chip);
1626 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1627 vlan->vid_end);
1628 mv88e6xxx_reg_unlock(chip);
1629
1630 /* We don't need any dynamic resource from the kernel (yet),
1631 * so skip the prepare phase.
1632 */
1633 return err;
1634 }
1635
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)1636 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1637 const unsigned char *addr, u16 vid,
1638 u8 state)
1639 {
1640 struct mv88e6xxx_atu_entry entry;
1641 struct mv88e6xxx_vtu_entry vlan;
1642 u16 fid;
1643 int err;
1644
1645 /* Null VLAN ID corresponds to the port private database */
1646 if (vid == 0) {
1647 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1648 if (err)
1649 return err;
1650 } else {
1651 vlan.vid = vid - 1;
1652 vlan.valid = false;
1653
1654 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1655 if (err)
1656 return err;
1657
1658 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1659 if (vlan.vid != vid || !vlan.valid)
1660 return -EOPNOTSUPP;
1661
1662 fid = vlan.fid;
1663 }
1664
1665 entry.state = 0;
1666 ether_addr_copy(entry.mac, addr);
1667 eth_addr_dec(entry.mac);
1668
1669 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1670 if (err)
1671 return err;
1672
1673 /* Initialize a fresh ATU entry if it isn't found */
1674 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1675 memset(&entry, 0, sizeof(entry));
1676 ether_addr_copy(entry.mac, addr);
1677 }
1678
1679 /* Purge the ATU entry only if no port is using it anymore */
1680 if (!state) {
1681 entry.portvec &= ~BIT(port);
1682 if (!entry.portvec)
1683 entry.state = 0;
1684 } else {
1685 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1686 entry.portvec = BIT(port);
1687 else
1688 entry.portvec |= BIT(port);
1689
1690 entry.state = state;
1691 }
1692
1693 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1694 }
1695
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)1696 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1697 const struct mv88e6xxx_policy *policy)
1698 {
1699 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1700 enum mv88e6xxx_policy_action action = policy->action;
1701 const u8 *addr = policy->addr;
1702 u16 vid = policy->vid;
1703 u8 state;
1704 int err;
1705 int id;
1706
1707 if (!chip->info->ops->port_set_policy)
1708 return -EOPNOTSUPP;
1709
1710 switch (mapping) {
1711 case MV88E6XXX_POLICY_MAPPING_DA:
1712 case MV88E6XXX_POLICY_MAPPING_SA:
1713 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1714 state = 0; /* Dissociate the port and address */
1715 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1716 is_multicast_ether_addr(addr))
1717 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1718 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1719 is_unicast_ether_addr(addr))
1720 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1721 else
1722 return -EOPNOTSUPP;
1723
1724 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1725 state);
1726 if (err)
1727 return err;
1728 break;
1729 default:
1730 return -EOPNOTSUPP;
1731 }
1732
1733 /* Skip the port's policy clearing if the mapping is still in use */
1734 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1735 idr_for_each_entry(&chip->policies, policy, id)
1736 if (policy->port == port &&
1737 policy->mapping == mapping &&
1738 policy->action != action)
1739 return 0;
1740
1741 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1742 }
1743
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)1744 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1745 struct ethtool_rx_flow_spec *fs)
1746 {
1747 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1748 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1749 enum mv88e6xxx_policy_mapping mapping;
1750 enum mv88e6xxx_policy_action action;
1751 struct mv88e6xxx_policy *policy;
1752 u16 vid = 0;
1753 u8 *addr;
1754 int err;
1755 int id;
1756
1757 if (fs->location != RX_CLS_LOC_ANY)
1758 return -EINVAL;
1759
1760 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1761 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1762 else
1763 return -EOPNOTSUPP;
1764
1765 switch (fs->flow_type & ~FLOW_EXT) {
1766 case ETHER_FLOW:
1767 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1768 is_zero_ether_addr(mac_mask->h_source)) {
1769 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1770 addr = mac_entry->h_dest;
1771 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1772 !is_zero_ether_addr(mac_mask->h_source)) {
1773 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1774 addr = mac_entry->h_source;
1775 } else {
1776 /* Cannot support DA and SA mapping in the same rule */
1777 return -EOPNOTSUPP;
1778 }
1779 break;
1780 default:
1781 return -EOPNOTSUPP;
1782 }
1783
1784 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1785 if (fs->m_ext.vlan_tci != htons(0xffff))
1786 return -EOPNOTSUPP;
1787 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1788 }
1789
1790 idr_for_each_entry(&chip->policies, policy, id) {
1791 if (policy->port == port && policy->mapping == mapping &&
1792 policy->action == action && policy->vid == vid &&
1793 ether_addr_equal(policy->addr, addr))
1794 return -EEXIST;
1795 }
1796
1797 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1798 if (!policy)
1799 return -ENOMEM;
1800
1801 fs->location = 0;
1802 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1803 GFP_KERNEL);
1804 if (err) {
1805 devm_kfree(chip->dev, policy);
1806 return err;
1807 }
1808
1809 memcpy(&policy->fs, fs, sizeof(*fs));
1810 ether_addr_copy(policy->addr, addr);
1811 policy->mapping = mapping;
1812 policy->action = action;
1813 policy->port = port;
1814 policy->vid = vid;
1815
1816 err = mv88e6xxx_policy_apply(chip, port, policy);
1817 if (err) {
1818 idr_remove(&chip->policies, fs->location);
1819 devm_kfree(chip->dev, policy);
1820 return err;
1821 }
1822
1823 return 0;
1824 }
1825
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)1826 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1827 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1828 {
1829 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1830 struct mv88e6xxx_chip *chip = ds->priv;
1831 struct mv88e6xxx_policy *policy;
1832 int err;
1833 int id;
1834
1835 mv88e6xxx_reg_lock(chip);
1836
1837 switch (rxnfc->cmd) {
1838 case ETHTOOL_GRXCLSRLCNT:
1839 rxnfc->data = 0;
1840 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1841 rxnfc->rule_cnt = 0;
1842 idr_for_each_entry(&chip->policies, policy, id)
1843 if (policy->port == port)
1844 rxnfc->rule_cnt++;
1845 err = 0;
1846 break;
1847 case ETHTOOL_GRXCLSRULE:
1848 err = -ENOENT;
1849 policy = idr_find(&chip->policies, fs->location);
1850 if (policy) {
1851 memcpy(fs, &policy->fs, sizeof(*fs));
1852 err = 0;
1853 }
1854 break;
1855 case ETHTOOL_GRXCLSRLALL:
1856 rxnfc->data = 0;
1857 rxnfc->rule_cnt = 0;
1858 idr_for_each_entry(&chip->policies, policy, id)
1859 if (policy->port == port)
1860 rule_locs[rxnfc->rule_cnt++] = id;
1861 err = 0;
1862 break;
1863 default:
1864 err = -EOPNOTSUPP;
1865 break;
1866 }
1867
1868 mv88e6xxx_reg_unlock(chip);
1869
1870 return err;
1871 }
1872
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)1873 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1874 struct ethtool_rxnfc *rxnfc)
1875 {
1876 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1877 struct mv88e6xxx_chip *chip = ds->priv;
1878 struct mv88e6xxx_policy *policy;
1879 int err;
1880
1881 mv88e6xxx_reg_lock(chip);
1882
1883 switch (rxnfc->cmd) {
1884 case ETHTOOL_SRXCLSRLINS:
1885 err = mv88e6xxx_policy_insert(chip, port, fs);
1886 break;
1887 case ETHTOOL_SRXCLSRLDEL:
1888 err = -ENOENT;
1889 policy = idr_remove(&chip->policies, fs->location);
1890 if (policy) {
1891 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1892 err = mv88e6xxx_policy_apply(chip, port, policy);
1893 devm_kfree(chip->dev, policy);
1894 }
1895 break;
1896 default:
1897 err = -EOPNOTSUPP;
1898 break;
1899 }
1900
1901 mv88e6xxx_reg_unlock(chip);
1902
1903 return err;
1904 }
1905
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)1906 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1907 u16 vid)
1908 {
1909 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1910 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1911
1912 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1913 }
1914
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)1915 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1916 {
1917 int port;
1918 int err;
1919
1920 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1921 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1922 if (err)
1923 return err;
1924 }
1925
1926 return 0;
1927 }
1928
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)1929 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1930 u16 vid, u8 member, bool warn)
1931 {
1932 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1933 struct mv88e6xxx_vtu_entry vlan;
1934 int i, err;
1935
1936 if (!vid)
1937 return -EOPNOTSUPP;
1938
1939 vlan.vid = vid - 1;
1940 vlan.valid = false;
1941
1942 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1943 if (err)
1944 return err;
1945
1946 if (vlan.vid != vid || !vlan.valid) {
1947 memset(&vlan, 0, sizeof(vlan));
1948
1949 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1950 if (err)
1951 return err;
1952
1953 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1954 if (i == port)
1955 vlan.member[i] = member;
1956 else
1957 vlan.member[i] = non_member;
1958
1959 vlan.vid = vid;
1960 vlan.valid = true;
1961
1962 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1963 if (err)
1964 return err;
1965
1966 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1967 if (err)
1968 return err;
1969 } else if (vlan.member[port] != member) {
1970 vlan.member[port] = member;
1971
1972 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1973 if (err)
1974 return err;
1975 } else if (warn) {
1976 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1977 port, vid);
1978 }
1979
1980 return 0;
1981 }
1982
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1983 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1984 const struct switchdev_obj_port_vlan *vlan)
1985 {
1986 struct mv88e6xxx_chip *chip = ds->priv;
1987 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1988 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1989 bool warn;
1990 u8 member;
1991 u16 vid;
1992
1993 if (!chip->info->max_vid)
1994 return;
1995
1996 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1997 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1998 else if (untagged)
1999 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2000 else
2001 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2002
2003 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2004 * and then the CPU port. Do not warn for duplicates for the CPU port.
2005 */
2006 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2007
2008 mv88e6xxx_reg_lock(chip);
2009
2010 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2011 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
2012 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2013 vid, untagged ? 'u' : 't');
2014
2015 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
2016 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
2017 vlan->vid_end);
2018
2019 mv88e6xxx_reg_unlock(chip);
2020 }
2021
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2022 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2023 int port, u16 vid)
2024 {
2025 struct mv88e6xxx_vtu_entry vlan;
2026 int i, err;
2027
2028 if (!vid)
2029 return -EOPNOTSUPP;
2030
2031 vlan.vid = vid - 1;
2032 vlan.valid = false;
2033
2034 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2035 if (err)
2036 return err;
2037
2038 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2039 * tell switchdev that this VLAN is likely handled in software.
2040 */
2041 if (vlan.vid != vid || !vlan.valid ||
2042 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2043 return -EOPNOTSUPP;
2044
2045 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2046
2047 /* keep the VLAN unless all ports are excluded */
2048 vlan.valid = false;
2049 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2050 if (vlan.member[i] !=
2051 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2052 vlan.valid = true;
2053 break;
2054 }
2055 }
2056
2057 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2058 if (err)
2059 return err;
2060
2061 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2062 }
2063
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2064 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2065 const struct switchdev_obj_port_vlan *vlan)
2066 {
2067 struct mv88e6xxx_chip *chip = ds->priv;
2068 u16 pvid, vid;
2069 int err = 0;
2070
2071 if (!chip->info->max_vid)
2072 return -EOPNOTSUPP;
2073
2074 mv88e6xxx_reg_lock(chip);
2075
2076 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2077 if (err)
2078 goto unlock;
2079
2080 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2081 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2082 if (err)
2083 goto unlock;
2084
2085 if (vid == pvid) {
2086 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2087 if (err)
2088 goto unlock;
2089 }
2090 }
2091
2092 unlock:
2093 mv88e6xxx_reg_unlock(chip);
2094
2095 return err;
2096 }
2097
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2098 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2099 const unsigned char *addr, u16 vid)
2100 {
2101 struct mv88e6xxx_chip *chip = ds->priv;
2102 int err;
2103
2104 mv88e6xxx_reg_lock(chip);
2105 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2106 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2107 mv88e6xxx_reg_unlock(chip);
2108
2109 return err;
2110 }
2111
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2112 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2113 const unsigned char *addr, u16 vid)
2114 {
2115 struct mv88e6xxx_chip *chip = ds->priv;
2116 int err;
2117
2118 mv88e6xxx_reg_lock(chip);
2119 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2120 mv88e6xxx_reg_unlock(chip);
2121
2122 return err;
2123 }
2124
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2125 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2126 u16 fid, u16 vid, int port,
2127 dsa_fdb_dump_cb_t *cb, void *data)
2128 {
2129 struct mv88e6xxx_atu_entry addr;
2130 bool is_static;
2131 int err;
2132
2133 addr.state = 0;
2134 eth_broadcast_addr(addr.mac);
2135
2136 do {
2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2138 if (err)
2139 return err;
2140
2141 if (!addr.state)
2142 break;
2143
2144 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2145 continue;
2146
2147 if (!is_unicast_ether_addr(addr.mac))
2148 continue;
2149
2150 is_static = (addr.state ==
2151 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2152 err = cb(addr.mac, vid, is_static, data);
2153 if (err)
2154 return err;
2155 } while (!is_broadcast_ether_addr(addr.mac));
2156
2157 return err;
2158 }
2159
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2160 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2161 dsa_fdb_dump_cb_t *cb, void *data)
2162 {
2163 struct mv88e6xxx_vtu_entry vlan;
2164 u16 fid;
2165 int err;
2166
2167 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2168 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2169 if (err)
2170 return err;
2171
2172 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2173 if (err)
2174 return err;
2175
2176 /* Dump VLANs' Filtering Information Databases */
2177 vlan.vid = chip->info->max_vid;
2178 vlan.valid = false;
2179
2180 do {
2181 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2182 if (err)
2183 return err;
2184
2185 if (!vlan.valid)
2186 break;
2187
2188 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2189 cb, data);
2190 if (err)
2191 return err;
2192 } while (vlan.vid < chip->info->max_vid);
2193
2194 return err;
2195 }
2196
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2197 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2198 dsa_fdb_dump_cb_t *cb, void *data)
2199 {
2200 struct mv88e6xxx_chip *chip = ds->priv;
2201 int err;
2202
2203 mv88e6xxx_reg_lock(chip);
2204 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2205 mv88e6xxx_reg_unlock(chip);
2206
2207 return err;
2208 }
2209
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct net_device * br)2210 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2211 struct net_device *br)
2212 {
2213 struct dsa_switch *ds = chip->ds;
2214 struct dsa_switch_tree *dst = ds->dst;
2215 struct dsa_port *dp;
2216 int err;
2217
2218 list_for_each_entry(dp, &dst->ports, list) {
2219 if (dp->bridge_dev == br) {
2220 if (dp->ds == ds) {
2221 /* This is a local bridge group member,
2222 * remap its Port VLAN Map.
2223 */
2224 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2225 if (err)
2226 return err;
2227 } else {
2228 /* This is an external bridge group member,
2229 * remap its cross-chip Port VLAN Table entry.
2230 */
2231 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2232 dp->index);
2233 if (err)
2234 return err;
2235 }
2236 }
2237 }
2238
2239 return 0;
2240 }
2241
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * br)2242 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2243 struct net_device *br)
2244 {
2245 struct mv88e6xxx_chip *chip = ds->priv;
2246 int err;
2247
2248 mv88e6xxx_reg_lock(chip);
2249 err = mv88e6xxx_bridge_map(chip, br);
2250 mv88e6xxx_reg_unlock(chip);
2251
2252 return err;
2253 }
2254
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * br)2255 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2256 struct net_device *br)
2257 {
2258 struct mv88e6xxx_chip *chip = ds->priv;
2259
2260 mv88e6xxx_reg_lock(chip);
2261 if (mv88e6xxx_bridge_map(chip, br) ||
2262 mv88e6xxx_port_vlan_map(chip, port))
2263 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2264 mv88e6xxx_reg_unlock(chip);
2265 }
2266
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2267 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2268 int tree_index, int sw_index,
2269 int port, struct net_device *br)
2270 {
2271 struct mv88e6xxx_chip *chip = ds->priv;
2272 int err;
2273
2274 if (tree_index != ds->dst->index)
2275 return 0;
2276
2277 mv88e6xxx_reg_lock(chip);
2278 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2279 mv88e6xxx_reg_unlock(chip);
2280
2281 return err;
2282 }
2283
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2284 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2285 int tree_index, int sw_index,
2286 int port, struct net_device *br)
2287 {
2288 struct mv88e6xxx_chip *chip = ds->priv;
2289
2290 if (tree_index != ds->dst->index)
2291 return;
2292
2293 mv88e6xxx_reg_lock(chip);
2294 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2295 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2296 mv88e6xxx_reg_unlock(chip);
2297 }
2298
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)2299 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2300 {
2301 if (chip->info->ops->reset)
2302 return chip->info->ops->reset(chip);
2303
2304 return 0;
2305 }
2306
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)2307 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2308 {
2309 struct gpio_desc *gpiod = chip->reset;
2310
2311 /* If there is a GPIO connected to the reset pin, toggle it */
2312 if (gpiod) {
2313 gpiod_set_value_cansleep(gpiod, 1);
2314 usleep_range(10000, 20000);
2315 gpiod_set_value_cansleep(gpiod, 0);
2316 usleep_range(10000, 20000);
2317
2318 mv88e6xxx_g1_wait_eeprom_done(chip);
2319 }
2320 }
2321
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)2322 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2323 {
2324 int i, err;
2325
2326 /* Set all ports to the Disabled state */
2327 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2328 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2329 if (err)
2330 return err;
2331 }
2332
2333 /* Wait for transmit queues to drain,
2334 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2335 */
2336 usleep_range(2000, 4000);
2337
2338 return 0;
2339 }
2340
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)2341 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2342 {
2343 int err;
2344
2345 err = mv88e6xxx_disable_ports(chip);
2346 if (err)
2347 return err;
2348
2349 mv88e6xxx_hardware_reset(chip);
2350
2351 return mv88e6xxx_software_reset(chip);
2352 }
2353
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)2354 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2355 enum mv88e6xxx_frame_mode frame,
2356 enum mv88e6xxx_egress_mode egress, u16 etype)
2357 {
2358 int err;
2359
2360 if (!chip->info->ops->port_set_frame_mode)
2361 return -EOPNOTSUPP;
2362
2363 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2364 if (err)
2365 return err;
2366
2367 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2368 if (err)
2369 return err;
2370
2371 if (chip->info->ops->port_set_ether_type)
2372 return chip->info->ops->port_set_ether_type(chip, port, etype);
2373
2374 return 0;
2375 }
2376
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)2377 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2378 {
2379 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2380 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2381 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2382 }
2383
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)2384 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2385 {
2386 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2387 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2388 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2389 }
2390
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)2391 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2392 {
2393 return mv88e6xxx_set_port_mode(chip, port,
2394 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2395 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2396 ETH_P_EDSA);
2397 }
2398
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)2399 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2400 {
2401 if (dsa_is_dsa_port(chip->ds, port))
2402 return mv88e6xxx_set_port_mode_dsa(chip, port);
2403
2404 if (dsa_is_user_port(chip->ds, port))
2405 return mv88e6xxx_set_port_mode_normal(chip, port);
2406
2407 /* Setup CPU port mode depending on its supported tag format */
2408 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2409 return mv88e6xxx_set_port_mode_dsa(chip, port);
2410
2411 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2412 return mv88e6xxx_set_port_mode_edsa(chip, port);
2413
2414 return -EINVAL;
2415 }
2416
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)2417 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2418 {
2419 bool message = dsa_is_dsa_port(chip->ds, port);
2420
2421 return mv88e6xxx_port_set_message_port(chip, port, message);
2422 }
2423
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)2424 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2425 {
2426 struct dsa_switch *ds = chip->ds;
2427 bool flood;
2428
2429 /* Upstream ports flood frames with unknown unicast or multicast DA */
2430 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2431 if (chip->info->ops->port_set_egress_floods)
2432 return chip->info->ops->port_set_egress_floods(chip, port,
2433 flood, flood);
2434
2435 return 0;
2436 }
2437
mv88e6xxx_serdes_irq_thread_fn(int irq,void * dev_id)2438 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2439 {
2440 struct mv88e6xxx_port *mvp = dev_id;
2441 struct mv88e6xxx_chip *chip = mvp->chip;
2442 irqreturn_t ret = IRQ_NONE;
2443 int port = mvp->port;
2444 u8 lane;
2445
2446 mv88e6xxx_reg_lock(chip);
2447 lane = mv88e6xxx_serdes_get_lane(chip, port);
2448 if (lane)
2449 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2450 mv88e6xxx_reg_unlock(chip);
2451
2452 return ret;
2453 }
2454
mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip * chip,int port,u8 lane)2455 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2456 u8 lane)
2457 {
2458 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2459 unsigned int irq;
2460 int err;
2461
2462 /* Nothing to request if this SERDES port has no IRQ */
2463 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2464 if (!irq)
2465 return 0;
2466
2467 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2468 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2469
2470 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2471 mv88e6xxx_reg_unlock(chip);
2472 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2473 IRQF_ONESHOT, dev_id->serdes_irq_name,
2474 dev_id);
2475 mv88e6xxx_reg_lock(chip);
2476 if (err)
2477 return err;
2478
2479 dev_id->serdes_irq = irq;
2480
2481 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2482 }
2483
mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip * chip,int port,u8 lane)2484 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2485 u8 lane)
2486 {
2487 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2488 unsigned int irq = dev_id->serdes_irq;
2489 int err;
2490
2491 /* Nothing to free if no IRQ has been requested */
2492 if (!irq)
2493 return 0;
2494
2495 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2496
2497 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2498 mv88e6xxx_reg_unlock(chip);
2499 free_irq(irq, dev_id);
2500 mv88e6xxx_reg_lock(chip);
2501
2502 dev_id->serdes_irq = 0;
2503
2504 return err;
2505 }
2506
mv88e6xxx_serdes_power(struct mv88e6xxx_chip * chip,int port,bool on)2507 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2508 bool on)
2509 {
2510 u8 lane;
2511 int err;
2512
2513 lane = mv88e6xxx_serdes_get_lane(chip, port);
2514 if (!lane)
2515 return 0;
2516
2517 if (on) {
2518 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2519 if (err)
2520 return err;
2521
2522 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2523 } else {
2524 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2525 if (err)
2526 return err;
2527
2528 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2529 }
2530
2531 return err;
2532 }
2533
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)2534 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2535 {
2536 struct dsa_switch *ds = chip->ds;
2537 int upstream_port;
2538 int err;
2539
2540 upstream_port = dsa_upstream_port(ds, port);
2541 if (chip->info->ops->port_set_upstream_port) {
2542 err = chip->info->ops->port_set_upstream_port(chip, port,
2543 upstream_port);
2544 if (err)
2545 return err;
2546 }
2547
2548 if (port == upstream_port) {
2549 if (chip->info->ops->set_cpu_port) {
2550 err = chip->info->ops->set_cpu_port(chip,
2551 upstream_port);
2552 if (err)
2553 return err;
2554 }
2555
2556 if (chip->info->ops->set_egress_port) {
2557 err = chip->info->ops->set_egress_port(chip,
2558 MV88E6XXX_EGRESS_DIR_INGRESS,
2559 upstream_port);
2560 if (err)
2561 return err;
2562
2563 err = chip->info->ops->set_egress_port(chip,
2564 MV88E6XXX_EGRESS_DIR_EGRESS,
2565 upstream_port);
2566 if (err)
2567 return err;
2568 }
2569 }
2570
2571 return 0;
2572 }
2573
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)2574 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2575 {
2576 struct dsa_switch *ds = chip->ds;
2577 int err;
2578 u16 reg;
2579
2580 chip->ports[port].chip = chip;
2581 chip->ports[port].port = port;
2582
2583 /* MAC Forcing register: don't force link, speed, duplex or flow control
2584 * state to any particular values on physical ports, but force the CPU
2585 * port and all DSA ports to their maximum bandwidth and full duplex.
2586 */
2587 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2588 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2589 SPEED_MAX, DUPLEX_FULL,
2590 PAUSE_OFF,
2591 PHY_INTERFACE_MODE_NA);
2592 else
2593 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2594 SPEED_UNFORCED, DUPLEX_UNFORCED,
2595 PAUSE_ON,
2596 PHY_INTERFACE_MODE_NA);
2597 if (err)
2598 return err;
2599
2600 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2601 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2602 * tunneling, determine priority by looking at 802.1p and IP
2603 * priority fields (IP prio has precedence), and set STP state
2604 * to Forwarding.
2605 *
2606 * If this is the CPU link, use DSA or EDSA tagging depending
2607 * on which tagging mode was configured.
2608 *
2609 * If this is a link to another switch, use DSA tagging mode.
2610 *
2611 * If this is the upstream port for this switch, enable
2612 * forwarding of unknown unicasts and multicasts.
2613 */
2614 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2615 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2616 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2617 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2618 if (err)
2619 return err;
2620
2621 err = mv88e6xxx_setup_port_mode(chip, port);
2622 if (err)
2623 return err;
2624
2625 err = mv88e6xxx_setup_egress_floods(chip, port);
2626 if (err)
2627 return err;
2628
2629 /* Port Control 2: don't force a good FCS, set the MTU size to
2630 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2631 * untagged frames on this port, do a destination address lookup on all
2632 * received packets as usual, disable ARP mirroring and don't send a
2633 * copy of all transmitted/received frames on this port to the CPU.
2634 */
2635 err = mv88e6xxx_port_set_map_da(chip, port);
2636 if (err)
2637 return err;
2638
2639 err = mv88e6xxx_setup_upstream_port(chip, port);
2640 if (err)
2641 return err;
2642
2643 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2644 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2645 if (err)
2646 return err;
2647
2648 if (chip->info->ops->port_set_jumbo_size) {
2649 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2650 if (err)
2651 return err;
2652 }
2653
2654 /* Port Association Vector: when learning source addresses
2655 * of packets, add the address to the address database using
2656 * a port bitmap that has only the bit for this port set and
2657 * the other bits clear.
2658 */
2659 reg = 1 << port;
2660 /* Disable learning for CPU port */
2661 if (dsa_is_cpu_port(ds, port))
2662 reg = 0;
2663
2664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2665 reg);
2666 if (err)
2667 return err;
2668
2669 /* Egress rate control 2: disable egress rate control. */
2670 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2671 0x0000);
2672 if (err)
2673 return err;
2674
2675 if (chip->info->ops->port_pause_limit) {
2676 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2677 if (err)
2678 return err;
2679 }
2680
2681 if (chip->info->ops->port_disable_learn_limit) {
2682 err = chip->info->ops->port_disable_learn_limit(chip, port);
2683 if (err)
2684 return err;
2685 }
2686
2687 if (chip->info->ops->port_disable_pri_override) {
2688 err = chip->info->ops->port_disable_pri_override(chip, port);
2689 if (err)
2690 return err;
2691 }
2692
2693 if (chip->info->ops->port_tag_remap) {
2694 err = chip->info->ops->port_tag_remap(chip, port);
2695 if (err)
2696 return err;
2697 }
2698
2699 if (chip->info->ops->port_egress_rate_limiting) {
2700 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2701 if (err)
2702 return err;
2703 }
2704
2705 if (chip->info->ops->port_setup_message_port) {
2706 err = chip->info->ops->port_setup_message_port(chip, port);
2707 if (err)
2708 return err;
2709 }
2710
2711 /* Port based VLAN map: give each port the same default address
2712 * database, and allow bidirectional communication between the
2713 * CPU and DSA port(s), and the other ports.
2714 */
2715 err = mv88e6xxx_port_set_fid(chip, port, 0);
2716 if (err)
2717 return err;
2718
2719 err = mv88e6xxx_port_vlan_map(chip, port);
2720 if (err)
2721 return err;
2722
2723 /* Default VLAN ID and priority: don't set a default VLAN
2724 * ID, and set the default packet priority to zero.
2725 */
2726 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2727 }
2728
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)2729 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2730 {
2731 struct mv88e6xxx_chip *chip = ds->priv;
2732
2733 if (chip->info->ops->port_set_jumbo_size)
2734 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2735 else if (chip->info->ops->set_max_frame_size)
2736 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2737 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2738 }
2739
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)2740 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2741 {
2742 struct mv88e6xxx_chip *chip = ds->priv;
2743 int ret = 0;
2744
2745 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2746 new_mtu += EDSA_HLEN;
2747
2748 mv88e6xxx_reg_lock(chip);
2749 if (chip->info->ops->port_set_jumbo_size)
2750 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2751 else if (chip->info->ops->set_max_frame_size)
2752 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2753 else
2754 if (new_mtu > 1522)
2755 ret = -EINVAL;
2756 mv88e6xxx_reg_unlock(chip);
2757
2758 return ret;
2759 }
2760
mv88e6xxx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)2761 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2762 struct phy_device *phydev)
2763 {
2764 struct mv88e6xxx_chip *chip = ds->priv;
2765 int err;
2766
2767 mv88e6xxx_reg_lock(chip);
2768 err = mv88e6xxx_serdes_power(chip, port, true);
2769 mv88e6xxx_reg_unlock(chip);
2770
2771 return err;
2772 }
2773
mv88e6xxx_port_disable(struct dsa_switch * ds,int port)2774 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2775 {
2776 struct mv88e6xxx_chip *chip = ds->priv;
2777
2778 mv88e6xxx_reg_lock(chip);
2779 if (mv88e6xxx_serdes_power(chip, port, false))
2780 dev_err(chip->dev, "failed to power off SERDES\n");
2781 mv88e6xxx_reg_unlock(chip);
2782 }
2783
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)2784 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2785 unsigned int ageing_time)
2786 {
2787 struct mv88e6xxx_chip *chip = ds->priv;
2788 int err;
2789
2790 mv88e6xxx_reg_lock(chip);
2791 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2792 mv88e6xxx_reg_unlock(chip);
2793
2794 return err;
2795 }
2796
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)2797 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2798 {
2799 int err;
2800
2801 /* Initialize the statistics unit */
2802 if (chip->info->ops->stats_set_histogram) {
2803 err = chip->info->ops->stats_set_histogram(chip);
2804 if (err)
2805 return err;
2806 }
2807
2808 return mv88e6xxx_g1_stats_clear(chip);
2809 }
2810
2811 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)2812 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2813 {
2814 int port;
2815 int err;
2816 u16 val;
2817
2818 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2819 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2820 if (err) {
2821 dev_err(chip->dev,
2822 "Error reading hidden register: %d\n", err);
2823 return false;
2824 }
2825 if (val != 0x01c0)
2826 return false;
2827 }
2828
2829 return true;
2830 }
2831
2832 /* The 6390 copper ports have an errata which require poking magic
2833 * values into undocumented hidden registers and then performing a
2834 * software reset.
2835 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)2836 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2837 {
2838 int port;
2839 int err;
2840
2841 if (mv88e6390_setup_errata_applied(chip))
2842 return 0;
2843
2844 /* Set the ports into blocking mode */
2845 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2846 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2847 if (err)
2848 return err;
2849 }
2850
2851 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2852 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2853 if (err)
2854 return err;
2855 }
2856
2857 return mv88e6xxx_software_reset(chip);
2858 }
2859
mv88e6xxx_teardown(struct dsa_switch * ds)2860 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2861 {
2862 mv88e6xxx_teardown_devlink_params(ds);
2863 dsa_devlink_resources_unregister(ds);
2864 mv88e6xxx_teardown_devlink_regions(ds);
2865 }
2866
mv88e6xxx_setup(struct dsa_switch * ds)2867 static int mv88e6xxx_setup(struct dsa_switch *ds)
2868 {
2869 struct mv88e6xxx_chip *chip = ds->priv;
2870 u8 cmode;
2871 int err;
2872 int i;
2873
2874 chip->ds = ds;
2875 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2876
2877 mv88e6xxx_reg_lock(chip);
2878
2879 if (chip->info->ops->setup_errata) {
2880 err = chip->info->ops->setup_errata(chip);
2881 if (err)
2882 goto unlock;
2883 }
2884
2885 /* Cache the cmode of each port. */
2886 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2887 if (chip->info->ops->port_get_cmode) {
2888 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2889 if (err)
2890 goto unlock;
2891
2892 chip->ports[i].cmode = cmode;
2893 }
2894 }
2895
2896 /* Setup Switch Port Registers */
2897 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2898 if (dsa_is_unused_port(ds, i))
2899 continue;
2900
2901 /* Prevent the use of an invalid port. */
2902 if (mv88e6xxx_is_invalid_port(chip, i)) {
2903 dev_err(chip->dev, "port %d is invalid\n", i);
2904 err = -EINVAL;
2905 goto unlock;
2906 }
2907
2908 err = mv88e6xxx_setup_port(chip, i);
2909 if (err)
2910 goto unlock;
2911 }
2912
2913 err = mv88e6xxx_irl_setup(chip);
2914 if (err)
2915 goto unlock;
2916
2917 err = mv88e6xxx_mac_setup(chip);
2918 if (err)
2919 goto unlock;
2920
2921 err = mv88e6xxx_phy_setup(chip);
2922 if (err)
2923 goto unlock;
2924
2925 err = mv88e6xxx_vtu_setup(chip);
2926 if (err)
2927 goto unlock;
2928
2929 err = mv88e6xxx_pvt_setup(chip);
2930 if (err)
2931 goto unlock;
2932
2933 err = mv88e6xxx_atu_setup(chip);
2934 if (err)
2935 goto unlock;
2936
2937 err = mv88e6xxx_broadcast_setup(chip, 0);
2938 if (err)
2939 goto unlock;
2940
2941 err = mv88e6xxx_pot_setup(chip);
2942 if (err)
2943 goto unlock;
2944
2945 err = mv88e6xxx_rmu_setup(chip);
2946 if (err)
2947 goto unlock;
2948
2949 err = mv88e6xxx_rsvd2cpu_setup(chip);
2950 if (err)
2951 goto unlock;
2952
2953 err = mv88e6xxx_trunk_setup(chip);
2954 if (err)
2955 goto unlock;
2956
2957 err = mv88e6xxx_devmap_setup(chip);
2958 if (err)
2959 goto unlock;
2960
2961 err = mv88e6xxx_pri_setup(chip);
2962 if (err)
2963 goto unlock;
2964
2965 /* Setup PTP Hardware Clock and timestamping */
2966 if (chip->info->ptp_support) {
2967 err = mv88e6xxx_ptp_setup(chip);
2968 if (err)
2969 goto unlock;
2970
2971 err = mv88e6xxx_hwtstamp_setup(chip);
2972 if (err)
2973 goto unlock;
2974 }
2975
2976 err = mv88e6xxx_stats_setup(chip);
2977 if (err)
2978 goto unlock;
2979
2980 unlock:
2981 mv88e6xxx_reg_unlock(chip);
2982
2983 if (err)
2984 return err;
2985
2986 /* Have to be called without holding the register lock, since
2987 * they take the devlink lock, and we later take the locks in
2988 * the reverse order when getting/setting parameters or
2989 * resource occupancy.
2990 */
2991 err = mv88e6xxx_setup_devlink_resources(ds);
2992 if (err)
2993 return err;
2994
2995 err = mv88e6xxx_setup_devlink_params(ds);
2996 if (err)
2997 goto out_resources;
2998
2999 err = mv88e6xxx_setup_devlink_regions(ds);
3000 if (err)
3001 goto out_params;
3002
3003 return 0;
3004
3005 out_params:
3006 mv88e6xxx_teardown_devlink_params(ds);
3007 out_resources:
3008 dsa_devlink_resources_unregister(ds);
3009
3010 return err;
3011 }
3012
3013 /* prod_id for switch families which do not have a PHY model number */
3014 static const u16 family_prod_id_table[] = {
3015 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3016 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3017 };
3018
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3019 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3020 {
3021 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3022 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3023 u16 prod_id;
3024 u16 val;
3025 int err;
3026
3027 if (!chip->info->ops->phy_read)
3028 return -EOPNOTSUPP;
3029
3030 mv88e6xxx_reg_lock(chip);
3031 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3032 mv88e6xxx_reg_unlock(chip);
3033
3034 /* Some internal PHYs don't have a model number. */
3035 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3036 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3037 prod_id = family_prod_id_table[chip->info->family];
3038 if (prod_id)
3039 val |= prod_id >> 4;
3040 }
3041
3042 return err ? err : val;
3043 }
3044
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3045 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3046 {
3047 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3048 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3049 int err;
3050
3051 if (!chip->info->ops->phy_write)
3052 return -EOPNOTSUPP;
3053
3054 mv88e6xxx_reg_lock(chip);
3055 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3056 mv88e6xxx_reg_unlock(chip);
3057
3058 return err;
3059 }
3060
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3061 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3062 struct device_node *np,
3063 bool external)
3064 {
3065 static int index;
3066 struct mv88e6xxx_mdio_bus *mdio_bus;
3067 struct mii_bus *bus;
3068 int err;
3069
3070 if (external) {
3071 mv88e6xxx_reg_lock(chip);
3072 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3073 mv88e6xxx_reg_unlock(chip);
3074
3075 if (err)
3076 return err;
3077 }
3078
3079 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3080 if (!bus)
3081 return -ENOMEM;
3082
3083 mdio_bus = bus->priv;
3084 mdio_bus->bus = bus;
3085 mdio_bus->chip = chip;
3086 INIT_LIST_HEAD(&mdio_bus->list);
3087 mdio_bus->external = external;
3088
3089 if (np) {
3090 bus->name = np->full_name;
3091 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3092 } else {
3093 bus->name = "mv88e6xxx SMI";
3094 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3095 }
3096
3097 bus->read = mv88e6xxx_mdio_read;
3098 bus->write = mv88e6xxx_mdio_write;
3099 bus->parent = chip->dev;
3100
3101 if (!external) {
3102 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3103 if (err)
3104 goto out;
3105 }
3106
3107 err = of_mdiobus_register(bus, np);
3108 if (err) {
3109 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3110 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3111 goto out;
3112 }
3113
3114 if (external)
3115 list_add_tail(&mdio_bus->list, &chip->mdios);
3116 else
3117 list_add(&mdio_bus->list, &chip->mdios);
3118
3119 return 0;
3120
3121 out:
3122 mdiobus_free(bus);
3123 return err;
3124 }
3125
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3126 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3127
3128 {
3129 struct mv88e6xxx_mdio_bus *mdio_bus;
3130 struct mii_bus *bus;
3131
3132 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3133 bus = mdio_bus->bus;
3134
3135 if (!mdio_bus->external)
3136 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3137
3138 mdiobus_unregister(bus);
3139 mdiobus_free(bus);
3140 }
3141 }
3142
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip,struct device_node * np)3143 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3144 struct device_node *np)
3145 {
3146 struct device_node *child;
3147 int err;
3148
3149 /* Always register one mdio bus for the internal/default mdio
3150 * bus. This maybe represented in the device tree, but is
3151 * optional.
3152 */
3153 child = of_get_child_by_name(np, "mdio");
3154 err = mv88e6xxx_mdio_register(chip, child, false);
3155 of_node_put(child);
3156 if (err)
3157 return err;
3158
3159 /* Walk the device tree, and see if there are any other nodes
3160 * which say they are compatible with the external mdio
3161 * bus.
3162 */
3163 for_each_available_child_of_node(np, child) {
3164 if (of_device_is_compatible(
3165 child, "marvell,mv88e6xxx-mdio-external")) {
3166 err = mv88e6xxx_mdio_register(chip, child, true);
3167 if (err) {
3168 mv88e6xxx_mdios_unregister(chip);
3169 of_node_put(child);
3170 return err;
3171 }
3172 }
3173 }
3174
3175 return 0;
3176 }
3177
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3178 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3179 {
3180 struct mv88e6xxx_chip *chip = ds->priv;
3181
3182 return chip->eeprom_len;
3183 }
3184
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3185 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3186 struct ethtool_eeprom *eeprom, u8 *data)
3187 {
3188 struct mv88e6xxx_chip *chip = ds->priv;
3189 int err;
3190
3191 if (!chip->info->ops->get_eeprom)
3192 return -EOPNOTSUPP;
3193
3194 mv88e6xxx_reg_lock(chip);
3195 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3196 mv88e6xxx_reg_unlock(chip);
3197
3198 if (err)
3199 return err;
3200
3201 eeprom->magic = 0xc3ec4951;
3202
3203 return 0;
3204 }
3205
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3206 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3207 struct ethtool_eeprom *eeprom, u8 *data)
3208 {
3209 struct mv88e6xxx_chip *chip = ds->priv;
3210 int err;
3211
3212 if (!chip->info->ops->set_eeprom)
3213 return -EOPNOTSUPP;
3214
3215 if (eeprom->magic != 0xc3ec4951)
3216 return -EINVAL;
3217
3218 mv88e6xxx_reg_lock(chip);
3219 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3220 mv88e6xxx_reg_unlock(chip);
3221
3222 return err;
3223 }
3224
3225 static const struct mv88e6xxx_ops mv88e6085_ops = {
3226 /* MV88E6XXX_FAMILY_6097 */
3227 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3228 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3229 .irl_init_all = mv88e6352_g2_irl_init_all,
3230 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3231 .phy_read = mv88e6185_phy_ppu_read,
3232 .phy_write = mv88e6185_phy_ppu_write,
3233 .port_set_link = mv88e6xxx_port_set_link,
3234 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3235 .port_tag_remap = mv88e6095_port_tag_remap,
3236 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3237 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3238 .port_set_ether_type = mv88e6351_port_set_ether_type,
3239 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3240 .port_pause_limit = mv88e6097_port_pause_limit,
3241 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3242 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3243 .port_get_cmode = mv88e6185_port_get_cmode,
3244 .port_setup_message_port = mv88e6xxx_setup_message_port,
3245 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3246 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3247 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3248 .stats_get_strings = mv88e6095_stats_get_strings,
3249 .stats_get_stats = mv88e6095_stats_get_stats,
3250 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3251 .set_egress_port = mv88e6095_g1_set_egress_port,
3252 .watchdog_ops = &mv88e6097_watchdog_ops,
3253 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3254 .pot_clear = mv88e6xxx_g2_pot_clear,
3255 .ppu_enable = mv88e6185_g1_ppu_enable,
3256 .ppu_disable = mv88e6185_g1_ppu_disable,
3257 .reset = mv88e6185_g1_reset,
3258 .rmu_disable = mv88e6085_g1_rmu_disable,
3259 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3260 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3261 .phylink_validate = mv88e6185_phylink_validate,
3262 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3263 };
3264
3265 static const struct mv88e6xxx_ops mv88e6095_ops = {
3266 /* MV88E6XXX_FAMILY_6095 */
3267 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3268 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3269 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3270 .phy_read = mv88e6185_phy_ppu_read,
3271 .phy_write = mv88e6185_phy_ppu_write,
3272 .port_set_link = mv88e6xxx_port_set_link,
3273 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3274 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3275 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3276 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3277 .port_get_cmode = mv88e6185_port_get_cmode,
3278 .port_setup_message_port = mv88e6xxx_setup_message_port,
3279 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3280 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3281 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3282 .stats_get_strings = mv88e6095_stats_get_strings,
3283 .stats_get_stats = mv88e6095_stats_get_stats,
3284 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3285 .ppu_enable = mv88e6185_g1_ppu_enable,
3286 .ppu_disable = mv88e6185_g1_ppu_disable,
3287 .reset = mv88e6185_g1_reset,
3288 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3289 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3290 .phylink_validate = mv88e6185_phylink_validate,
3291 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3292 };
3293
3294 static const struct mv88e6xxx_ops mv88e6097_ops = {
3295 /* MV88E6XXX_FAMILY_6097 */
3296 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3297 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3298 .irl_init_all = mv88e6352_g2_irl_init_all,
3299 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3300 .phy_read = mv88e6xxx_g2_smi_phy_read,
3301 .phy_write = mv88e6xxx_g2_smi_phy_write,
3302 .port_set_link = mv88e6xxx_port_set_link,
3303 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3304 .port_tag_remap = mv88e6095_port_tag_remap,
3305 .port_set_policy = mv88e6352_port_set_policy,
3306 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3307 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3308 .port_set_ether_type = mv88e6351_port_set_ether_type,
3309 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3310 .port_pause_limit = mv88e6097_port_pause_limit,
3311 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3312 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3313 .port_get_cmode = mv88e6185_port_get_cmode,
3314 .port_setup_message_port = mv88e6xxx_setup_message_port,
3315 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3316 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3317 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3318 .stats_get_strings = mv88e6095_stats_get_strings,
3319 .stats_get_stats = mv88e6095_stats_get_stats,
3320 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3321 .set_egress_port = mv88e6095_g1_set_egress_port,
3322 .watchdog_ops = &mv88e6097_watchdog_ops,
3323 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3324 .pot_clear = mv88e6xxx_g2_pot_clear,
3325 .reset = mv88e6352_g1_reset,
3326 .rmu_disable = mv88e6085_g1_rmu_disable,
3327 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3329 .phylink_validate = mv88e6185_phylink_validate,
3330 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3331 };
3332
3333 static const struct mv88e6xxx_ops mv88e6123_ops = {
3334 /* MV88E6XXX_FAMILY_6165 */
3335 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3336 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3337 .irl_init_all = mv88e6352_g2_irl_init_all,
3338 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3339 .phy_read = mv88e6xxx_g2_smi_phy_read,
3340 .phy_write = mv88e6xxx_g2_smi_phy_write,
3341 .port_set_link = mv88e6xxx_port_set_link,
3342 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3343 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3344 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3347 .port_get_cmode = mv88e6185_port_get_cmode,
3348 .port_setup_message_port = mv88e6xxx_setup_message_port,
3349 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3350 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3351 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3352 .stats_get_strings = mv88e6095_stats_get_strings,
3353 .stats_get_stats = mv88e6095_stats_get_stats,
3354 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3355 .set_egress_port = mv88e6095_g1_set_egress_port,
3356 .watchdog_ops = &mv88e6097_watchdog_ops,
3357 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3358 .pot_clear = mv88e6xxx_g2_pot_clear,
3359 .reset = mv88e6352_g1_reset,
3360 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3361 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3362 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3363 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3364 .phylink_validate = mv88e6185_phylink_validate,
3365 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3366 };
3367
3368 static const struct mv88e6xxx_ops mv88e6131_ops = {
3369 /* MV88E6XXX_FAMILY_6185 */
3370 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3371 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3372 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3373 .phy_read = mv88e6185_phy_ppu_read,
3374 .phy_write = mv88e6185_phy_ppu_write,
3375 .port_set_link = mv88e6xxx_port_set_link,
3376 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3377 .port_tag_remap = mv88e6095_port_tag_remap,
3378 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3379 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3380 .port_set_ether_type = mv88e6351_port_set_ether_type,
3381 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3382 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3383 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3384 .port_pause_limit = mv88e6097_port_pause_limit,
3385 .port_set_pause = mv88e6185_port_set_pause,
3386 .port_get_cmode = mv88e6185_port_get_cmode,
3387 .port_setup_message_port = mv88e6xxx_setup_message_port,
3388 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3389 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3390 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3391 .stats_get_strings = mv88e6095_stats_get_strings,
3392 .stats_get_stats = mv88e6095_stats_get_stats,
3393 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3394 .set_egress_port = mv88e6095_g1_set_egress_port,
3395 .watchdog_ops = &mv88e6097_watchdog_ops,
3396 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3397 .ppu_enable = mv88e6185_g1_ppu_enable,
3398 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3399 .ppu_disable = mv88e6185_g1_ppu_disable,
3400 .reset = mv88e6185_g1_reset,
3401 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3402 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3403 .phylink_validate = mv88e6185_phylink_validate,
3404 };
3405
3406 static const struct mv88e6xxx_ops mv88e6141_ops = {
3407 /* MV88E6XXX_FAMILY_6341 */
3408 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3409 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3410 .irl_init_all = mv88e6352_g2_irl_init_all,
3411 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3412 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3414 .phy_read = mv88e6xxx_g2_smi_phy_read,
3415 .phy_write = mv88e6xxx_g2_smi_phy_write,
3416 .port_set_link = mv88e6xxx_port_set_link,
3417 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3418 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3419 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3420 .port_tag_remap = mv88e6095_port_tag_remap,
3421 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3422 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3423 .port_set_ether_type = mv88e6351_port_set_ether_type,
3424 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3425 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3426 .port_pause_limit = mv88e6097_port_pause_limit,
3427 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3428 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3429 .port_get_cmode = mv88e6352_port_get_cmode,
3430 .port_set_cmode = mv88e6341_port_set_cmode,
3431 .port_setup_message_port = mv88e6xxx_setup_message_port,
3432 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3433 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3434 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3435 .stats_get_strings = mv88e6320_stats_get_strings,
3436 .stats_get_stats = mv88e6390_stats_get_stats,
3437 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3438 .set_egress_port = mv88e6390_g1_set_egress_port,
3439 .watchdog_ops = &mv88e6390_watchdog_ops,
3440 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3441 .pot_clear = mv88e6xxx_g2_pot_clear,
3442 .reset = mv88e6352_g1_reset,
3443 .rmu_disable = mv88e6390_g1_rmu_disable,
3444 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3445 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3446 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3448 .serdes_power = mv88e6390_serdes_power,
3449 .serdes_get_lane = mv88e6341_serdes_get_lane,
3450 /* Check status register pause & lpa register */
3451 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3452 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3453 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3454 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3455 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3456 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3457 .serdes_irq_status = mv88e6390_serdes_irq_status,
3458 .gpio_ops = &mv88e6352_gpio_ops,
3459 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3460 .serdes_get_strings = mv88e6390_serdes_get_strings,
3461 .serdes_get_stats = mv88e6390_serdes_get_stats,
3462 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3463 .serdes_get_regs = mv88e6390_serdes_get_regs,
3464 .phylink_validate = mv88e6341_phylink_validate,
3465 };
3466
3467 static const struct mv88e6xxx_ops mv88e6161_ops = {
3468 /* MV88E6XXX_FAMILY_6165 */
3469 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3470 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3471 .irl_init_all = mv88e6352_g2_irl_init_all,
3472 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3473 .phy_read = mv88e6xxx_g2_smi_phy_read,
3474 .phy_write = mv88e6xxx_g2_smi_phy_write,
3475 .port_set_link = mv88e6xxx_port_set_link,
3476 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3477 .port_tag_remap = mv88e6095_port_tag_remap,
3478 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3479 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3480 .port_set_ether_type = mv88e6351_port_set_ether_type,
3481 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3482 .port_pause_limit = mv88e6097_port_pause_limit,
3483 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3484 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3485 .port_get_cmode = mv88e6185_port_get_cmode,
3486 .port_setup_message_port = mv88e6xxx_setup_message_port,
3487 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3488 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3489 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3490 .stats_get_strings = mv88e6095_stats_get_strings,
3491 .stats_get_stats = mv88e6095_stats_get_stats,
3492 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3493 .set_egress_port = mv88e6095_g1_set_egress_port,
3494 .watchdog_ops = &mv88e6097_watchdog_ops,
3495 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3496 .pot_clear = mv88e6xxx_g2_pot_clear,
3497 .reset = mv88e6352_g1_reset,
3498 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3499 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3500 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3501 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3502 .avb_ops = &mv88e6165_avb_ops,
3503 .ptp_ops = &mv88e6165_ptp_ops,
3504 .phylink_validate = mv88e6185_phylink_validate,
3505 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3506 };
3507
3508 static const struct mv88e6xxx_ops mv88e6165_ops = {
3509 /* MV88E6XXX_FAMILY_6165 */
3510 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3511 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3512 .irl_init_all = mv88e6352_g2_irl_init_all,
3513 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3514 .phy_read = mv88e6165_phy_read,
3515 .phy_write = mv88e6165_phy_write,
3516 .port_set_link = mv88e6xxx_port_set_link,
3517 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3518 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3519 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3520 .port_get_cmode = mv88e6185_port_get_cmode,
3521 .port_setup_message_port = mv88e6xxx_setup_message_port,
3522 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3523 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3524 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3525 .stats_get_strings = mv88e6095_stats_get_strings,
3526 .stats_get_stats = mv88e6095_stats_get_stats,
3527 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3528 .set_egress_port = mv88e6095_g1_set_egress_port,
3529 .watchdog_ops = &mv88e6097_watchdog_ops,
3530 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3531 .pot_clear = mv88e6xxx_g2_pot_clear,
3532 .reset = mv88e6352_g1_reset,
3533 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3534 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3535 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3536 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3537 .avb_ops = &mv88e6165_avb_ops,
3538 .ptp_ops = &mv88e6165_ptp_ops,
3539 .phylink_validate = mv88e6185_phylink_validate,
3540 };
3541
3542 static const struct mv88e6xxx_ops mv88e6171_ops = {
3543 /* MV88E6XXX_FAMILY_6351 */
3544 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3545 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3546 .irl_init_all = mv88e6352_g2_irl_init_all,
3547 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3548 .phy_read = mv88e6xxx_g2_smi_phy_read,
3549 .phy_write = mv88e6xxx_g2_smi_phy_write,
3550 .port_set_link = mv88e6xxx_port_set_link,
3551 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3552 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3553 .port_tag_remap = mv88e6095_port_tag_remap,
3554 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3555 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3556 .port_set_ether_type = mv88e6351_port_set_ether_type,
3557 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3558 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3559 .port_pause_limit = mv88e6097_port_pause_limit,
3560 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3561 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3562 .port_get_cmode = mv88e6352_port_get_cmode,
3563 .port_setup_message_port = mv88e6xxx_setup_message_port,
3564 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3565 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3566 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3567 .stats_get_strings = mv88e6095_stats_get_strings,
3568 .stats_get_stats = mv88e6095_stats_get_stats,
3569 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3570 .set_egress_port = mv88e6095_g1_set_egress_port,
3571 .watchdog_ops = &mv88e6097_watchdog_ops,
3572 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3573 .pot_clear = mv88e6xxx_g2_pot_clear,
3574 .reset = mv88e6352_g1_reset,
3575 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3576 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3577 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3578 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3579 .phylink_validate = mv88e6185_phylink_validate,
3580 };
3581
3582 static const struct mv88e6xxx_ops mv88e6172_ops = {
3583 /* MV88E6XXX_FAMILY_6352 */
3584 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3585 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3586 .irl_init_all = mv88e6352_g2_irl_init_all,
3587 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3588 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3589 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3590 .phy_read = mv88e6xxx_g2_smi_phy_read,
3591 .phy_write = mv88e6xxx_g2_smi_phy_write,
3592 .port_set_link = mv88e6xxx_port_set_link,
3593 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3594 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3595 .port_tag_remap = mv88e6095_port_tag_remap,
3596 .port_set_policy = mv88e6352_port_set_policy,
3597 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3598 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3599 .port_set_ether_type = mv88e6351_port_set_ether_type,
3600 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3601 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3602 .port_pause_limit = mv88e6097_port_pause_limit,
3603 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3604 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3605 .port_get_cmode = mv88e6352_port_get_cmode,
3606 .port_setup_message_port = mv88e6xxx_setup_message_port,
3607 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3608 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3609 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3610 .stats_get_strings = mv88e6095_stats_get_strings,
3611 .stats_get_stats = mv88e6095_stats_get_stats,
3612 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3613 .set_egress_port = mv88e6095_g1_set_egress_port,
3614 .watchdog_ops = &mv88e6097_watchdog_ops,
3615 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3616 .pot_clear = mv88e6xxx_g2_pot_clear,
3617 .reset = mv88e6352_g1_reset,
3618 .rmu_disable = mv88e6352_g1_rmu_disable,
3619 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3620 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3621 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3622 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3623 .serdes_get_lane = mv88e6352_serdes_get_lane,
3624 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3625 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3626 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3627 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3628 .serdes_power = mv88e6352_serdes_power,
3629 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3630 .serdes_get_regs = mv88e6352_serdes_get_regs,
3631 .gpio_ops = &mv88e6352_gpio_ops,
3632 .phylink_validate = mv88e6352_phylink_validate,
3633 };
3634
3635 static const struct mv88e6xxx_ops mv88e6175_ops = {
3636 /* MV88E6XXX_FAMILY_6351 */
3637 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3638 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3639 .irl_init_all = mv88e6352_g2_irl_init_all,
3640 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3641 .phy_read = mv88e6xxx_g2_smi_phy_read,
3642 .phy_write = mv88e6xxx_g2_smi_phy_write,
3643 .port_set_link = mv88e6xxx_port_set_link,
3644 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3645 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3646 .port_tag_remap = mv88e6095_port_tag_remap,
3647 .port_set_policy = mv88e6352_port_set_policy,
3648 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3649 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3650 .port_set_ether_type = mv88e6351_port_set_ether_type,
3651 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3652 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3653 .port_pause_limit = mv88e6097_port_pause_limit,
3654 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3655 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3656 .port_get_cmode = mv88e6352_port_get_cmode,
3657 .port_setup_message_port = mv88e6xxx_setup_message_port,
3658 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3659 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3660 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3661 .stats_get_strings = mv88e6095_stats_get_strings,
3662 .stats_get_stats = mv88e6095_stats_get_stats,
3663 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3664 .set_egress_port = mv88e6095_g1_set_egress_port,
3665 .watchdog_ops = &mv88e6097_watchdog_ops,
3666 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3667 .pot_clear = mv88e6xxx_g2_pot_clear,
3668 .reset = mv88e6352_g1_reset,
3669 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3670 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3671 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3672 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3673 .phylink_validate = mv88e6185_phylink_validate,
3674 };
3675
3676 static const struct mv88e6xxx_ops mv88e6176_ops = {
3677 /* MV88E6XXX_FAMILY_6352 */
3678 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3679 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3680 .irl_init_all = mv88e6352_g2_irl_init_all,
3681 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3682 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3683 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3684 .phy_read = mv88e6xxx_g2_smi_phy_read,
3685 .phy_write = mv88e6xxx_g2_smi_phy_write,
3686 .port_set_link = mv88e6xxx_port_set_link,
3687 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3688 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3689 .port_tag_remap = mv88e6095_port_tag_remap,
3690 .port_set_policy = mv88e6352_port_set_policy,
3691 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3692 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3693 .port_set_ether_type = mv88e6351_port_set_ether_type,
3694 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3695 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3696 .port_pause_limit = mv88e6097_port_pause_limit,
3697 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3698 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3699 .port_get_cmode = mv88e6352_port_get_cmode,
3700 .port_setup_message_port = mv88e6xxx_setup_message_port,
3701 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3702 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3703 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3704 .stats_get_strings = mv88e6095_stats_get_strings,
3705 .stats_get_stats = mv88e6095_stats_get_stats,
3706 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3707 .set_egress_port = mv88e6095_g1_set_egress_port,
3708 .watchdog_ops = &mv88e6097_watchdog_ops,
3709 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3710 .pot_clear = mv88e6xxx_g2_pot_clear,
3711 .reset = mv88e6352_g1_reset,
3712 .rmu_disable = mv88e6352_g1_rmu_disable,
3713 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3714 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3715 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3716 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3717 .serdes_get_lane = mv88e6352_serdes_get_lane,
3718 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3719 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3720 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3721 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3722 .serdes_power = mv88e6352_serdes_power,
3723 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3724 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3725 .serdes_irq_status = mv88e6352_serdes_irq_status,
3726 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3727 .serdes_get_regs = mv88e6352_serdes_get_regs,
3728 .gpio_ops = &mv88e6352_gpio_ops,
3729 .phylink_validate = mv88e6352_phylink_validate,
3730 };
3731
3732 static const struct mv88e6xxx_ops mv88e6185_ops = {
3733 /* MV88E6XXX_FAMILY_6185 */
3734 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3735 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3736 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3737 .phy_read = mv88e6185_phy_ppu_read,
3738 .phy_write = mv88e6185_phy_ppu_write,
3739 .port_set_link = mv88e6xxx_port_set_link,
3740 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3741 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3742 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3743 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3744 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3745 .port_set_pause = mv88e6185_port_set_pause,
3746 .port_get_cmode = mv88e6185_port_get_cmode,
3747 .port_setup_message_port = mv88e6xxx_setup_message_port,
3748 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3749 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3750 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3751 .stats_get_strings = mv88e6095_stats_get_strings,
3752 .stats_get_stats = mv88e6095_stats_get_stats,
3753 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3754 .set_egress_port = mv88e6095_g1_set_egress_port,
3755 .watchdog_ops = &mv88e6097_watchdog_ops,
3756 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3757 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3758 .ppu_enable = mv88e6185_g1_ppu_enable,
3759 .ppu_disable = mv88e6185_g1_ppu_disable,
3760 .reset = mv88e6185_g1_reset,
3761 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3762 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3763 .phylink_validate = mv88e6185_phylink_validate,
3764 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3765 };
3766
3767 static const struct mv88e6xxx_ops mv88e6190_ops = {
3768 /* MV88E6XXX_FAMILY_6390 */
3769 .setup_errata = mv88e6390_setup_errata,
3770 .irl_init_all = mv88e6390_g2_irl_init_all,
3771 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3772 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3773 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3774 .phy_read = mv88e6xxx_g2_smi_phy_read,
3775 .phy_write = mv88e6xxx_g2_smi_phy_write,
3776 .port_set_link = mv88e6xxx_port_set_link,
3777 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3778 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3779 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3780 .port_tag_remap = mv88e6390_port_tag_remap,
3781 .port_set_policy = mv88e6352_port_set_policy,
3782 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3783 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3784 .port_set_ether_type = mv88e6351_port_set_ether_type,
3785 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3786 .port_pause_limit = mv88e6390_port_pause_limit,
3787 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3788 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3789 .port_get_cmode = mv88e6352_port_get_cmode,
3790 .port_set_cmode = mv88e6390_port_set_cmode,
3791 .port_setup_message_port = mv88e6xxx_setup_message_port,
3792 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3793 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3794 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3795 .stats_get_strings = mv88e6320_stats_get_strings,
3796 .stats_get_stats = mv88e6390_stats_get_stats,
3797 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3798 .set_egress_port = mv88e6390_g1_set_egress_port,
3799 .watchdog_ops = &mv88e6390_watchdog_ops,
3800 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3801 .pot_clear = mv88e6xxx_g2_pot_clear,
3802 .reset = mv88e6352_g1_reset,
3803 .rmu_disable = mv88e6390_g1_rmu_disable,
3804 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3805 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3806 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3807 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3808 .serdes_power = mv88e6390_serdes_power,
3809 .serdes_get_lane = mv88e6390_serdes_get_lane,
3810 /* Check status register pause & lpa register */
3811 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3812 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3813 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3814 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3815 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3816 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3817 .serdes_irq_status = mv88e6390_serdes_irq_status,
3818 .serdes_get_strings = mv88e6390_serdes_get_strings,
3819 .serdes_get_stats = mv88e6390_serdes_get_stats,
3820 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3821 .serdes_get_regs = mv88e6390_serdes_get_regs,
3822 .gpio_ops = &mv88e6352_gpio_ops,
3823 .phylink_validate = mv88e6390_phylink_validate,
3824 };
3825
3826 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3827 /* MV88E6XXX_FAMILY_6390 */
3828 .setup_errata = mv88e6390_setup_errata,
3829 .irl_init_all = mv88e6390_g2_irl_init_all,
3830 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3831 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3832 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3833 .phy_read = mv88e6xxx_g2_smi_phy_read,
3834 .phy_write = mv88e6xxx_g2_smi_phy_write,
3835 .port_set_link = mv88e6xxx_port_set_link,
3836 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3837 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3838 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3839 .port_tag_remap = mv88e6390_port_tag_remap,
3840 .port_set_policy = mv88e6352_port_set_policy,
3841 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3842 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3843 .port_set_ether_type = mv88e6351_port_set_ether_type,
3844 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3845 .port_pause_limit = mv88e6390_port_pause_limit,
3846 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3847 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3848 .port_get_cmode = mv88e6352_port_get_cmode,
3849 .port_set_cmode = mv88e6390x_port_set_cmode,
3850 .port_setup_message_port = mv88e6xxx_setup_message_port,
3851 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3852 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3853 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3854 .stats_get_strings = mv88e6320_stats_get_strings,
3855 .stats_get_stats = mv88e6390_stats_get_stats,
3856 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3857 .set_egress_port = mv88e6390_g1_set_egress_port,
3858 .watchdog_ops = &mv88e6390_watchdog_ops,
3859 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3860 .pot_clear = mv88e6xxx_g2_pot_clear,
3861 .reset = mv88e6352_g1_reset,
3862 .rmu_disable = mv88e6390_g1_rmu_disable,
3863 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3864 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3865 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3866 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3867 .serdes_power = mv88e6390_serdes_power,
3868 .serdes_get_lane = mv88e6390x_serdes_get_lane,
3869 /* Check status register pause & lpa register */
3870 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3871 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3872 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3873 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3874 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3875 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3876 .serdes_irq_status = mv88e6390_serdes_irq_status,
3877 .serdes_get_strings = mv88e6390_serdes_get_strings,
3878 .serdes_get_stats = mv88e6390_serdes_get_stats,
3879 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3880 .serdes_get_regs = mv88e6390_serdes_get_regs,
3881 .gpio_ops = &mv88e6352_gpio_ops,
3882 .phylink_validate = mv88e6390x_phylink_validate,
3883 };
3884
3885 static const struct mv88e6xxx_ops mv88e6191_ops = {
3886 /* MV88E6XXX_FAMILY_6390 */
3887 .setup_errata = mv88e6390_setup_errata,
3888 .irl_init_all = mv88e6390_g2_irl_init_all,
3889 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3890 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3891 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3892 .phy_read = mv88e6xxx_g2_smi_phy_read,
3893 .phy_write = mv88e6xxx_g2_smi_phy_write,
3894 .port_set_link = mv88e6xxx_port_set_link,
3895 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3896 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3897 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3898 .port_tag_remap = mv88e6390_port_tag_remap,
3899 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3900 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3901 .port_set_ether_type = mv88e6351_port_set_ether_type,
3902 .port_pause_limit = mv88e6390_port_pause_limit,
3903 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3904 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3905 .port_get_cmode = mv88e6352_port_get_cmode,
3906 .port_set_cmode = mv88e6390_port_set_cmode,
3907 .port_setup_message_port = mv88e6xxx_setup_message_port,
3908 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3909 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3910 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3911 .stats_get_strings = mv88e6320_stats_get_strings,
3912 .stats_get_stats = mv88e6390_stats_get_stats,
3913 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3914 .set_egress_port = mv88e6390_g1_set_egress_port,
3915 .watchdog_ops = &mv88e6390_watchdog_ops,
3916 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3917 .pot_clear = mv88e6xxx_g2_pot_clear,
3918 .reset = mv88e6352_g1_reset,
3919 .rmu_disable = mv88e6390_g1_rmu_disable,
3920 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3921 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3922 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3923 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3924 .serdes_power = mv88e6390_serdes_power,
3925 .serdes_get_lane = mv88e6390_serdes_get_lane,
3926 /* Check status register pause & lpa register */
3927 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3928 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3929 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3930 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3931 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3932 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3933 .serdes_irq_status = mv88e6390_serdes_irq_status,
3934 .serdes_get_strings = mv88e6390_serdes_get_strings,
3935 .serdes_get_stats = mv88e6390_serdes_get_stats,
3936 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3937 .serdes_get_regs = mv88e6390_serdes_get_regs,
3938 .avb_ops = &mv88e6390_avb_ops,
3939 .ptp_ops = &mv88e6352_ptp_ops,
3940 .phylink_validate = mv88e6390_phylink_validate,
3941 };
3942
3943 static const struct mv88e6xxx_ops mv88e6240_ops = {
3944 /* MV88E6XXX_FAMILY_6352 */
3945 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3946 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3947 .irl_init_all = mv88e6352_g2_irl_init_all,
3948 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3949 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3950 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3951 .phy_read = mv88e6xxx_g2_smi_phy_read,
3952 .phy_write = mv88e6xxx_g2_smi_phy_write,
3953 .port_set_link = mv88e6xxx_port_set_link,
3954 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3955 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3956 .port_tag_remap = mv88e6095_port_tag_remap,
3957 .port_set_policy = mv88e6352_port_set_policy,
3958 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3959 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3960 .port_set_ether_type = mv88e6351_port_set_ether_type,
3961 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3962 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3963 .port_pause_limit = mv88e6097_port_pause_limit,
3964 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3965 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3966 .port_get_cmode = mv88e6352_port_get_cmode,
3967 .port_setup_message_port = mv88e6xxx_setup_message_port,
3968 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3969 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3970 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3971 .stats_get_strings = mv88e6095_stats_get_strings,
3972 .stats_get_stats = mv88e6095_stats_get_stats,
3973 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3974 .set_egress_port = mv88e6095_g1_set_egress_port,
3975 .watchdog_ops = &mv88e6097_watchdog_ops,
3976 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3977 .pot_clear = mv88e6xxx_g2_pot_clear,
3978 .reset = mv88e6352_g1_reset,
3979 .rmu_disable = mv88e6352_g1_rmu_disable,
3980 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3981 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3982 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3983 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3984 .serdes_get_lane = mv88e6352_serdes_get_lane,
3985 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3986 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3987 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3988 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3989 .serdes_power = mv88e6352_serdes_power,
3990 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3991 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3992 .serdes_irq_status = mv88e6352_serdes_irq_status,
3993 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3994 .serdes_get_regs = mv88e6352_serdes_get_regs,
3995 .gpio_ops = &mv88e6352_gpio_ops,
3996 .avb_ops = &mv88e6352_avb_ops,
3997 .ptp_ops = &mv88e6352_ptp_ops,
3998 .phylink_validate = mv88e6352_phylink_validate,
3999 };
4000
4001 static const struct mv88e6xxx_ops mv88e6250_ops = {
4002 /* MV88E6XXX_FAMILY_6250 */
4003 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4004 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4005 .irl_init_all = mv88e6352_g2_irl_init_all,
4006 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4007 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4009 .phy_read = mv88e6xxx_g2_smi_phy_read,
4010 .phy_write = mv88e6xxx_g2_smi_phy_write,
4011 .port_set_link = mv88e6xxx_port_set_link,
4012 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4013 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4014 .port_tag_remap = mv88e6095_port_tag_remap,
4015 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4016 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4017 .port_set_ether_type = mv88e6351_port_set_ether_type,
4018 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4019 .port_pause_limit = mv88e6097_port_pause_limit,
4020 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4021 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4022 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4023 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4024 .stats_get_strings = mv88e6250_stats_get_strings,
4025 .stats_get_stats = mv88e6250_stats_get_stats,
4026 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4027 .set_egress_port = mv88e6095_g1_set_egress_port,
4028 .watchdog_ops = &mv88e6250_watchdog_ops,
4029 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4030 .pot_clear = mv88e6xxx_g2_pot_clear,
4031 .reset = mv88e6250_g1_reset,
4032 .vtu_getnext = mv88e6250_g1_vtu_getnext,
4033 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4034 .avb_ops = &mv88e6352_avb_ops,
4035 .ptp_ops = &mv88e6250_ptp_ops,
4036 .phylink_validate = mv88e6065_phylink_validate,
4037 };
4038
4039 static const struct mv88e6xxx_ops mv88e6290_ops = {
4040 /* MV88E6XXX_FAMILY_6390 */
4041 .setup_errata = mv88e6390_setup_errata,
4042 .irl_init_all = mv88e6390_g2_irl_init_all,
4043 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4044 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4045 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4046 .phy_read = mv88e6xxx_g2_smi_phy_read,
4047 .phy_write = mv88e6xxx_g2_smi_phy_write,
4048 .port_set_link = mv88e6xxx_port_set_link,
4049 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4050 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4051 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4052 .port_tag_remap = mv88e6390_port_tag_remap,
4053 .port_set_policy = mv88e6352_port_set_policy,
4054 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4055 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4056 .port_set_ether_type = mv88e6351_port_set_ether_type,
4057 .port_pause_limit = mv88e6390_port_pause_limit,
4058 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4059 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4060 .port_get_cmode = mv88e6352_port_get_cmode,
4061 .port_set_cmode = mv88e6390_port_set_cmode,
4062 .port_setup_message_port = mv88e6xxx_setup_message_port,
4063 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4064 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4065 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4066 .stats_get_strings = mv88e6320_stats_get_strings,
4067 .stats_get_stats = mv88e6390_stats_get_stats,
4068 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4069 .set_egress_port = mv88e6390_g1_set_egress_port,
4070 .watchdog_ops = &mv88e6390_watchdog_ops,
4071 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4072 .pot_clear = mv88e6xxx_g2_pot_clear,
4073 .reset = mv88e6352_g1_reset,
4074 .rmu_disable = mv88e6390_g1_rmu_disable,
4075 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4076 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4077 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4078 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4079 .serdes_power = mv88e6390_serdes_power,
4080 .serdes_get_lane = mv88e6390_serdes_get_lane,
4081 /* Check status register pause & lpa register */
4082 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4083 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4084 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4085 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4086 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4087 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4088 .serdes_irq_status = mv88e6390_serdes_irq_status,
4089 .serdes_get_strings = mv88e6390_serdes_get_strings,
4090 .serdes_get_stats = mv88e6390_serdes_get_stats,
4091 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4092 .serdes_get_regs = mv88e6390_serdes_get_regs,
4093 .gpio_ops = &mv88e6352_gpio_ops,
4094 .avb_ops = &mv88e6390_avb_ops,
4095 .ptp_ops = &mv88e6352_ptp_ops,
4096 .phylink_validate = mv88e6390_phylink_validate,
4097 };
4098
4099 static const struct mv88e6xxx_ops mv88e6320_ops = {
4100 /* MV88E6XXX_FAMILY_6320 */
4101 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4102 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4103 .irl_init_all = mv88e6352_g2_irl_init_all,
4104 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4105 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4106 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4107 .phy_read = mv88e6xxx_g2_smi_phy_read,
4108 .phy_write = mv88e6xxx_g2_smi_phy_write,
4109 .port_set_link = mv88e6xxx_port_set_link,
4110 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4111 .port_tag_remap = mv88e6095_port_tag_remap,
4112 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4113 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4114 .port_set_ether_type = mv88e6351_port_set_ether_type,
4115 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4116 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4117 .port_pause_limit = mv88e6097_port_pause_limit,
4118 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4119 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4120 .port_get_cmode = mv88e6352_port_get_cmode,
4121 .port_setup_message_port = mv88e6xxx_setup_message_port,
4122 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4123 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4124 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4125 .stats_get_strings = mv88e6320_stats_get_strings,
4126 .stats_get_stats = mv88e6320_stats_get_stats,
4127 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4128 .set_egress_port = mv88e6095_g1_set_egress_port,
4129 .watchdog_ops = &mv88e6390_watchdog_ops,
4130 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4131 .pot_clear = mv88e6xxx_g2_pot_clear,
4132 .reset = mv88e6352_g1_reset,
4133 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4134 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4135 .gpio_ops = &mv88e6352_gpio_ops,
4136 .avb_ops = &mv88e6352_avb_ops,
4137 .ptp_ops = &mv88e6352_ptp_ops,
4138 .phylink_validate = mv88e6185_phylink_validate,
4139 };
4140
4141 static const struct mv88e6xxx_ops mv88e6321_ops = {
4142 /* MV88E6XXX_FAMILY_6320 */
4143 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4144 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4145 .irl_init_all = mv88e6352_g2_irl_init_all,
4146 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4147 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4148 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4149 .phy_read = mv88e6xxx_g2_smi_phy_read,
4150 .phy_write = mv88e6xxx_g2_smi_phy_write,
4151 .port_set_link = mv88e6xxx_port_set_link,
4152 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4153 .port_tag_remap = mv88e6095_port_tag_remap,
4154 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4155 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4156 .port_set_ether_type = mv88e6351_port_set_ether_type,
4157 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4158 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4159 .port_pause_limit = mv88e6097_port_pause_limit,
4160 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4161 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4162 .port_get_cmode = mv88e6352_port_get_cmode,
4163 .port_setup_message_port = mv88e6xxx_setup_message_port,
4164 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4165 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4166 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4167 .stats_get_strings = mv88e6320_stats_get_strings,
4168 .stats_get_stats = mv88e6320_stats_get_stats,
4169 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4170 .set_egress_port = mv88e6095_g1_set_egress_port,
4171 .watchdog_ops = &mv88e6390_watchdog_ops,
4172 .reset = mv88e6352_g1_reset,
4173 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4174 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4175 .gpio_ops = &mv88e6352_gpio_ops,
4176 .avb_ops = &mv88e6352_avb_ops,
4177 .ptp_ops = &mv88e6352_ptp_ops,
4178 .phylink_validate = mv88e6185_phylink_validate,
4179 };
4180
4181 static const struct mv88e6xxx_ops mv88e6341_ops = {
4182 /* MV88E6XXX_FAMILY_6341 */
4183 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4184 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4185 .irl_init_all = mv88e6352_g2_irl_init_all,
4186 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4187 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4188 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4189 .phy_read = mv88e6xxx_g2_smi_phy_read,
4190 .phy_write = mv88e6xxx_g2_smi_phy_write,
4191 .port_set_link = mv88e6xxx_port_set_link,
4192 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4193 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4194 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4195 .port_tag_remap = mv88e6095_port_tag_remap,
4196 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4197 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4198 .port_set_ether_type = mv88e6351_port_set_ether_type,
4199 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4200 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4201 .port_pause_limit = mv88e6097_port_pause_limit,
4202 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4203 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4204 .port_get_cmode = mv88e6352_port_get_cmode,
4205 .port_set_cmode = mv88e6341_port_set_cmode,
4206 .port_setup_message_port = mv88e6xxx_setup_message_port,
4207 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4208 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4209 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4210 .stats_get_strings = mv88e6320_stats_get_strings,
4211 .stats_get_stats = mv88e6390_stats_get_stats,
4212 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4213 .set_egress_port = mv88e6390_g1_set_egress_port,
4214 .watchdog_ops = &mv88e6390_watchdog_ops,
4215 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4216 .pot_clear = mv88e6xxx_g2_pot_clear,
4217 .reset = mv88e6352_g1_reset,
4218 .rmu_disable = mv88e6390_g1_rmu_disable,
4219 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4220 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4221 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4222 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4223 .serdes_power = mv88e6390_serdes_power,
4224 .serdes_get_lane = mv88e6341_serdes_get_lane,
4225 /* Check status register pause & lpa register */
4226 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4227 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4228 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4229 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4230 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4231 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4232 .serdes_irq_status = mv88e6390_serdes_irq_status,
4233 .gpio_ops = &mv88e6352_gpio_ops,
4234 .avb_ops = &mv88e6390_avb_ops,
4235 .ptp_ops = &mv88e6352_ptp_ops,
4236 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4237 .serdes_get_strings = mv88e6390_serdes_get_strings,
4238 .serdes_get_stats = mv88e6390_serdes_get_stats,
4239 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4240 .serdes_get_regs = mv88e6390_serdes_get_regs,
4241 .phylink_validate = mv88e6341_phylink_validate,
4242 };
4243
4244 static const struct mv88e6xxx_ops mv88e6350_ops = {
4245 /* MV88E6XXX_FAMILY_6351 */
4246 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4247 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4248 .irl_init_all = mv88e6352_g2_irl_init_all,
4249 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4250 .phy_read = mv88e6xxx_g2_smi_phy_read,
4251 .phy_write = mv88e6xxx_g2_smi_phy_write,
4252 .port_set_link = mv88e6xxx_port_set_link,
4253 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4254 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4255 .port_tag_remap = mv88e6095_port_tag_remap,
4256 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4257 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4258 .port_set_ether_type = mv88e6351_port_set_ether_type,
4259 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4260 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4261 .port_pause_limit = mv88e6097_port_pause_limit,
4262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4264 .port_get_cmode = mv88e6352_port_get_cmode,
4265 .port_setup_message_port = mv88e6xxx_setup_message_port,
4266 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4267 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4268 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4269 .stats_get_strings = mv88e6095_stats_get_strings,
4270 .stats_get_stats = mv88e6095_stats_get_stats,
4271 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4272 .set_egress_port = mv88e6095_g1_set_egress_port,
4273 .watchdog_ops = &mv88e6097_watchdog_ops,
4274 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4275 .pot_clear = mv88e6xxx_g2_pot_clear,
4276 .reset = mv88e6352_g1_reset,
4277 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4278 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4279 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4280 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4281 .phylink_validate = mv88e6185_phylink_validate,
4282 };
4283
4284 static const struct mv88e6xxx_ops mv88e6351_ops = {
4285 /* MV88E6XXX_FAMILY_6351 */
4286 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4287 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4288 .irl_init_all = mv88e6352_g2_irl_init_all,
4289 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4290 .phy_read = mv88e6xxx_g2_smi_phy_read,
4291 .phy_write = mv88e6xxx_g2_smi_phy_write,
4292 .port_set_link = mv88e6xxx_port_set_link,
4293 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4294 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4295 .port_tag_remap = mv88e6095_port_tag_remap,
4296 .port_set_policy = mv88e6352_port_set_policy,
4297 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4298 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4299 .port_set_ether_type = mv88e6351_port_set_ether_type,
4300 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4301 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4302 .port_pause_limit = mv88e6097_port_pause_limit,
4303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4305 .port_get_cmode = mv88e6352_port_get_cmode,
4306 .port_setup_message_port = mv88e6xxx_setup_message_port,
4307 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4308 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4309 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4310 .stats_get_strings = mv88e6095_stats_get_strings,
4311 .stats_get_stats = mv88e6095_stats_get_stats,
4312 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4313 .set_egress_port = mv88e6095_g1_set_egress_port,
4314 .watchdog_ops = &mv88e6097_watchdog_ops,
4315 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4316 .pot_clear = mv88e6xxx_g2_pot_clear,
4317 .reset = mv88e6352_g1_reset,
4318 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4319 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4320 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4321 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4322 .avb_ops = &mv88e6352_avb_ops,
4323 .ptp_ops = &mv88e6352_ptp_ops,
4324 .phylink_validate = mv88e6185_phylink_validate,
4325 };
4326
4327 static const struct mv88e6xxx_ops mv88e6352_ops = {
4328 /* MV88E6XXX_FAMILY_6352 */
4329 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4330 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4331 .irl_init_all = mv88e6352_g2_irl_init_all,
4332 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4333 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4334 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4335 .phy_read = mv88e6xxx_g2_smi_phy_read,
4336 .phy_write = mv88e6xxx_g2_smi_phy_write,
4337 .port_set_link = mv88e6xxx_port_set_link,
4338 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4339 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4340 .port_tag_remap = mv88e6095_port_tag_remap,
4341 .port_set_policy = mv88e6352_port_set_policy,
4342 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4343 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4344 .port_set_ether_type = mv88e6351_port_set_ether_type,
4345 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4346 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4347 .port_pause_limit = mv88e6097_port_pause_limit,
4348 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4349 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4350 .port_get_cmode = mv88e6352_port_get_cmode,
4351 .port_setup_message_port = mv88e6xxx_setup_message_port,
4352 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4353 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4354 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4355 .stats_get_strings = mv88e6095_stats_get_strings,
4356 .stats_get_stats = mv88e6095_stats_get_stats,
4357 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4358 .set_egress_port = mv88e6095_g1_set_egress_port,
4359 .watchdog_ops = &mv88e6097_watchdog_ops,
4360 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4361 .pot_clear = mv88e6xxx_g2_pot_clear,
4362 .reset = mv88e6352_g1_reset,
4363 .rmu_disable = mv88e6352_g1_rmu_disable,
4364 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4365 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4366 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4367 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4368 .serdes_get_lane = mv88e6352_serdes_get_lane,
4369 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4370 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4371 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4372 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4373 .serdes_power = mv88e6352_serdes_power,
4374 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4375 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4376 .serdes_irq_status = mv88e6352_serdes_irq_status,
4377 .gpio_ops = &mv88e6352_gpio_ops,
4378 .avb_ops = &mv88e6352_avb_ops,
4379 .ptp_ops = &mv88e6352_ptp_ops,
4380 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4381 .serdes_get_strings = mv88e6352_serdes_get_strings,
4382 .serdes_get_stats = mv88e6352_serdes_get_stats,
4383 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4384 .serdes_get_regs = mv88e6352_serdes_get_regs,
4385 .phylink_validate = mv88e6352_phylink_validate,
4386 };
4387
4388 static const struct mv88e6xxx_ops mv88e6390_ops = {
4389 /* MV88E6XXX_FAMILY_6390 */
4390 .setup_errata = mv88e6390_setup_errata,
4391 .irl_init_all = mv88e6390_g2_irl_init_all,
4392 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4393 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4394 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4395 .phy_read = mv88e6xxx_g2_smi_phy_read,
4396 .phy_write = mv88e6xxx_g2_smi_phy_write,
4397 .port_set_link = mv88e6xxx_port_set_link,
4398 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4399 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4400 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4401 .port_tag_remap = mv88e6390_port_tag_remap,
4402 .port_set_policy = mv88e6352_port_set_policy,
4403 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4404 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4405 .port_set_ether_type = mv88e6351_port_set_ether_type,
4406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4407 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4408 .port_pause_limit = mv88e6390_port_pause_limit,
4409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4411 .port_get_cmode = mv88e6352_port_get_cmode,
4412 .port_set_cmode = mv88e6390_port_set_cmode,
4413 .port_setup_message_port = mv88e6xxx_setup_message_port,
4414 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4415 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4416 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4417 .stats_get_strings = mv88e6320_stats_get_strings,
4418 .stats_get_stats = mv88e6390_stats_get_stats,
4419 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4420 .set_egress_port = mv88e6390_g1_set_egress_port,
4421 .watchdog_ops = &mv88e6390_watchdog_ops,
4422 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4423 .pot_clear = mv88e6xxx_g2_pot_clear,
4424 .reset = mv88e6352_g1_reset,
4425 .rmu_disable = mv88e6390_g1_rmu_disable,
4426 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4427 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4428 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4429 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4430 .serdes_power = mv88e6390_serdes_power,
4431 .serdes_get_lane = mv88e6390_serdes_get_lane,
4432 /* Check status register pause & lpa register */
4433 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4434 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4435 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4436 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4437 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4438 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4439 .serdes_irq_status = mv88e6390_serdes_irq_status,
4440 .gpio_ops = &mv88e6352_gpio_ops,
4441 .avb_ops = &mv88e6390_avb_ops,
4442 .ptp_ops = &mv88e6352_ptp_ops,
4443 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4444 .serdes_get_strings = mv88e6390_serdes_get_strings,
4445 .serdes_get_stats = mv88e6390_serdes_get_stats,
4446 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4447 .serdes_get_regs = mv88e6390_serdes_get_regs,
4448 .phylink_validate = mv88e6390_phylink_validate,
4449 };
4450
4451 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4452 /* MV88E6XXX_FAMILY_6390 */
4453 .setup_errata = mv88e6390_setup_errata,
4454 .irl_init_all = mv88e6390_g2_irl_init_all,
4455 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4456 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4457 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4458 .phy_read = mv88e6xxx_g2_smi_phy_read,
4459 .phy_write = mv88e6xxx_g2_smi_phy_write,
4460 .port_set_link = mv88e6xxx_port_set_link,
4461 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4462 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4463 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4464 .port_tag_remap = mv88e6390_port_tag_remap,
4465 .port_set_policy = mv88e6352_port_set_policy,
4466 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4467 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4468 .port_set_ether_type = mv88e6351_port_set_ether_type,
4469 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4470 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4471 .port_pause_limit = mv88e6390_port_pause_limit,
4472 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4473 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4474 .port_get_cmode = mv88e6352_port_get_cmode,
4475 .port_set_cmode = mv88e6390x_port_set_cmode,
4476 .port_setup_message_port = mv88e6xxx_setup_message_port,
4477 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4478 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4479 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4480 .stats_get_strings = mv88e6320_stats_get_strings,
4481 .stats_get_stats = mv88e6390_stats_get_stats,
4482 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4483 .set_egress_port = mv88e6390_g1_set_egress_port,
4484 .watchdog_ops = &mv88e6390_watchdog_ops,
4485 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4486 .pot_clear = mv88e6xxx_g2_pot_clear,
4487 .reset = mv88e6352_g1_reset,
4488 .rmu_disable = mv88e6390_g1_rmu_disable,
4489 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4490 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4491 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4492 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4493 .serdes_power = mv88e6390_serdes_power,
4494 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4495 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4496 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4497 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4498 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4499 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4500 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4501 .serdes_irq_status = mv88e6390_serdes_irq_status,
4502 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4503 .serdes_get_strings = mv88e6390_serdes_get_strings,
4504 .serdes_get_stats = mv88e6390_serdes_get_stats,
4505 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4506 .serdes_get_regs = mv88e6390_serdes_get_regs,
4507 .gpio_ops = &mv88e6352_gpio_ops,
4508 .avb_ops = &mv88e6390_avb_ops,
4509 .ptp_ops = &mv88e6352_ptp_ops,
4510 .phylink_validate = mv88e6390x_phylink_validate,
4511 };
4512
4513 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4514 [MV88E6085] = {
4515 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4516 .family = MV88E6XXX_FAMILY_6097,
4517 .name = "Marvell 88E6085",
4518 .num_databases = 4096,
4519 .num_macs = 8192,
4520 .num_ports = 10,
4521 .num_internal_phys = 5,
4522 .max_vid = 4095,
4523 .port_base_addr = 0x10,
4524 .phy_base_addr = 0x0,
4525 .global1_addr = 0x1b,
4526 .global2_addr = 0x1c,
4527 .age_time_coeff = 15000,
4528 .g1_irqs = 8,
4529 .g2_irqs = 10,
4530 .atu_move_port_mask = 0xf,
4531 .pvt = true,
4532 .multi_chip = true,
4533 .tag_protocol = DSA_TAG_PROTO_DSA,
4534 .ops = &mv88e6085_ops,
4535 },
4536
4537 [MV88E6095] = {
4538 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4539 .family = MV88E6XXX_FAMILY_6095,
4540 .name = "Marvell 88E6095/88E6095F",
4541 .num_databases = 256,
4542 .num_macs = 8192,
4543 .num_ports = 11,
4544 .num_internal_phys = 0,
4545 .max_vid = 4095,
4546 .port_base_addr = 0x10,
4547 .phy_base_addr = 0x0,
4548 .global1_addr = 0x1b,
4549 .global2_addr = 0x1c,
4550 .age_time_coeff = 15000,
4551 .g1_irqs = 8,
4552 .atu_move_port_mask = 0xf,
4553 .multi_chip = true,
4554 .tag_protocol = DSA_TAG_PROTO_DSA,
4555 .ops = &mv88e6095_ops,
4556 },
4557
4558 [MV88E6097] = {
4559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4560 .family = MV88E6XXX_FAMILY_6097,
4561 .name = "Marvell 88E6097/88E6097F",
4562 .num_databases = 4096,
4563 .num_macs = 8192,
4564 .num_ports = 11,
4565 .num_internal_phys = 8,
4566 .max_vid = 4095,
4567 .port_base_addr = 0x10,
4568 .phy_base_addr = 0x0,
4569 .global1_addr = 0x1b,
4570 .global2_addr = 0x1c,
4571 .age_time_coeff = 15000,
4572 .g1_irqs = 8,
4573 .g2_irqs = 10,
4574 .atu_move_port_mask = 0xf,
4575 .pvt = true,
4576 .multi_chip = true,
4577 .tag_protocol = DSA_TAG_PROTO_EDSA,
4578 .ops = &mv88e6097_ops,
4579 },
4580
4581 [MV88E6123] = {
4582 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4583 .family = MV88E6XXX_FAMILY_6165,
4584 .name = "Marvell 88E6123",
4585 .num_databases = 4096,
4586 .num_macs = 1024,
4587 .num_ports = 3,
4588 .num_internal_phys = 5,
4589 .max_vid = 4095,
4590 .port_base_addr = 0x10,
4591 .phy_base_addr = 0x0,
4592 .global1_addr = 0x1b,
4593 .global2_addr = 0x1c,
4594 .age_time_coeff = 15000,
4595 .g1_irqs = 9,
4596 .g2_irqs = 10,
4597 .atu_move_port_mask = 0xf,
4598 .pvt = true,
4599 .multi_chip = true,
4600 .tag_protocol = DSA_TAG_PROTO_EDSA,
4601 .ops = &mv88e6123_ops,
4602 },
4603
4604 [MV88E6131] = {
4605 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4606 .family = MV88E6XXX_FAMILY_6185,
4607 .name = "Marvell 88E6131",
4608 .num_databases = 256,
4609 .num_macs = 8192,
4610 .num_ports = 8,
4611 .num_internal_phys = 0,
4612 .max_vid = 4095,
4613 .port_base_addr = 0x10,
4614 .phy_base_addr = 0x0,
4615 .global1_addr = 0x1b,
4616 .global2_addr = 0x1c,
4617 .age_time_coeff = 15000,
4618 .g1_irqs = 9,
4619 .atu_move_port_mask = 0xf,
4620 .multi_chip = true,
4621 .tag_protocol = DSA_TAG_PROTO_DSA,
4622 .ops = &mv88e6131_ops,
4623 },
4624
4625 [MV88E6141] = {
4626 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4627 .family = MV88E6XXX_FAMILY_6341,
4628 .name = "Marvell 88E6141",
4629 .num_databases = 4096,
4630 .num_macs = 2048,
4631 .num_ports = 6,
4632 .num_internal_phys = 5,
4633 .num_gpio = 11,
4634 .max_vid = 4095,
4635 .port_base_addr = 0x10,
4636 .phy_base_addr = 0x10,
4637 .global1_addr = 0x1b,
4638 .global2_addr = 0x1c,
4639 .age_time_coeff = 3750,
4640 .atu_move_port_mask = 0x1f,
4641 .g1_irqs = 9,
4642 .g2_irqs = 10,
4643 .pvt = true,
4644 .multi_chip = true,
4645 .tag_protocol = DSA_TAG_PROTO_EDSA,
4646 .ops = &mv88e6141_ops,
4647 },
4648
4649 [MV88E6161] = {
4650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4651 .family = MV88E6XXX_FAMILY_6165,
4652 .name = "Marvell 88E6161",
4653 .num_databases = 4096,
4654 .num_macs = 1024,
4655 .num_ports = 6,
4656 .num_internal_phys = 5,
4657 .max_vid = 4095,
4658 .port_base_addr = 0x10,
4659 .phy_base_addr = 0x0,
4660 .global1_addr = 0x1b,
4661 .global2_addr = 0x1c,
4662 .age_time_coeff = 15000,
4663 .g1_irqs = 9,
4664 .g2_irqs = 10,
4665 .atu_move_port_mask = 0xf,
4666 .pvt = true,
4667 .multi_chip = true,
4668 .tag_protocol = DSA_TAG_PROTO_EDSA,
4669 .ptp_support = true,
4670 .ops = &mv88e6161_ops,
4671 },
4672
4673 [MV88E6165] = {
4674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4675 .family = MV88E6XXX_FAMILY_6165,
4676 .name = "Marvell 88E6165",
4677 .num_databases = 4096,
4678 .num_macs = 8192,
4679 .num_ports = 6,
4680 .num_internal_phys = 0,
4681 .max_vid = 4095,
4682 .port_base_addr = 0x10,
4683 .phy_base_addr = 0x0,
4684 .global1_addr = 0x1b,
4685 .global2_addr = 0x1c,
4686 .age_time_coeff = 15000,
4687 .g1_irqs = 9,
4688 .g2_irqs = 10,
4689 .atu_move_port_mask = 0xf,
4690 .pvt = true,
4691 .multi_chip = true,
4692 .tag_protocol = DSA_TAG_PROTO_DSA,
4693 .ptp_support = true,
4694 .ops = &mv88e6165_ops,
4695 },
4696
4697 [MV88E6171] = {
4698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4699 .family = MV88E6XXX_FAMILY_6351,
4700 .name = "Marvell 88E6171",
4701 .num_databases = 4096,
4702 .num_macs = 8192,
4703 .num_ports = 7,
4704 .num_internal_phys = 5,
4705 .max_vid = 4095,
4706 .port_base_addr = 0x10,
4707 .phy_base_addr = 0x0,
4708 .global1_addr = 0x1b,
4709 .global2_addr = 0x1c,
4710 .age_time_coeff = 15000,
4711 .g1_irqs = 9,
4712 .g2_irqs = 10,
4713 .atu_move_port_mask = 0xf,
4714 .pvt = true,
4715 .multi_chip = true,
4716 .tag_protocol = DSA_TAG_PROTO_EDSA,
4717 .ops = &mv88e6171_ops,
4718 },
4719
4720 [MV88E6172] = {
4721 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4722 .family = MV88E6XXX_FAMILY_6352,
4723 .name = "Marvell 88E6172",
4724 .num_databases = 4096,
4725 .num_macs = 8192,
4726 .num_ports = 7,
4727 .num_internal_phys = 5,
4728 .num_gpio = 15,
4729 .max_vid = 4095,
4730 .port_base_addr = 0x10,
4731 .phy_base_addr = 0x0,
4732 .global1_addr = 0x1b,
4733 .global2_addr = 0x1c,
4734 .age_time_coeff = 15000,
4735 .g1_irqs = 9,
4736 .g2_irqs = 10,
4737 .atu_move_port_mask = 0xf,
4738 .pvt = true,
4739 .multi_chip = true,
4740 .tag_protocol = DSA_TAG_PROTO_EDSA,
4741 .ops = &mv88e6172_ops,
4742 },
4743
4744 [MV88E6175] = {
4745 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4746 .family = MV88E6XXX_FAMILY_6351,
4747 .name = "Marvell 88E6175",
4748 .num_databases = 4096,
4749 .num_macs = 8192,
4750 .num_ports = 7,
4751 .num_internal_phys = 5,
4752 .max_vid = 4095,
4753 .port_base_addr = 0x10,
4754 .phy_base_addr = 0x0,
4755 .global1_addr = 0x1b,
4756 .global2_addr = 0x1c,
4757 .age_time_coeff = 15000,
4758 .g1_irqs = 9,
4759 .g2_irqs = 10,
4760 .atu_move_port_mask = 0xf,
4761 .pvt = true,
4762 .multi_chip = true,
4763 .tag_protocol = DSA_TAG_PROTO_EDSA,
4764 .ops = &mv88e6175_ops,
4765 },
4766
4767 [MV88E6176] = {
4768 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4769 .family = MV88E6XXX_FAMILY_6352,
4770 .name = "Marvell 88E6176",
4771 .num_databases = 4096,
4772 .num_macs = 8192,
4773 .num_ports = 7,
4774 .num_internal_phys = 5,
4775 .num_gpio = 15,
4776 .max_vid = 4095,
4777 .port_base_addr = 0x10,
4778 .phy_base_addr = 0x0,
4779 .global1_addr = 0x1b,
4780 .global2_addr = 0x1c,
4781 .age_time_coeff = 15000,
4782 .g1_irqs = 9,
4783 .g2_irqs = 10,
4784 .atu_move_port_mask = 0xf,
4785 .pvt = true,
4786 .multi_chip = true,
4787 .tag_protocol = DSA_TAG_PROTO_EDSA,
4788 .ops = &mv88e6176_ops,
4789 },
4790
4791 [MV88E6185] = {
4792 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4793 .family = MV88E6XXX_FAMILY_6185,
4794 .name = "Marvell 88E6185",
4795 .num_databases = 256,
4796 .num_macs = 8192,
4797 .num_ports = 10,
4798 .num_internal_phys = 0,
4799 .max_vid = 4095,
4800 .port_base_addr = 0x10,
4801 .phy_base_addr = 0x0,
4802 .global1_addr = 0x1b,
4803 .global2_addr = 0x1c,
4804 .age_time_coeff = 15000,
4805 .g1_irqs = 8,
4806 .atu_move_port_mask = 0xf,
4807 .multi_chip = true,
4808 .tag_protocol = DSA_TAG_PROTO_EDSA,
4809 .ops = &mv88e6185_ops,
4810 },
4811
4812 [MV88E6190] = {
4813 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4814 .family = MV88E6XXX_FAMILY_6390,
4815 .name = "Marvell 88E6190",
4816 .num_databases = 4096,
4817 .num_macs = 16384,
4818 .num_ports = 11, /* 10 + Z80 */
4819 .num_internal_phys = 9,
4820 .num_gpio = 16,
4821 .max_vid = 8191,
4822 .port_base_addr = 0x0,
4823 .phy_base_addr = 0x0,
4824 .global1_addr = 0x1b,
4825 .global2_addr = 0x1c,
4826 .tag_protocol = DSA_TAG_PROTO_DSA,
4827 .age_time_coeff = 3750,
4828 .g1_irqs = 9,
4829 .g2_irqs = 14,
4830 .pvt = true,
4831 .multi_chip = true,
4832 .atu_move_port_mask = 0x1f,
4833 .ops = &mv88e6190_ops,
4834 },
4835
4836 [MV88E6190X] = {
4837 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4838 .family = MV88E6XXX_FAMILY_6390,
4839 .name = "Marvell 88E6190X",
4840 .num_databases = 4096,
4841 .num_macs = 16384,
4842 .num_ports = 11, /* 10 + Z80 */
4843 .num_internal_phys = 9,
4844 .num_gpio = 16,
4845 .max_vid = 8191,
4846 .port_base_addr = 0x0,
4847 .phy_base_addr = 0x0,
4848 .global1_addr = 0x1b,
4849 .global2_addr = 0x1c,
4850 .age_time_coeff = 3750,
4851 .g1_irqs = 9,
4852 .g2_irqs = 14,
4853 .atu_move_port_mask = 0x1f,
4854 .pvt = true,
4855 .multi_chip = true,
4856 .tag_protocol = DSA_TAG_PROTO_DSA,
4857 .ops = &mv88e6190x_ops,
4858 },
4859
4860 [MV88E6191] = {
4861 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4862 .family = MV88E6XXX_FAMILY_6390,
4863 .name = "Marvell 88E6191",
4864 .num_databases = 4096,
4865 .num_macs = 16384,
4866 .num_ports = 11, /* 10 + Z80 */
4867 .num_internal_phys = 9,
4868 .max_vid = 8191,
4869 .port_base_addr = 0x0,
4870 .phy_base_addr = 0x0,
4871 .global1_addr = 0x1b,
4872 .global2_addr = 0x1c,
4873 .age_time_coeff = 3750,
4874 .g1_irqs = 9,
4875 .g2_irqs = 14,
4876 .atu_move_port_mask = 0x1f,
4877 .pvt = true,
4878 .multi_chip = true,
4879 .tag_protocol = DSA_TAG_PROTO_DSA,
4880 .ptp_support = true,
4881 .ops = &mv88e6191_ops,
4882 },
4883
4884 [MV88E6220] = {
4885 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4886 .family = MV88E6XXX_FAMILY_6250,
4887 .name = "Marvell 88E6220",
4888 .num_databases = 64,
4889
4890 /* Ports 2-4 are not routed to pins
4891 * => usable ports 0, 1, 5, 6
4892 */
4893 .num_ports = 7,
4894 .num_internal_phys = 2,
4895 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4896 .max_vid = 4095,
4897 .port_base_addr = 0x08,
4898 .phy_base_addr = 0x00,
4899 .global1_addr = 0x0f,
4900 .global2_addr = 0x07,
4901 .age_time_coeff = 15000,
4902 .g1_irqs = 9,
4903 .g2_irqs = 10,
4904 .atu_move_port_mask = 0xf,
4905 .dual_chip = true,
4906 .tag_protocol = DSA_TAG_PROTO_DSA,
4907 .ptp_support = true,
4908 .ops = &mv88e6250_ops,
4909 },
4910
4911 [MV88E6240] = {
4912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4913 .family = MV88E6XXX_FAMILY_6352,
4914 .name = "Marvell 88E6240",
4915 .num_databases = 4096,
4916 .num_macs = 8192,
4917 .num_ports = 7,
4918 .num_internal_phys = 5,
4919 .num_gpio = 15,
4920 .max_vid = 4095,
4921 .port_base_addr = 0x10,
4922 .phy_base_addr = 0x0,
4923 .global1_addr = 0x1b,
4924 .global2_addr = 0x1c,
4925 .age_time_coeff = 15000,
4926 .g1_irqs = 9,
4927 .g2_irqs = 10,
4928 .atu_move_port_mask = 0xf,
4929 .pvt = true,
4930 .multi_chip = true,
4931 .tag_protocol = DSA_TAG_PROTO_EDSA,
4932 .ptp_support = true,
4933 .ops = &mv88e6240_ops,
4934 },
4935
4936 [MV88E6250] = {
4937 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4938 .family = MV88E6XXX_FAMILY_6250,
4939 .name = "Marvell 88E6250",
4940 .num_databases = 64,
4941 .num_ports = 7,
4942 .num_internal_phys = 5,
4943 .max_vid = 4095,
4944 .port_base_addr = 0x08,
4945 .phy_base_addr = 0x00,
4946 .global1_addr = 0x0f,
4947 .global2_addr = 0x07,
4948 .age_time_coeff = 15000,
4949 .g1_irqs = 9,
4950 .g2_irqs = 10,
4951 .atu_move_port_mask = 0xf,
4952 .dual_chip = true,
4953 .tag_protocol = DSA_TAG_PROTO_DSA,
4954 .ptp_support = true,
4955 .ops = &mv88e6250_ops,
4956 },
4957
4958 [MV88E6290] = {
4959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4960 .family = MV88E6XXX_FAMILY_6390,
4961 .name = "Marvell 88E6290",
4962 .num_databases = 4096,
4963 .num_ports = 11, /* 10 + Z80 */
4964 .num_internal_phys = 9,
4965 .num_gpio = 16,
4966 .max_vid = 8191,
4967 .port_base_addr = 0x0,
4968 .phy_base_addr = 0x0,
4969 .global1_addr = 0x1b,
4970 .global2_addr = 0x1c,
4971 .age_time_coeff = 3750,
4972 .g1_irqs = 9,
4973 .g2_irqs = 14,
4974 .atu_move_port_mask = 0x1f,
4975 .pvt = true,
4976 .multi_chip = true,
4977 .tag_protocol = DSA_TAG_PROTO_DSA,
4978 .ptp_support = true,
4979 .ops = &mv88e6290_ops,
4980 },
4981
4982 [MV88E6320] = {
4983 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4984 .family = MV88E6XXX_FAMILY_6320,
4985 .name = "Marvell 88E6320",
4986 .num_databases = 4096,
4987 .num_macs = 8192,
4988 .num_ports = 7,
4989 .num_internal_phys = 5,
4990 .num_gpio = 15,
4991 .max_vid = 4095,
4992 .port_base_addr = 0x10,
4993 .phy_base_addr = 0x0,
4994 .global1_addr = 0x1b,
4995 .global2_addr = 0x1c,
4996 .age_time_coeff = 15000,
4997 .g1_irqs = 8,
4998 .g2_irqs = 10,
4999 .atu_move_port_mask = 0xf,
5000 .pvt = true,
5001 .multi_chip = true,
5002 .tag_protocol = DSA_TAG_PROTO_EDSA,
5003 .ptp_support = true,
5004 .ops = &mv88e6320_ops,
5005 },
5006
5007 [MV88E6321] = {
5008 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5009 .family = MV88E6XXX_FAMILY_6320,
5010 .name = "Marvell 88E6321",
5011 .num_databases = 4096,
5012 .num_macs = 8192,
5013 .num_ports = 7,
5014 .num_internal_phys = 5,
5015 .num_gpio = 15,
5016 .max_vid = 4095,
5017 .port_base_addr = 0x10,
5018 .phy_base_addr = 0x0,
5019 .global1_addr = 0x1b,
5020 .global2_addr = 0x1c,
5021 .age_time_coeff = 15000,
5022 .g1_irqs = 8,
5023 .g2_irqs = 10,
5024 .atu_move_port_mask = 0xf,
5025 .multi_chip = true,
5026 .tag_protocol = DSA_TAG_PROTO_EDSA,
5027 .ptp_support = true,
5028 .ops = &mv88e6321_ops,
5029 },
5030
5031 [MV88E6341] = {
5032 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5033 .family = MV88E6XXX_FAMILY_6341,
5034 .name = "Marvell 88E6341",
5035 .num_databases = 4096,
5036 .num_macs = 2048,
5037 .num_internal_phys = 5,
5038 .num_ports = 6,
5039 .num_gpio = 11,
5040 .max_vid = 4095,
5041 .port_base_addr = 0x10,
5042 .phy_base_addr = 0x10,
5043 .global1_addr = 0x1b,
5044 .global2_addr = 0x1c,
5045 .age_time_coeff = 3750,
5046 .atu_move_port_mask = 0x1f,
5047 .g1_irqs = 9,
5048 .g2_irqs = 10,
5049 .pvt = true,
5050 .multi_chip = true,
5051 .tag_protocol = DSA_TAG_PROTO_EDSA,
5052 .ptp_support = true,
5053 .ops = &mv88e6341_ops,
5054 },
5055
5056 [MV88E6350] = {
5057 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5058 .family = MV88E6XXX_FAMILY_6351,
5059 .name = "Marvell 88E6350",
5060 .num_databases = 4096,
5061 .num_macs = 8192,
5062 .num_ports = 7,
5063 .num_internal_phys = 5,
5064 .max_vid = 4095,
5065 .port_base_addr = 0x10,
5066 .phy_base_addr = 0x0,
5067 .global1_addr = 0x1b,
5068 .global2_addr = 0x1c,
5069 .age_time_coeff = 15000,
5070 .g1_irqs = 9,
5071 .g2_irqs = 10,
5072 .atu_move_port_mask = 0xf,
5073 .pvt = true,
5074 .multi_chip = true,
5075 .tag_protocol = DSA_TAG_PROTO_EDSA,
5076 .ops = &mv88e6350_ops,
5077 },
5078
5079 [MV88E6351] = {
5080 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5081 .family = MV88E6XXX_FAMILY_6351,
5082 .name = "Marvell 88E6351",
5083 .num_databases = 4096,
5084 .num_macs = 8192,
5085 .num_ports = 7,
5086 .num_internal_phys = 5,
5087 .max_vid = 4095,
5088 .port_base_addr = 0x10,
5089 .phy_base_addr = 0x0,
5090 .global1_addr = 0x1b,
5091 .global2_addr = 0x1c,
5092 .age_time_coeff = 15000,
5093 .g1_irqs = 9,
5094 .g2_irqs = 10,
5095 .atu_move_port_mask = 0xf,
5096 .pvt = true,
5097 .multi_chip = true,
5098 .tag_protocol = DSA_TAG_PROTO_EDSA,
5099 .ops = &mv88e6351_ops,
5100 },
5101
5102 [MV88E6352] = {
5103 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5104 .family = MV88E6XXX_FAMILY_6352,
5105 .name = "Marvell 88E6352",
5106 .num_databases = 4096,
5107 .num_macs = 8192,
5108 .num_ports = 7,
5109 .num_internal_phys = 5,
5110 .num_gpio = 15,
5111 .max_vid = 4095,
5112 .port_base_addr = 0x10,
5113 .phy_base_addr = 0x0,
5114 .global1_addr = 0x1b,
5115 .global2_addr = 0x1c,
5116 .age_time_coeff = 15000,
5117 .g1_irqs = 9,
5118 .g2_irqs = 10,
5119 .atu_move_port_mask = 0xf,
5120 .pvt = true,
5121 .multi_chip = true,
5122 .tag_protocol = DSA_TAG_PROTO_EDSA,
5123 .ptp_support = true,
5124 .ops = &mv88e6352_ops,
5125 },
5126 [MV88E6390] = {
5127 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5128 .family = MV88E6XXX_FAMILY_6390,
5129 .name = "Marvell 88E6390",
5130 .num_databases = 4096,
5131 .num_macs = 16384,
5132 .num_ports = 11, /* 10 + Z80 */
5133 .num_internal_phys = 9,
5134 .num_gpio = 16,
5135 .max_vid = 8191,
5136 .port_base_addr = 0x0,
5137 .phy_base_addr = 0x0,
5138 .global1_addr = 0x1b,
5139 .global2_addr = 0x1c,
5140 .age_time_coeff = 3750,
5141 .g1_irqs = 9,
5142 .g2_irqs = 14,
5143 .atu_move_port_mask = 0x1f,
5144 .pvt = true,
5145 .multi_chip = true,
5146 .tag_protocol = DSA_TAG_PROTO_DSA,
5147 .ptp_support = true,
5148 .ops = &mv88e6390_ops,
5149 },
5150 [MV88E6390X] = {
5151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5152 .family = MV88E6XXX_FAMILY_6390,
5153 .name = "Marvell 88E6390X",
5154 .num_databases = 4096,
5155 .num_macs = 16384,
5156 .num_ports = 11, /* 10 + Z80 */
5157 .num_internal_phys = 9,
5158 .num_gpio = 16,
5159 .max_vid = 8191,
5160 .port_base_addr = 0x0,
5161 .phy_base_addr = 0x0,
5162 .global1_addr = 0x1b,
5163 .global2_addr = 0x1c,
5164 .age_time_coeff = 3750,
5165 .g1_irqs = 9,
5166 .g2_irqs = 14,
5167 .atu_move_port_mask = 0x1f,
5168 .pvt = true,
5169 .multi_chip = true,
5170 .tag_protocol = DSA_TAG_PROTO_DSA,
5171 .ptp_support = true,
5172 .ops = &mv88e6390x_ops,
5173 },
5174 };
5175
mv88e6xxx_lookup_info(unsigned int prod_num)5176 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5177 {
5178 int i;
5179
5180 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5181 if (mv88e6xxx_table[i].prod_num == prod_num)
5182 return &mv88e6xxx_table[i];
5183
5184 return NULL;
5185 }
5186
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)5187 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5188 {
5189 const struct mv88e6xxx_info *info;
5190 unsigned int prod_num, rev;
5191 u16 id;
5192 int err;
5193
5194 mv88e6xxx_reg_lock(chip);
5195 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5196 mv88e6xxx_reg_unlock(chip);
5197 if (err)
5198 return err;
5199
5200 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5201 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5202
5203 info = mv88e6xxx_lookup_info(prod_num);
5204 if (!info)
5205 return -ENODEV;
5206
5207 /* Update the compatible info with the probed one */
5208 chip->info = info;
5209
5210 err = mv88e6xxx_g2_require(chip);
5211 if (err)
5212 return err;
5213
5214 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5215 chip->info->prod_num, chip->info->name, rev);
5216
5217 return 0;
5218 }
5219
mv88e6xxx_alloc_chip(struct device * dev)5220 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5221 {
5222 struct mv88e6xxx_chip *chip;
5223
5224 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5225 if (!chip)
5226 return NULL;
5227
5228 chip->dev = dev;
5229
5230 mutex_init(&chip->reg_lock);
5231 INIT_LIST_HEAD(&chip->mdios);
5232 idr_init(&chip->policies);
5233
5234 return chip;
5235 }
5236
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)5237 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5238 int port,
5239 enum dsa_tag_protocol m)
5240 {
5241 struct mv88e6xxx_chip *chip = ds->priv;
5242
5243 return chip->info->tag_protocol;
5244 }
5245
mv88e6xxx_port_mdb_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5246 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5247 const struct switchdev_obj_port_mdb *mdb)
5248 {
5249 /* We don't need any dynamic resource from the kernel (yet),
5250 * so skip the prepare phase.
5251 */
5252
5253 return 0;
5254 }
5255
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5256 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5257 const struct switchdev_obj_port_mdb *mdb)
5258 {
5259 struct mv88e6xxx_chip *chip = ds->priv;
5260
5261 mv88e6xxx_reg_lock(chip);
5262 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5263 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5264 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5265 port);
5266 mv88e6xxx_reg_unlock(chip);
5267 }
5268
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5269 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5270 const struct switchdev_obj_port_mdb *mdb)
5271 {
5272 struct mv88e6xxx_chip *chip = ds->priv;
5273 int err;
5274
5275 mv88e6xxx_reg_lock(chip);
5276 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5277 mv88e6xxx_reg_unlock(chip);
5278
5279 return err;
5280 }
5281
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)5282 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5283 struct dsa_mall_mirror_tc_entry *mirror,
5284 bool ingress)
5285 {
5286 enum mv88e6xxx_egress_direction direction = ingress ?
5287 MV88E6XXX_EGRESS_DIR_INGRESS :
5288 MV88E6XXX_EGRESS_DIR_EGRESS;
5289 struct mv88e6xxx_chip *chip = ds->priv;
5290 bool other_mirrors = false;
5291 int i;
5292 int err;
5293
5294 if (!chip->info->ops->set_egress_port)
5295 return -EOPNOTSUPP;
5296
5297 mutex_lock(&chip->reg_lock);
5298 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5299 mirror->to_local_port) {
5300 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5301 other_mirrors |= ingress ?
5302 chip->ports[i].mirror_ingress :
5303 chip->ports[i].mirror_egress;
5304
5305 /* Can't change egress port when other mirror is active */
5306 if (other_mirrors) {
5307 err = -EBUSY;
5308 goto out;
5309 }
5310
5311 err = chip->info->ops->set_egress_port(chip,
5312 direction,
5313 mirror->to_local_port);
5314 if (err)
5315 goto out;
5316 }
5317
5318 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5319 out:
5320 mutex_unlock(&chip->reg_lock);
5321
5322 return err;
5323 }
5324
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)5325 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5326 struct dsa_mall_mirror_tc_entry *mirror)
5327 {
5328 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5329 MV88E6XXX_EGRESS_DIR_INGRESS :
5330 MV88E6XXX_EGRESS_DIR_EGRESS;
5331 struct mv88e6xxx_chip *chip = ds->priv;
5332 bool other_mirrors = false;
5333 int i;
5334
5335 mutex_lock(&chip->reg_lock);
5336 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5337 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5338
5339 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5340 other_mirrors |= mirror->ingress ?
5341 chip->ports[i].mirror_ingress :
5342 chip->ports[i].mirror_egress;
5343
5344 /* Reset egress port when no other mirror is active */
5345 if (!other_mirrors) {
5346 if (chip->info->ops->set_egress_port(chip,
5347 direction,
5348 dsa_upstream_port(ds,
5349 port)))
5350 dev_err(ds->dev, "failed to set egress port\n");
5351 }
5352
5353 mutex_unlock(&chip->reg_lock);
5354 }
5355
mv88e6xxx_port_egress_floods(struct dsa_switch * ds,int port,bool unicast,bool multicast)5356 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5357 bool unicast, bool multicast)
5358 {
5359 struct mv88e6xxx_chip *chip = ds->priv;
5360 int err = -EOPNOTSUPP;
5361
5362 mv88e6xxx_reg_lock(chip);
5363 if (chip->info->ops->port_set_egress_floods)
5364 err = chip->info->ops->port_set_egress_floods(chip, port,
5365 unicast,
5366 multicast);
5367 mv88e6xxx_reg_unlock(chip);
5368
5369 return err;
5370 }
5371
5372 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5373 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
5374 .setup = mv88e6xxx_setup,
5375 .teardown = mv88e6xxx_teardown,
5376 .phylink_validate = mv88e6xxx_validate,
5377 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5378 .phylink_mac_config = mv88e6xxx_mac_config,
5379 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5380 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
5381 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
5382 .get_strings = mv88e6xxx_get_strings,
5383 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
5384 .get_sset_count = mv88e6xxx_get_sset_count,
5385 .port_enable = mv88e6xxx_port_enable,
5386 .port_disable = mv88e6xxx_port_disable,
5387 .port_max_mtu = mv88e6xxx_get_max_mtu,
5388 .port_change_mtu = mv88e6xxx_change_mtu,
5389 .get_mac_eee = mv88e6xxx_get_mac_eee,
5390 .set_mac_eee = mv88e6xxx_set_mac_eee,
5391 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
5392 .get_eeprom = mv88e6xxx_get_eeprom,
5393 .set_eeprom = mv88e6xxx_set_eeprom,
5394 .get_regs_len = mv88e6xxx_get_regs_len,
5395 .get_regs = mv88e6xxx_get_regs,
5396 .get_rxnfc = mv88e6xxx_get_rxnfc,
5397 .set_rxnfc = mv88e6xxx_set_rxnfc,
5398 .set_ageing_time = mv88e6xxx_set_ageing_time,
5399 .port_bridge_join = mv88e6xxx_port_bridge_join,
5400 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
5401 .port_egress_floods = mv88e6xxx_port_egress_floods,
5402 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
5403 .port_fast_age = mv88e6xxx_port_fast_age,
5404 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
5405 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
5406 .port_vlan_add = mv88e6xxx_port_vlan_add,
5407 .port_vlan_del = mv88e6xxx_port_vlan_del,
5408 .port_fdb_add = mv88e6xxx_port_fdb_add,
5409 .port_fdb_del = mv88e6xxx_port_fdb_del,
5410 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
5411 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
5412 .port_mdb_add = mv88e6xxx_port_mdb_add,
5413 .port_mdb_del = mv88e6xxx_port_mdb_del,
5414 .port_mirror_add = mv88e6xxx_port_mirror_add,
5415 .port_mirror_del = mv88e6xxx_port_mirror_del,
5416 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
5417 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5418 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
5419 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
5420 .port_txtstamp = mv88e6xxx_port_txtstamp,
5421 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
5422 .get_ts_info = mv88e6xxx_get_ts_info,
5423 .devlink_param_get = mv88e6xxx_devlink_param_get,
5424 .devlink_param_set = mv88e6xxx_devlink_param_set,
5425 .devlink_info_get = mv88e6xxx_devlink_info_get,
5426 };
5427
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)5428 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5429 {
5430 struct device *dev = chip->dev;
5431 struct dsa_switch *ds;
5432
5433 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5434 if (!ds)
5435 return -ENOMEM;
5436
5437 ds->dev = dev;
5438 ds->num_ports = mv88e6xxx_num_ports(chip);
5439 ds->priv = chip;
5440 ds->dev = dev;
5441 ds->ops = &mv88e6xxx_switch_ops;
5442 ds->ageing_time_min = chip->info->age_time_coeff;
5443 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5444
5445 dev_set_drvdata(dev, ds);
5446
5447 return dsa_register_switch(ds);
5448 }
5449
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)5450 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5451 {
5452 dsa_unregister_switch(chip->ds);
5453 }
5454
pdata_device_get_match_data(struct device * dev)5455 static const void *pdata_device_get_match_data(struct device *dev)
5456 {
5457 const struct of_device_id *matches = dev->driver->of_match_table;
5458 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5459
5460 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5461 matches++) {
5462 if (!strcmp(pdata->compatible, matches->compatible))
5463 return matches->data;
5464 }
5465 return NULL;
5466 }
5467
5468 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5469 * would be lost after a power cycle so prevent it to be suspended.
5470 */
mv88e6xxx_suspend(struct device * dev)5471 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5472 {
5473 return -EOPNOTSUPP;
5474 }
5475
mv88e6xxx_resume(struct device * dev)5476 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5477 {
5478 return 0;
5479 }
5480
5481 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5482
mv88e6xxx_probe(struct mdio_device * mdiodev)5483 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5484 {
5485 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5486 const struct mv88e6xxx_info *compat_info = NULL;
5487 struct device *dev = &mdiodev->dev;
5488 struct device_node *np = dev->of_node;
5489 struct mv88e6xxx_chip *chip;
5490 int port;
5491 int err;
5492
5493 if (!np && !pdata)
5494 return -EINVAL;
5495
5496 if (np)
5497 compat_info = of_device_get_match_data(dev);
5498
5499 if (pdata) {
5500 compat_info = pdata_device_get_match_data(dev);
5501
5502 if (!pdata->netdev)
5503 return -EINVAL;
5504
5505 for (port = 0; port < DSA_MAX_PORTS; port++) {
5506 if (!(pdata->enabled_ports & (1 << port)))
5507 continue;
5508 if (strcmp(pdata->cd.port_names[port], "cpu"))
5509 continue;
5510 pdata->cd.netdev[port] = &pdata->netdev->dev;
5511 break;
5512 }
5513 }
5514
5515 if (!compat_info)
5516 return -EINVAL;
5517
5518 chip = mv88e6xxx_alloc_chip(dev);
5519 if (!chip) {
5520 err = -ENOMEM;
5521 goto out;
5522 }
5523
5524 chip->info = compat_info;
5525
5526 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5527 if (err)
5528 goto out;
5529
5530 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5531 if (IS_ERR(chip->reset)) {
5532 err = PTR_ERR(chip->reset);
5533 goto out;
5534 }
5535 if (chip->reset)
5536 usleep_range(1000, 2000);
5537
5538 err = mv88e6xxx_detect(chip);
5539 if (err)
5540 goto out;
5541
5542 mv88e6xxx_phy_init(chip);
5543
5544 if (chip->info->ops->get_eeprom) {
5545 if (np)
5546 of_property_read_u32(np, "eeprom-length",
5547 &chip->eeprom_len);
5548 else
5549 chip->eeprom_len = pdata->eeprom_len;
5550 }
5551
5552 mv88e6xxx_reg_lock(chip);
5553 err = mv88e6xxx_switch_reset(chip);
5554 mv88e6xxx_reg_unlock(chip);
5555 if (err)
5556 goto out;
5557
5558 if (np) {
5559 chip->irq = of_irq_get(np, 0);
5560 if (chip->irq == -EPROBE_DEFER) {
5561 err = chip->irq;
5562 goto out;
5563 }
5564 }
5565
5566 if (pdata)
5567 chip->irq = pdata->irq;
5568
5569 /* Has to be performed before the MDIO bus is created, because
5570 * the PHYs will link their interrupts to these interrupt
5571 * controllers
5572 */
5573 mv88e6xxx_reg_lock(chip);
5574 if (chip->irq > 0)
5575 err = mv88e6xxx_g1_irq_setup(chip);
5576 else
5577 err = mv88e6xxx_irq_poll_setup(chip);
5578 mv88e6xxx_reg_unlock(chip);
5579
5580 if (err)
5581 goto out;
5582
5583 if (chip->info->g2_irqs > 0) {
5584 err = mv88e6xxx_g2_irq_setup(chip);
5585 if (err)
5586 goto out_g1_irq;
5587 }
5588
5589 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5590 if (err)
5591 goto out_g2_irq;
5592
5593 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5594 if (err)
5595 goto out_g1_atu_prob_irq;
5596
5597 err = mv88e6xxx_mdios_register(chip, np);
5598 if (err)
5599 goto out_g1_vtu_prob_irq;
5600
5601 err = mv88e6xxx_register_switch(chip);
5602 if (err)
5603 goto out_mdio;
5604
5605 return 0;
5606
5607 out_mdio:
5608 mv88e6xxx_mdios_unregister(chip);
5609 out_g1_vtu_prob_irq:
5610 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5611 out_g1_atu_prob_irq:
5612 mv88e6xxx_g1_atu_prob_irq_free(chip);
5613 out_g2_irq:
5614 if (chip->info->g2_irqs > 0)
5615 mv88e6xxx_g2_irq_free(chip);
5616 out_g1_irq:
5617 if (chip->irq > 0)
5618 mv88e6xxx_g1_irq_free(chip);
5619 else
5620 mv88e6xxx_irq_poll_free(chip);
5621 out:
5622 if (pdata)
5623 dev_put(pdata->netdev);
5624
5625 return err;
5626 }
5627
mv88e6xxx_remove(struct mdio_device * mdiodev)5628 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5629 {
5630 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5631 struct mv88e6xxx_chip *chip = ds->priv;
5632
5633 if (chip->info->ptp_support) {
5634 mv88e6xxx_hwtstamp_free(chip);
5635 mv88e6xxx_ptp_free(chip);
5636 }
5637
5638 mv88e6xxx_phy_destroy(chip);
5639 mv88e6xxx_unregister_switch(chip);
5640 mv88e6xxx_mdios_unregister(chip);
5641
5642 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5643 mv88e6xxx_g1_atu_prob_irq_free(chip);
5644
5645 if (chip->info->g2_irqs > 0)
5646 mv88e6xxx_g2_irq_free(chip);
5647
5648 if (chip->irq > 0)
5649 mv88e6xxx_g1_irq_free(chip);
5650 else
5651 mv88e6xxx_irq_poll_free(chip);
5652 }
5653
5654 static const struct of_device_id mv88e6xxx_of_match[] = {
5655 {
5656 .compatible = "marvell,mv88e6085",
5657 .data = &mv88e6xxx_table[MV88E6085],
5658 },
5659 {
5660 .compatible = "marvell,mv88e6190",
5661 .data = &mv88e6xxx_table[MV88E6190],
5662 },
5663 {
5664 .compatible = "marvell,mv88e6250",
5665 .data = &mv88e6xxx_table[MV88E6250],
5666 },
5667 { /* sentinel */ },
5668 };
5669
5670 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5671
5672 static struct mdio_driver mv88e6xxx_driver = {
5673 .probe = mv88e6xxx_probe,
5674 .remove = mv88e6xxx_remove,
5675 .mdiodrv.driver = {
5676 .name = "mv88e6085",
5677 .of_match_table = mv88e6xxx_of_match,
5678 .pm = &mv88e6xxx_pm_ops,
5679 },
5680 };
5681
5682 mdio_module_driver(mv88e6xxx_driver);
5683
5684 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5685 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5686 MODULE_LICENSE("GPL");
5687