1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
32
33 #include "nouveau_drv.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
36
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
42
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
46
47 static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49
50 /*
51 * NV10-NV40 tiling helpers
52 */
53
54 static void
nv10_bo_update_tile_region(struct drm_device * dev,struct nouveau_drm_tile * reg,u32 addr,u32 size,u32 pitch,u32 flags)55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
57 {
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
62
63 nouveau_fence_unref(®->fence);
64
65 if (tile->pitch)
66 nvkm_fb_tile_fini(fb, i, tile);
67
68 if (pitch)
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
70
71 nvkm_fb_tile_prog(fb, i, tile);
72 }
73
74 static struct nouveau_drm_tile *
nv10_bo_get_tile_region(struct drm_device * dev,int i)75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
76 {
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79
80 spin_lock(&drm->tile.lock);
81
82 if (!tile->used &&
83 (!tile->fence || nouveau_fence_done(tile->fence)))
84 tile->used = true;
85 else
86 tile = NULL;
87
88 spin_unlock(&drm->tile.lock);
89 return tile;
90 }
91
92 static void
nv10_bo_put_tile_region(struct drm_device * dev,struct nouveau_drm_tile * tile,struct dma_fence * fence)93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
95 {
96 struct nouveau_drm *drm = nouveau_drm(dev);
97
98 if (tile) {
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
101 tile->used = false;
102 spin_unlock(&drm->tile.lock);
103 }
104 }
105
106 static struct nouveau_drm_tile *
nv10_bo_set_tiling(struct drm_device * dev,u32 addr,u32 size,u32 pitch,u32 zeta)107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
109 {
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
113 int i;
114
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
117
118 if (pitch && !found) {
119 found = tile;
120 continue;
121
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
125 }
126
127 nv10_bo_put_tile_region(dev, tile, NULL);
128 }
129
130 if (found)
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
132 return found;
133 }
134
135 static void
nouveau_bo_del_ttm(struct ttm_buffer_object * bo)136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
137 {
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
141
142 WARN_ON(nvbo->pin_refcnt > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
145
146 /*
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
149 */
150 if (bo->base.dev)
151 drm_gem_object_release(&bo->base);
152
153 kfree(nvbo);
154 }
155
156 static inline u64
roundup_64(u64 x,u32 y)157 roundup_64(u64 x, u32 y)
158 {
159 x += y - 1;
160 do_div(x, y);
161 return x * y;
162 }
163
164 static void
nouveau_bo_fixup_align(struct nouveau_bo * nvbo,int * align,u64 * size)165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
166 {
167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
168 struct nvif_device *device = &drm->client.device;
169
170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
171 if (nvbo->mode) {
172 if (device->info.chipset >= 0x40) {
173 *align = 65536;
174 *size = roundup_64(*size, 64 * nvbo->mode);
175
176 } else if (device->info.chipset >= 0x30) {
177 *align = 32768;
178 *size = roundup_64(*size, 64 * nvbo->mode);
179
180 } else if (device->info.chipset >= 0x20) {
181 *align = 16384;
182 *size = roundup_64(*size, 64 * nvbo->mode);
183
184 } else if (device->info.chipset >= 0x10) {
185 *align = 16384;
186 *size = roundup_64(*size, 32 * nvbo->mode);
187 }
188 }
189 } else {
190 *size = roundup_64(*size, (1 << nvbo->page));
191 *align = max((1 << nvbo->page), *align);
192 }
193
194 *size = roundup_64(*size, PAGE_SIZE);
195 }
196
197 struct nouveau_bo *
nouveau_bo_alloc(struct nouveau_cli * cli,u64 * size,int * align,u32 domain,u32 tile_mode,u32 tile_flags)198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
199 u32 tile_mode, u32 tile_flags)
200 {
201 struct nouveau_drm *drm = cli->drm;
202 struct nouveau_bo *nvbo;
203 struct nvif_mmu *mmu = &cli->mmu;
204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
205 int i, pi = -1;
206
207 if (!*size) {
208 NV_WARN(drm, "skipped size %016llx\n", *size);
209 return ERR_PTR(-EINVAL);
210 }
211
212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
213 if (!nvbo)
214 return ERR_PTR(-ENOMEM);
215 INIT_LIST_HEAD(&nvbo->head);
216 INIT_LIST_HEAD(&nvbo->entry);
217 INIT_LIST_HEAD(&nvbo->vma_list);
218 nvbo->bo.bdev = &drm->ttm.bdev;
219
220 /* This is confusing, and doesn't actually mean we want an uncached
221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
222 * into in nouveau_gem_new().
223 */
224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
225 /* Determine if we can get a cache-coherent map, forcing
226 * uncached mapping if we can't.
227 */
228 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
229 nvbo->force_coherent = true;
230 }
231
232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
235 kfree(nvbo);
236 return ERR_PTR(-EINVAL);
237 }
238
239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
240 } else
241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
242 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
243 nvbo->comp = (tile_flags & 0x00030000) >> 16;
244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
245 kfree(nvbo);
246 return ERR_PTR(-EINVAL);
247 }
248 } else {
249 nvbo->zeta = (tile_flags & 0x00000007);
250 }
251 nvbo->mode = tile_mode;
252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
253
254 /* Determine the desirable target GPU page size for the buffer. */
255 for (i = 0; i < vmm->page_nr; i++) {
256 /* Because we cannot currently allow VMM maps to fail
257 * during buffer migration, we need to determine page
258 * size for the buffer up-front, and pre-allocate its
259 * page tables.
260 *
261 * Skip page sizes that can't support needed domains.
262 */
263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
265 continue;
266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
268 continue;
269
270 /* Select this page size if it's the first that supports
271 * the potential memory domains, or when it's compatible
272 * with the requested compression settings.
273 */
274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
275 pi = i;
276
277 /* Stop once the buffer is larger than the current page size. */
278 if (*size >= 1ULL << vmm->page[i].shift)
279 break;
280 }
281
282 if (WARN_ON(pi < 0)) {
283 kfree(nvbo);
284 return ERR_PTR(-EINVAL);
285 }
286
287 /* Disable compression if suitable settings couldn't be found. */
288 if (nvbo->comp && !vmm->page[pi].comp) {
289 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
290 nvbo->kind = mmu->kind[nvbo->kind];
291 nvbo->comp = 0;
292 }
293 nvbo->page = vmm->page[pi].shift;
294
295 nouveau_bo_fixup_align(nvbo, align, size);
296
297 return nvbo;
298 }
299
300 int
nouveau_bo_init(struct nouveau_bo * nvbo,u64 size,int align,u32 domain,struct sg_table * sg,struct dma_resv * robj)301 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
302 struct sg_table *sg, struct dma_resv *robj)
303 {
304 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
305 size_t acc_size;
306 int ret;
307
308 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
309
310 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
311 nouveau_bo_placement_set(nvbo, domain, 0);
312 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
313
314 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
315 &nvbo->placement, align >> PAGE_SHIFT, false,
316 acc_size, sg, robj, nouveau_bo_del_ttm);
317 if (ret) {
318 /* ttm will call nouveau_bo_del_ttm if it fails.. */
319 return ret;
320 }
321
322 return 0;
323 }
324
325 int
nouveau_bo_new(struct nouveau_cli * cli,u64 size,int align,uint32_t domain,uint32_t tile_mode,uint32_t tile_flags,struct sg_table * sg,struct dma_resv * robj,struct nouveau_bo ** pnvbo)326 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
327 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
328 struct sg_table *sg, struct dma_resv *robj,
329 struct nouveau_bo **pnvbo)
330 {
331 struct nouveau_bo *nvbo;
332 int ret;
333
334 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
335 tile_flags);
336 if (IS_ERR(nvbo))
337 return PTR_ERR(nvbo);
338
339 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
340 if (ret)
341 return ret;
342
343 *pnvbo = nvbo;
344 return 0;
345 }
346
347 static void
set_placement_list(struct nouveau_drm * drm,struct ttm_place * pl,unsigned * n,uint32_t domain,uint32_t flags)348 set_placement_list(struct nouveau_drm *drm, struct ttm_place *pl, unsigned *n,
349 uint32_t domain, uint32_t flags)
350 {
351 *n = 0;
352
353 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
354 struct nvif_mmu *mmu = &drm->client.mmu;
355
356 pl[*n].mem_type = TTM_PL_VRAM;
357 pl[*n].flags = flags & ~TTM_PL_FLAG_CACHED;
358
359 /* Some BARs do not support being ioremapped WC */
360 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
361 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
362 pl[*n].flags &= ~TTM_PL_FLAG_WC;
363
364 (*n)++;
365 }
366 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
367 pl[*n].mem_type = TTM_PL_TT;
368 pl[*n].flags = flags;
369
370 if (drm->agp.bridge)
371 pl[*n].flags &= ~TTM_PL_FLAG_CACHED;
372
373 (*n)++;
374 }
375 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
376 pl[*n].mem_type = TTM_PL_SYSTEM;
377 pl[(*n)++].flags = flags;
378 }
379 }
380
381 static void
set_placement_range(struct nouveau_bo * nvbo,uint32_t domain)382 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
383 {
384 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
385 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
386 unsigned i, fpfn, lpfn;
387
388 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
389 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
390 nvbo->bo.mem.num_pages < vram_pages / 4) {
391 /*
392 * Make sure that the color and depth buffers are handled
393 * by independent memory controller units. Up to a 9x
394 * speed up when alpha-blending and depth-test are enabled
395 * at the same time.
396 */
397 if (nvbo->zeta) {
398 fpfn = vram_pages / 2;
399 lpfn = ~0;
400 } else {
401 fpfn = 0;
402 lpfn = vram_pages / 2;
403 }
404 for (i = 0; i < nvbo->placement.num_placement; ++i) {
405 nvbo->placements[i].fpfn = fpfn;
406 nvbo->placements[i].lpfn = lpfn;
407 }
408 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
409 nvbo->busy_placements[i].fpfn = fpfn;
410 nvbo->busy_placements[i].lpfn = lpfn;
411 }
412 }
413 }
414
415 void
nouveau_bo_placement_set(struct nouveau_bo * nvbo,uint32_t domain,uint32_t busy)416 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
417 uint32_t busy)
418 {
419 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
420 struct ttm_placement *pl = &nvbo->placement;
421 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
422 TTM_PL_MASK_CACHING) |
423 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
424
425 pl->placement = nvbo->placements;
426 set_placement_list(drm, nvbo->placements, &pl->num_placement,
427 domain, flags);
428
429 pl->busy_placement = nvbo->busy_placements;
430 set_placement_list(drm, nvbo->busy_placements, &pl->num_busy_placement,
431 domain | busy, flags);
432
433 set_placement_range(nvbo, domain);
434 }
435
436 int
nouveau_bo_pin(struct nouveau_bo * nvbo,uint32_t domain,bool contig)437 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
438 {
439 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
440 struct ttm_buffer_object *bo = &nvbo->bo;
441 bool force = false, evict = false;
442 int ret;
443
444 ret = ttm_bo_reserve(bo, false, false, NULL);
445 if (ret)
446 return ret;
447
448 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
449 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
450 if (!nvbo->contig) {
451 nvbo->contig = true;
452 force = true;
453 evict = true;
454 }
455 }
456
457 if (nvbo->pin_refcnt) {
458 bool error = evict;
459
460 switch (bo->mem.mem_type) {
461 case TTM_PL_VRAM:
462 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
463 break;
464 case TTM_PL_TT:
465 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
466 default:
467 break;
468 }
469
470 if (error) {
471 NV_ERROR(drm, "bo %p pinned elsewhere: "
472 "0x%08x vs 0x%08x\n", bo,
473 bo->mem.mem_type, domain);
474 ret = -EBUSY;
475 }
476 nvbo->pin_refcnt++;
477 goto out;
478 }
479
480 if (evict) {
481 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
482 ret = nouveau_bo_validate(nvbo, false, false);
483 if (ret)
484 goto out;
485 }
486
487 nvbo->pin_refcnt++;
488 nouveau_bo_placement_set(nvbo, domain, 0);
489
490 /* drop pin_refcnt temporarily, so we don't trip the assertion
491 * in nouveau_bo_move() that makes sure we're not trying to
492 * move a pinned buffer
493 */
494 nvbo->pin_refcnt--;
495 ret = nouveau_bo_validate(nvbo, false, false);
496 if (ret)
497 goto out;
498 nvbo->pin_refcnt++;
499
500 switch (bo->mem.mem_type) {
501 case TTM_PL_VRAM:
502 drm->gem.vram_available -= bo->mem.size;
503 break;
504 case TTM_PL_TT:
505 drm->gem.gart_available -= bo->mem.size;
506 break;
507 default:
508 break;
509 }
510
511 out:
512 if (force && ret)
513 nvbo->contig = false;
514 ttm_bo_unreserve(bo);
515 return ret;
516 }
517
518 int
nouveau_bo_unpin(struct nouveau_bo * nvbo)519 nouveau_bo_unpin(struct nouveau_bo *nvbo)
520 {
521 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
522 struct ttm_buffer_object *bo = &nvbo->bo;
523 int ret, ref;
524
525 ret = ttm_bo_reserve(bo, false, false, NULL);
526 if (ret)
527 return ret;
528
529 ref = --nvbo->pin_refcnt;
530 WARN_ON_ONCE(ref < 0);
531 if (ref)
532 goto out;
533
534 switch (bo->mem.mem_type) {
535 case TTM_PL_VRAM:
536 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
537 break;
538 case TTM_PL_TT:
539 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
540 break;
541 default:
542 break;
543 }
544
545 ret = nouveau_bo_validate(nvbo, false, false);
546 if (ret == 0) {
547 switch (bo->mem.mem_type) {
548 case TTM_PL_VRAM:
549 drm->gem.vram_available += bo->mem.size;
550 break;
551 case TTM_PL_TT:
552 drm->gem.gart_available += bo->mem.size;
553 break;
554 default:
555 break;
556 }
557 }
558
559 out:
560 ttm_bo_unreserve(bo);
561 return ret;
562 }
563
564 int
nouveau_bo_map(struct nouveau_bo * nvbo)565 nouveau_bo_map(struct nouveau_bo *nvbo)
566 {
567 int ret;
568
569 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
570 if (ret)
571 return ret;
572
573 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
574
575 ttm_bo_unreserve(&nvbo->bo);
576 return ret;
577 }
578
579 void
nouveau_bo_unmap(struct nouveau_bo * nvbo)580 nouveau_bo_unmap(struct nouveau_bo *nvbo)
581 {
582 if (!nvbo)
583 return;
584
585 ttm_bo_kunmap(&nvbo->kmap);
586 }
587
588 void
nouveau_bo_sync_for_device(struct nouveau_bo * nvbo)589 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
590 {
591 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
592 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
593 int i;
594
595 if (!ttm_dma || !ttm_dma->dma_address)
596 return;
597
598 /* Don't waste time looping if the object is coherent */
599 if (nvbo->force_coherent)
600 return;
601
602 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
603 dma_sync_single_for_device(drm->dev->dev,
604 ttm_dma->dma_address[i],
605 PAGE_SIZE, DMA_TO_DEVICE);
606 }
607
608 void
nouveau_bo_sync_for_cpu(struct nouveau_bo * nvbo)609 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
610 {
611 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
612 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
613 int i;
614
615 if (!ttm_dma || !ttm_dma->dma_address)
616 return;
617
618 /* Don't waste time looping if the object is coherent */
619 if (nvbo->force_coherent)
620 return;
621
622 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
623 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
624 PAGE_SIZE, DMA_FROM_DEVICE);
625 }
626
nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object * bo)627 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
628 {
629 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
630 struct nouveau_bo *nvbo = nouveau_bo(bo);
631
632 mutex_lock(&drm->ttm.io_reserve_mutex);
633 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
634 mutex_unlock(&drm->ttm.io_reserve_mutex);
635 }
636
nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object * bo)637 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
638 {
639 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
640 struct nouveau_bo *nvbo = nouveau_bo(bo);
641
642 mutex_lock(&drm->ttm.io_reserve_mutex);
643 list_del_init(&nvbo->io_reserve_lru);
644 mutex_unlock(&drm->ttm.io_reserve_mutex);
645 }
646
647 int
nouveau_bo_validate(struct nouveau_bo * nvbo,bool interruptible,bool no_wait_gpu)648 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
649 bool no_wait_gpu)
650 {
651 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
652 int ret;
653
654 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
655 if (ret)
656 return ret;
657
658 nouveau_bo_sync_for_device(nvbo);
659
660 return 0;
661 }
662
663 void
nouveau_bo_wr16(struct nouveau_bo * nvbo,unsigned index,u16 val)664 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
665 {
666 bool is_iomem;
667 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
668
669 mem += index;
670
671 if (is_iomem)
672 iowrite16_native(val, (void __force __iomem *)mem);
673 else
674 *mem = val;
675 }
676
677 u32
nouveau_bo_rd32(struct nouveau_bo * nvbo,unsigned index)678 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
679 {
680 bool is_iomem;
681 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
682
683 mem += index;
684
685 if (is_iomem)
686 return ioread32_native((void __force __iomem *)mem);
687 else
688 return *mem;
689 }
690
691 void
nouveau_bo_wr32(struct nouveau_bo * nvbo,unsigned index,u32 val)692 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
693 {
694 bool is_iomem;
695 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
696
697 mem += index;
698
699 if (is_iomem)
700 iowrite32_native(val, (void __force __iomem *)mem);
701 else
702 *mem = val;
703 }
704
705 static struct ttm_tt *
nouveau_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)706 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
707 {
708 #if IS_ENABLED(CONFIG_AGP)
709 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
710
711 if (drm->agp.bridge) {
712 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
713 }
714 #endif
715
716 return nouveau_sgdma_create_ttm(bo, page_flags);
717 }
718
719 static int
nouveau_ttm_tt_bind(struct ttm_bo_device * bdev,struct ttm_tt * ttm,struct ttm_resource * reg)720 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
721 struct ttm_resource *reg)
722 {
723 #if IS_ENABLED(CONFIG_AGP)
724 struct nouveau_drm *drm = nouveau_bdev(bdev);
725 #endif
726 if (!reg)
727 return -EINVAL;
728 #if IS_ENABLED(CONFIG_AGP)
729 if (drm->agp.bridge)
730 return ttm_agp_bind(ttm, reg);
731 #endif
732 return nouveau_sgdma_bind(bdev, ttm, reg);
733 }
734
735 static void
nouveau_ttm_tt_unbind(struct ttm_bo_device * bdev,struct ttm_tt * ttm)736 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
737 {
738 #if IS_ENABLED(CONFIG_AGP)
739 struct nouveau_drm *drm = nouveau_bdev(bdev);
740
741 if (drm->agp.bridge) {
742 ttm_agp_unbind(ttm);
743 return;
744 }
745 #endif
746 nouveau_sgdma_unbind(bdev, ttm);
747 }
748
749 static void
nouveau_bo_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * pl)750 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
751 {
752 struct nouveau_bo *nvbo = nouveau_bo(bo);
753
754 switch (bo->mem.mem_type) {
755 case TTM_PL_VRAM:
756 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
757 NOUVEAU_GEM_DOMAIN_CPU);
758 break;
759 default:
760 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
761 break;
762 }
763
764 *pl = nvbo->placement;
765 }
766
767 static int
nouveau_bo_move_prep(struct nouveau_drm * drm,struct ttm_buffer_object * bo,struct ttm_resource * reg)768 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
769 struct ttm_resource *reg)
770 {
771 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
772 struct nouveau_mem *new_mem = nouveau_mem(reg);
773 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
774 int ret;
775
776 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
777 old_mem->mem.size, &old_mem->vma[0]);
778 if (ret)
779 return ret;
780
781 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
782 new_mem->mem.size, &old_mem->vma[1]);
783 if (ret)
784 goto done;
785
786 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
787 if (ret)
788 goto done;
789
790 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
791 done:
792 if (ret) {
793 nvif_vmm_put(vmm, &old_mem->vma[1]);
794 nvif_vmm_put(vmm, &old_mem->vma[0]);
795 }
796 return 0;
797 }
798
799 static int
nouveau_bo_move_m2mf(struct ttm_buffer_object * bo,int evict,bool intr,bool no_wait_gpu,struct ttm_resource * new_reg)800 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
801 bool no_wait_gpu, struct ttm_resource *new_reg)
802 {
803 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
804 struct nouveau_channel *chan = drm->ttm.chan;
805 struct nouveau_cli *cli = (void *)chan->user.client;
806 struct nouveau_fence *fence;
807 int ret;
808
809 /* create temporary vmas for the transfer and attach them to the
810 * old nvkm_mem node, these will get cleaned up after ttm has
811 * destroyed the ttm_resource
812 */
813 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
814 ret = nouveau_bo_move_prep(drm, bo, new_reg);
815 if (ret)
816 return ret;
817 }
818
819 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
820 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
821 if (ret == 0) {
822 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
823 if (ret == 0) {
824 ret = nouveau_fence_new(chan, false, &fence);
825 if (ret == 0) {
826 ret = ttm_bo_move_accel_cleanup(bo,
827 &fence->base,
828 evict, false,
829 new_reg);
830 nouveau_fence_unref(&fence);
831 }
832 }
833 }
834 mutex_unlock(&cli->mutex);
835 return ret;
836 }
837
838 void
nouveau_bo_move_init(struct nouveau_drm * drm)839 nouveau_bo_move_init(struct nouveau_drm *drm)
840 {
841 static const struct _method_table {
842 const char *name;
843 int engine;
844 s32 oclass;
845 int (*exec)(struct nouveau_channel *,
846 struct ttm_buffer_object *,
847 struct ttm_resource *, struct ttm_resource *);
848 int (*init)(struct nouveau_channel *, u32 handle);
849 } _methods[] = {
850 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
851 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
853 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
855 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
856 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
857 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
858 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
859 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
861 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
862 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
863 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
864 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
865 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
866 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
867 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
868 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
869 {},
870 };
871 const struct _method_table *mthd = _methods;
872 const char *name = "CPU";
873 int ret;
874
875 do {
876 struct nouveau_channel *chan;
877
878 if (mthd->engine)
879 chan = drm->cechan;
880 else
881 chan = drm->channel;
882 if (chan == NULL)
883 continue;
884
885 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
886 mthd->oclass | (mthd->engine << 16),
887 mthd->oclass, NULL, 0,
888 &drm->ttm.copy);
889 if (ret == 0) {
890 ret = mthd->init(chan, drm->ttm.copy.handle);
891 if (ret) {
892 nvif_object_dtor(&drm->ttm.copy);
893 continue;
894 }
895
896 drm->ttm.move = mthd->exec;
897 drm->ttm.chan = chan;
898 name = mthd->name;
899 break;
900 }
901 } while ((++mthd)->exec);
902
903 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
904 }
905
906 static int
nouveau_bo_move_flipd(struct ttm_buffer_object * bo,bool evict,bool intr,bool no_wait_gpu,struct ttm_resource * new_reg)907 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
908 bool no_wait_gpu, struct ttm_resource *new_reg)
909 {
910 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
911 struct ttm_place placement_memtype = {
912 .fpfn = 0,
913 .lpfn = 0,
914 .mem_type = TTM_PL_TT,
915 .flags = TTM_PL_MASK_CACHING
916 };
917 struct ttm_placement placement;
918 struct ttm_resource tmp_reg;
919 int ret;
920
921 placement.num_placement = placement.num_busy_placement = 1;
922 placement.placement = placement.busy_placement = &placement_memtype;
923
924 tmp_reg = *new_reg;
925 tmp_reg.mm_node = NULL;
926 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
927 if (ret)
928 return ret;
929
930 ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
931 if (ret)
932 goto out;
933
934 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_reg);
935 if (ret)
936 goto out;
937
938 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
939 if (ret)
940 goto out;
941
942 ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
943 out:
944 ttm_resource_free(bo, &tmp_reg);
945 return ret;
946 }
947
948 static int
nouveau_bo_move_flips(struct ttm_buffer_object * bo,bool evict,bool intr,bool no_wait_gpu,struct ttm_resource * new_reg)949 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
950 bool no_wait_gpu, struct ttm_resource *new_reg)
951 {
952 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
953 struct ttm_place placement_memtype = {
954 .fpfn = 0,
955 .lpfn = 0,
956 .mem_type = TTM_PL_TT,
957 .flags = TTM_PL_MASK_CACHING
958 };
959 struct ttm_placement placement;
960 struct ttm_resource tmp_reg;
961 int ret;
962
963 placement.num_placement = placement.num_busy_placement = 1;
964 placement.placement = placement.busy_placement = &placement_memtype;
965
966 tmp_reg = *new_reg;
967 tmp_reg.mm_node = NULL;
968 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
969 if (ret)
970 return ret;
971
972 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
973 if (ret)
974 goto out;
975
976 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
977 if (ret)
978 goto out;
979
980 out:
981 ttm_resource_free(bo, &tmp_reg);
982 return ret;
983 }
984
985 static void
nouveau_bo_move_ntfy(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_reg)986 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
987 struct ttm_resource *new_reg)
988 {
989 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
990 struct nouveau_bo *nvbo = nouveau_bo(bo);
991 struct nouveau_vma *vma;
992
993 /* ttm can now (stupidly) pass the driver bos it didn't create... */
994 if (bo->destroy != nouveau_bo_del_ttm)
995 return;
996
997 nouveau_bo_del_io_reserve_lru(bo);
998
999 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
1000 mem->mem.page == nvbo->page) {
1001 list_for_each_entry(vma, &nvbo->vma_list, head) {
1002 nouveau_vma_map(vma, mem);
1003 }
1004 } else {
1005 list_for_each_entry(vma, &nvbo->vma_list, head) {
1006 WARN_ON(ttm_bo_wait(bo, false, false));
1007 nouveau_vma_unmap(vma);
1008 }
1009 }
1010
1011 if (new_reg) {
1012 if (new_reg->mm_node)
1013 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1014 else
1015 nvbo->offset = 0;
1016 }
1017
1018 }
1019
1020 static int
nouveau_bo_vm_bind(struct ttm_buffer_object * bo,struct ttm_resource * new_reg,struct nouveau_drm_tile ** new_tile)1021 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1022 struct nouveau_drm_tile **new_tile)
1023 {
1024 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1025 struct drm_device *dev = drm->dev;
1026 struct nouveau_bo *nvbo = nouveau_bo(bo);
1027 u64 offset = new_reg->start << PAGE_SHIFT;
1028
1029 *new_tile = NULL;
1030 if (new_reg->mem_type != TTM_PL_VRAM)
1031 return 0;
1032
1033 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1034 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1035 nvbo->mode, nvbo->zeta);
1036 }
1037
1038 return 0;
1039 }
1040
1041 static void
nouveau_bo_vm_cleanup(struct ttm_buffer_object * bo,struct nouveau_drm_tile * new_tile,struct nouveau_drm_tile ** old_tile)1042 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1043 struct nouveau_drm_tile *new_tile,
1044 struct nouveau_drm_tile **old_tile)
1045 {
1046 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1047 struct drm_device *dev = drm->dev;
1048 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1049
1050 nv10_bo_put_tile_region(dev, *old_tile, fence);
1051 *old_tile = new_tile;
1052 }
1053
1054 static int
nouveau_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_reg)1055 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1056 struct ttm_operation_ctx *ctx,
1057 struct ttm_resource *new_reg)
1058 {
1059 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1060 struct nouveau_bo *nvbo = nouveau_bo(bo);
1061 struct ttm_resource *old_reg = &bo->mem;
1062 struct nouveau_drm_tile *new_tile = NULL;
1063 int ret = 0;
1064
1065 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1066 if (ret)
1067 return ret;
1068
1069 if (nvbo->pin_refcnt)
1070 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1071
1072 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1073 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1074 if (ret)
1075 return ret;
1076 }
1077
1078 /* Fake bo copy. */
1079 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1080 ttm_bo_move_null(bo, new_reg);
1081 goto out;
1082 }
1083
1084 /* Hardware assisted copy. */
1085 if (drm->ttm.move) {
1086 if (new_reg->mem_type == TTM_PL_SYSTEM)
1087 ret = nouveau_bo_move_flipd(bo, evict,
1088 ctx->interruptible,
1089 ctx->no_wait_gpu, new_reg);
1090 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1091 ret = nouveau_bo_move_flips(bo, evict,
1092 ctx->interruptible,
1093 ctx->no_wait_gpu, new_reg);
1094 else
1095 ret = nouveau_bo_move_m2mf(bo, evict,
1096 ctx->interruptible,
1097 ctx->no_wait_gpu, new_reg);
1098 if (!ret)
1099 goto out;
1100 }
1101
1102 /* Fallback to software copy. */
1103 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1104 if (ret == 0)
1105 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1106
1107 out:
1108 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1109 if (ret)
1110 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1111 else
1112 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1113 }
1114
1115 return ret;
1116 }
1117
1118 static int
nouveau_bo_verify_access(struct ttm_buffer_object * bo,struct file * filp)1119 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1120 {
1121 struct nouveau_bo *nvbo = nouveau_bo(bo);
1122
1123 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1124 filp->private_data);
1125 }
1126
1127 static void
nouveau_ttm_io_mem_free_locked(struct nouveau_drm * drm,struct ttm_resource * reg)1128 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1129 struct ttm_resource *reg)
1130 {
1131 struct nouveau_mem *mem = nouveau_mem(reg);
1132
1133 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1134 switch (reg->mem_type) {
1135 case TTM_PL_TT:
1136 if (mem->kind)
1137 nvif_object_unmap_handle(&mem->mem.object);
1138 break;
1139 case TTM_PL_VRAM:
1140 nvif_object_unmap_handle(&mem->mem.object);
1141 break;
1142 default:
1143 break;
1144 }
1145 }
1146 }
1147
1148 static int
nouveau_ttm_io_mem_reserve(struct ttm_bo_device * bdev,struct ttm_resource * reg)1149 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1150 {
1151 struct nouveau_drm *drm = nouveau_bdev(bdev);
1152 struct nvkm_device *device = nvxx_device(&drm->client.device);
1153 struct nouveau_mem *mem = nouveau_mem(reg);
1154 int ret;
1155
1156 mutex_lock(&drm->ttm.io_reserve_mutex);
1157 retry:
1158 switch (reg->mem_type) {
1159 case TTM_PL_SYSTEM:
1160 /* System memory */
1161 ret = 0;
1162 goto out;
1163 case TTM_PL_TT:
1164 #if IS_ENABLED(CONFIG_AGP)
1165 if (drm->agp.bridge) {
1166 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1167 drm->agp.base;
1168 reg->bus.is_iomem = !drm->agp.cma;
1169 }
1170 #endif
1171 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1172 !mem->kind) {
1173 /* untiled */
1174 ret = 0;
1175 break;
1176 }
1177 fallthrough; /* tiled memory */
1178 case TTM_PL_VRAM:
1179 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1180 device->func->resource_addr(device, 1);
1181 reg->bus.is_iomem = true;
1182 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1183 union {
1184 struct nv50_mem_map_v0 nv50;
1185 struct gf100_mem_map_v0 gf100;
1186 } args;
1187 u64 handle, length;
1188 u32 argc = 0;
1189
1190 switch (mem->mem.object.oclass) {
1191 case NVIF_CLASS_MEM_NV50:
1192 args.nv50.version = 0;
1193 args.nv50.ro = 0;
1194 args.nv50.kind = mem->kind;
1195 args.nv50.comp = mem->comp;
1196 argc = sizeof(args.nv50);
1197 break;
1198 case NVIF_CLASS_MEM_GF100:
1199 args.gf100.version = 0;
1200 args.gf100.ro = 0;
1201 args.gf100.kind = mem->kind;
1202 argc = sizeof(args.gf100);
1203 break;
1204 default:
1205 WARN_ON(1);
1206 break;
1207 }
1208
1209 ret = nvif_object_map_handle(&mem->mem.object,
1210 &args, argc,
1211 &handle, &length);
1212 if (ret != 1) {
1213 if (WARN_ON(ret == 0))
1214 ret = -EINVAL;
1215 goto out;
1216 }
1217
1218 reg->bus.offset = handle;
1219 }
1220 ret = 0;
1221 break;
1222 default:
1223 ret = -EINVAL;
1224 }
1225
1226 out:
1227 if (ret == -ENOSPC) {
1228 struct nouveau_bo *nvbo;
1229
1230 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1231 typeof(*nvbo),
1232 io_reserve_lru);
1233 if (nvbo) {
1234 list_del_init(&nvbo->io_reserve_lru);
1235 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1236 bdev->dev_mapping);
1237 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1238 goto retry;
1239 }
1240
1241 }
1242 mutex_unlock(&drm->ttm.io_reserve_mutex);
1243 return ret;
1244 }
1245
1246 static void
nouveau_ttm_io_mem_free(struct ttm_bo_device * bdev,struct ttm_resource * reg)1247 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1248 {
1249 struct nouveau_drm *drm = nouveau_bdev(bdev);
1250
1251 mutex_lock(&drm->ttm.io_reserve_mutex);
1252 nouveau_ttm_io_mem_free_locked(drm, reg);
1253 mutex_unlock(&drm->ttm.io_reserve_mutex);
1254 }
1255
1256 static int
nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object * bo)1257 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1258 {
1259 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1260 struct nouveau_bo *nvbo = nouveau_bo(bo);
1261 struct nvkm_device *device = nvxx_device(&drm->client.device);
1262 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1263 int i, ret;
1264
1265 /* as long as the bo isn't in vram, and isn't tiled, we've got
1266 * nothing to do here.
1267 */
1268 if (bo->mem.mem_type != TTM_PL_VRAM) {
1269 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1270 !nvbo->kind)
1271 return 0;
1272
1273 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1274 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
1275 0);
1276
1277 ret = nouveau_bo_validate(nvbo, false, false);
1278 if (ret)
1279 return ret;
1280 }
1281 return 0;
1282 }
1283
1284 /* make sure bo is in mappable vram */
1285 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1286 bo->mem.start + bo->mem.num_pages < mappable)
1287 return 0;
1288
1289 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1290 nvbo->placements[i].fpfn = 0;
1291 nvbo->placements[i].lpfn = mappable;
1292 }
1293
1294 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1295 nvbo->busy_placements[i].fpfn = 0;
1296 nvbo->busy_placements[i].lpfn = mappable;
1297 }
1298
1299 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1300 return nouveau_bo_validate(nvbo, false, false);
1301 }
1302
1303 static int
nouveau_ttm_tt_populate(struct ttm_bo_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)1304 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
1305 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1306 {
1307 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1308 struct nouveau_drm *drm;
1309 struct device *dev;
1310 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1311
1312 if (ttm_tt_is_populated(ttm))
1313 return 0;
1314
1315 if (slave && ttm->sg) {
1316 /* make userspace faulting work */
1317 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1318 ttm_dma->dma_address, ttm->num_pages);
1319 ttm_tt_set_populated(ttm);
1320 return 0;
1321 }
1322
1323 drm = nouveau_bdev(bdev);
1324 dev = drm->dev->dev;
1325
1326 #if IS_ENABLED(CONFIG_AGP)
1327 if (drm->agp.bridge) {
1328 return ttm_pool_populate(ttm, ctx);
1329 }
1330 #endif
1331
1332 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1333 if (swiotlb_nr_tbl()) {
1334 return ttm_dma_populate((void *)ttm, dev, ctx);
1335 }
1336 #endif
1337 return ttm_populate_and_map_pages(dev, ttm_dma, ctx);
1338 }
1339
1340 static void
nouveau_ttm_tt_unpopulate(struct ttm_bo_device * bdev,struct ttm_tt * ttm)1341 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1342 struct ttm_tt *ttm)
1343 {
1344 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1345 struct nouveau_drm *drm;
1346 struct device *dev;
1347 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1348
1349 if (slave)
1350 return;
1351
1352 drm = nouveau_bdev(bdev);
1353 dev = drm->dev->dev;
1354
1355 #if IS_ENABLED(CONFIG_AGP)
1356 if (drm->agp.bridge) {
1357 ttm_pool_unpopulate(ttm);
1358 return;
1359 }
1360 #endif
1361
1362 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1363 if (swiotlb_nr_tbl()) {
1364 ttm_dma_unpopulate((void *)ttm, dev);
1365 return;
1366 }
1367 #endif
1368
1369 ttm_unmap_and_unpopulate_pages(dev, ttm_dma);
1370 }
1371
1372 static void
nouveau_ttm_tt_destroy(struct ttm_bo_device * bdev,struct ttm_tt * ttm)1373 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
1374 struct ttm_tt *ttm)
1375 {
1376 #if IS_ENABLED(CONFIG_AGP)
1377 struct nouveau_drm *drm = nouveau_bdev(bdev);
1378 if (drm->agp.bridge) {
1379 ttm_agp_unbind(ttm);
1380 ttm_tt_destroy_common(bdev, ttm);
1381 ttm_agp_destroy(ttm);
1382 return;
1383 }
1384 #endif
1385 nouveau_sgdma_destroy(bdev, ttm);
1386 }
1387
1388 void
nouveau_bo_fence(struct nouveau_bo * nvbo,struct nouveau_fence * fence,bool exclusive)1389 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1390 {
1391 struct dma_resv *resv = nvbo->bo.base.resv;
1392
1393 if (exclusive)
1394 dma_resv_add_excl_fence(resv, &fence->base);
1395 else if (fence)
1396 dma_resv_add_shared_fence(resv, &fence->base);
1397 }
1398
1399 struct ttm_bo_driver nouveau_bo_driver = {
1400 .ttm_tt_create = &nouveau_ttm_tt_create,
1401 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1402 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1403 .ttm_tt_bind = &nouveau_ttm_tt_bind,
1404 .ttm_tt_unbind = &nouveau_ttm_tt_unbind,
1405 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1406 .eviction_valuable = ttm_bo_eviction_valuable,
1407 .evict_flags = nouveau_bo_evict_flags,
1408 .move_notify = nouveau_bo_move_ntfy,
1409 .move = nouveau_bo_move,
1410 .verify_access = nouveau_bo_verify_access,
1411 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1412 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1413 .io_mem_free = &nouveau_ttm_io_mem_free,
1414 };
1415