1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/vga_switcheroo.h>
31 #include <linux/mmu_notifier.h>
32
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_ioctl.h>
35 #include <drm/drm_vblank.h>
36
37 #include <core/gpuobj.h>
38 #include <core/option.h>
39 #include <core/pci.h>
40 #include <core/tegra.h>
41
42 #include <nvif/driver.h>
43 #include <nvif/fifo.h>
44 #include <nvif/push006c.h>
45 #include <nvif/user.h>
46
47 #include <nvif/class.h>
48 #include <nvif/cl0002.h>
49 #include <nvif/cla06f.h>
50
51 #include "nouveau_drv.h"
52 #include "nouveau_dma.h"
53 #include "nouveau_ttm.h"
54 #include "nouveau_gem.h"
55 #include "nouveau_vga.h"
56 #include "nouveau_led.h"
57 #include "nouveau_hwmon.h"
58 #include "nouveau_acpi.h"
59 #include "nouveau_bios.h"
60 #include "nouveau_ioctl.h"
61 #include "nouveau_abi16.h"
62 #include "nouveau_fbcon.h"
63 #include "nouveau_fence.h"
64 #include "nouveau_debugfs.h"
65 #include "nouveau_usif.h"
66 #include "nouveau_connector.h"
67 #include "nouveau_platform.h"
68 #include "nouveau_svm.h"
69 #include "nouveau_dmem.h"
70
71 MODULE_PARM_DESC(config, "option string to pass to driver core");
72 static char *nouveau_config;
73 module_param_named(config, nouveau_config, charp, 0400);
74
75 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
76 static char *nouveau_debug;
77 module_param_named(debug, nouveau_debug, charp, 0400);
78
79 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
80 static int nouveau_noaccel = 0;
81 module_param_named(noaccel, nouveau_noaccel, int, 0400);
82
83 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
84 "0 = disabled, 1 = enabled, 2 = headless)");
85 int nouveau_modeset = -1;
86 module_param_named(modeset, nouveau_modeset, int, 0400);
87
88 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
89 static int nouveau_atomic = 0;
90 module_param_named(atomic, nouveau_atomic, int, 0400);
91
92 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
93 static int nouveau_runtime_pm = -1;
94 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
95
96 static struct drm_driver driver_stub;
97 static struct drm_driver driver_pci;
98 static struct drm_driver driver_platform;
99
100 static u64
nouveau_pci_name(struct pci_dev * pdev)101 nouveau_pci_name(struct pci_dev *pdev)
102 {
103 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
104 name |= pdev->bus->number << 16;
105 name |= PCI_SLOT(pdev->devfn) << 8;
106 return name | PCI_FUNC(pdev->devfn);
107 }
108
109 static u64
nouveau_platform_name(struct platform_device * platformdev)110 nouveau_platform_name(struct platform_device *platformdev)
111 {
112 return platformdev->id;
113 }
114
115 static u64
nouveau_name(struct drm_device * dev)116 nouveau_name(struct drm_device *dev)
117 {
118 if (dev->pdev)
119 return nouveau_pci_name(dev->pdev);
120 else
121 return nouveau_platform_name(to_platform_device(dev->dev));
122 }
123
124 static inline bool
nouveau_cli_work_ready(struct dma_fence * fence)125 nouveau_cli_work_ready(struct dma_fence *fence)
126 {
127 if (!dma_fence_is_signaled(fence))
128 return false;
129 dma_fence_put(fence);
130 return true;
131 }
132
133 static void
nouveau_cli_work(struct work_struct * w)134 nouveau_cli_work(struct work_struct *w)
135 {
136 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
137 struct nouveau_cli_work *work, *wtmp;
138 mutex_lock(&cli->lock);
139 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
140 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
141 list_del(&work->head);
142 work->func(work);
143 }
144 }
145 mutex_unlock(&cli->lock);
146 }
147
148 static void
nouveau_cli_work_fence(struct dma_fence * fence,struct dma_fence_cb * cb)149 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
150 {
151 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
152 schedule_work(&work->cli->work);
153 }
154
155 void
nouveau_cli_work_queue(struct nouveau_cli * cli,struct dma_fence * fence,struct nouveau_cli_work * work)156 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
157 struct nouveau_cli_work *work)
158 {
159 work->fence = dma_fence_get(fence);
160 work->cli = cli;
161 mutex_lock(&cli->lock);
162 list_add_tail(&work->head, &cli->worker);
163 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
164 nouveau_cli_work_fence(fence, &work->cb);
165 mutex_unlock(&cli->lock);
166 }
167
168 static void
nouveau_cli_fini(struct nouveau_cli * cli)169 nouveau_cli_fini(struct nouveau_cli *cli)
170 {
171 /* All our channels are dead now, which means all the fences they
172 * own are signalled, and all callback functions have been called.
173 *
174 * So, after flushing the workqueue, there should be nothing left.
175 */
176 flush_work(&cli->work);
177 WARN_ON(!list_empty(&cli->worker));
178
179 usif_client_fini(cli);
180 nouveau_vmm_fini(&cli->svm);
181 nouveau_vmm_fini(&cli->vmm);
182 nvif_mmu_dtor(&cli->mmu);
183 nvif_device_dtor(&cli->device);
184 mutex_lock(&cli->drm->master.lock);
185 nvif_client_dtor(&cli->base);
186 mutex_unlock(&cli->drm->master.lock);
187 }
188
189 static int
nouveau_cli_init(struct nouveau_drm * drm,const char * sname,struct nouveau_cli * cli)190 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
191 struct nouveau_cli *cli)
192 {
193 static const struct nvif_mclass
194 mems[] = {
195 { NVIF_CLASS_MEM_GF100, -1 },
196 { NVIF_CLASS_MEM_NV50 , -1 },
197 { NVIF_CLASS_MEM_NV04 , -1 },
198 {}
199 };
200 static const struct nvif_mclass
201 mmus[] = {
202 { NVIF_CLASS_MMU_GF100, -1 },
203 { NVIF_CLASS_MMU_NV50 , -1 },
204 { NVIF_CLASS_MMU_NV04 , -1 },
205 {}
206 };
207 static const struct nvif_mclass
208 vmms[] = {
209 { NVIF_CLASS_VMM_GP100, -1 },
210 { NVIF_CLASS_VMM_GM200, -1 },
211 { NVIF_CLASS_VMM_GF100, -1 },
212 { NVIF_CLASS_VMM_NV50 , -1 },
213 { NVIF_CLASS_VMM_NV04 , -1 },
214 {}
215 };
216 u64 device = nouveau_name(drm->dev);
217 int ret;
218
219 snprintf(cli->name, sizeof(cli->name), "%s", sname);
220 cli->drm = drm;
221 mutex_init(&cli->mutex);
222 usif_client_init(cli);
223
224 INIT_WORK(&cli->work, nouveau_cli_work);
225 INIT_LIST_HEAD(&cli->worker);
226 mutex_init(&cli->lock);
227
228 if (cli == &drm->master) {
229 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
230 cli->name, device, &cli->base);
231 } else {
232 mutex_lock(&drm->master.lock);
233 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
234 &cli->base);
235 mutex_unlock(&drm->master.lock);
236 }
237 if (ret) {
238 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
239 goto done;
240 }
241
242 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
243 &(struct nv_device_v0) {
244 .device = ~0,
245 }, sizeof(struct nv_device_v0),
246 &cli->device);
247 if (ret) {
248 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
249 goto done;
250 }
251
252 ret = nvif_mclass(&cli->device.object, mmus);
253 if (ret < 0) {
254 NV_PRINTK(err, cli, "No supported MMU class\n");
255 goto done;
256 }
257
258 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
259 &cli->mmu);
260 if (ret) {
261 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
262 goto done;
263 }
264
265 ret = nvif_mclass(&cli->mmu.object, vmms);
266 if (ret < 0) {
267 NV_PRINTK(err, cli, "No supported VMM class\n");
268 goto done;
269 }
270
271 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
272 if (ret) {
273 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
274 goto done;
275 }
276
277 ret = nvif_mclass(&cli->mmu.object, mems);
278 if (ret < 0) {
279 NV_PRINTK(err, cli, "No supported MEM class\n");
280 goto done;
281 }
282
283 cli->mem = &mems[ret];
284 return 0;
285 done:
286 if (ret)
287 nouveau_cli_fini(cli);
288 return ret;
289 }
290
291 static void
nouveau_accel_ce_fini(struct nouveau_drm * drm)292 nouveau_accel_ce_fini(struct nouveau_drm *drm)
293 {
294 nouveau_channel_idle(drm->cechan);
295 nvif_object_dtor(&drm->ttm.copy);
296 nouveau_channel_del(&drm->cechan);
297 }
298
299 static void
nouveau_accel_ce_init(struct nouveau_drm * drm)300 nouveau_accel_ce_init(struct nouveau_drm *drm)
301 {
302 struct nvif_device *device = &drm->client.device;
303 int ret = 0;
304
305 /* Allocate channel that has access to a (preferably async) copy
306 * engine, to use for TTM buffer moves.
307 */
308 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
309 ret = nouveau_channel_new(drm, device,
310 nvif_fifo_runlist_ce(device), 0,
311 true, &drm->cechan);
312 } else
313 if (device->info.chipset >= 0xa3 &&
314 device->info.chipset != 0xaa &&
315 device->info.chipset != 0xac) {
316 /* Prior to Kepler, there's only a single runlist, so all
317 * engines can be accessed from any channel.
318 *
319 * We still want to use a separate channel though.
320 */
321 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
322 &drm->cechan);
323 }
324
325 if (ret)
326 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
327 }
328
329 static void
nouveau_accel_gr_fini(struct nouveau_drm * drm)330 nouveau_accel_gr_fini(struct nouveau_drm *drm)
331 {
332 nouveau_channel_idle(drm->channel);
333 nvif_object_dtor(&drm->ntfy);
334 nvkm_gpuobj_del(&drm->notify);
335 nouveau_channel_del(&drm->channel);
336 }
337
338 static void
nouveau_accel_gr_init(struct nouveau_drm * drm)339 nouveau_accel_gr_init(struct nouveau_drm *drm)
340 {
341 struct nvif_device *device = &drm->client.device;
342 u32 arg0, arg1;
343 int ret;
344
345 /* Allocate channel that has access to the graphics engine. */
346 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
347 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
348 arg1 = 1;
349 } else {
350 arg0 = NvDmaFB;
351 arg1 = NvDmaTT;
352 }
353
354 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
355 &drm->channel);
356 if (ret) {
357 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
358 nouveau_accel_gr_fini(drm);
359 return;
360 }
361
362 /* A SW class is used on pre-NV50 HW to assist with handling the
363 * synchronisation of page flips, as well as to implement fences
364 * on TNT/TNT2 HW that lacks any kind of support in host.
365 */
366 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
367 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
368 NVDRM_NVSW, nouveau_abi16_swclass(drm),
369 NULL, 0, &drm->channel->nvsw);
370 if (ret == 0) {
371 struct nvif_push *push = drm->channel->chan.push;
372 ret = PUSH_WAIT(push, 2);
373 if (ret == 0)
374 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
375 }
376
377 if (ret) {
378 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
379 nouveau_accel_gr_fini(drm);
380 return;
381 }
382 }
383
384 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
385 * even if notification is never requested, so, allocate a ctxdma on
386 * any GPU where it's possible we'll end up using M2MF for BO moves.
387 */
388 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
389 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
390 &drm->notify);
391 if (ret) {
392 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
393 nouveau_accel_gr_fini(drm);
394 return;
395 }
396
397 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
398 NvNotify0, NV_DMA_IN_MEMORY,
399 &(struct nv_dma_v0) {
400 .target = NV_DMA_V0_TARGET_VRAM,
401 .access = NV_DMA_V0_ACCESS_RDWR,
402 .start = drm->notify->addr,
403 .limit = drm->notify->addr + 31
404 }, sizeof(struct nv_dma_v0),
405 &drm->ntfy);
406 if (ret) {
407 nouveau_accel_gr_fini(drm);
408 return;
409 }
410 }
411 }
412
413 static void
nouveau_accel_fini(struct nouveau_drm * drm)414 nouveau_accel_fini(struct nouveau_drm *drm)
415 {
416 nouveau_accel_ce_fini(drm);
417 nouveau_accel_gr_fini(drm);
418 if (drm->fence)
419 nouveau_fence(drm)->dtor(drm);
420 }
421
422 static void
nouveau_accel_init(struct nouveau_drm * drm)423 nouveau_accel_init(struct nouveau_drm *drm)
424 {
425 struct nvif_device *device = &drm->client.device;
426 struct nvif_sclass *sclass;
427 int ret, i, n;
428
429 if (nouveau_noaccel)
430 return;
431
432 /* Initialise global support for channels, and synchronisation. */
433 ret = nouveau_channels_init(drm);
434 if (ret)
435 return;
436
437 /*XXX: this is crap, but the fence/channel stuff is a little
438 * backwards in some places. this will be fixed.
439 */
440 ret = n = nvif_object_sclass_get(&device->object, &sclass);
441 if (ret < 0)
442 return;
443
444 for (ret = -ENOSYS, i = 0; i < n; i++) {
445 switch (sclass[i].oclass) {
446 case NV03_CHANNEL_DMA:
447 ret = nv04_fence_create(drm);
448 break;
449 case NV10_CHANNEL_DMA:
450 ret = nv10_fence_create(drm);
451 break;
452 case NV17_CHANNEL_DMA:
453 case NV40_CHANNEL_DMA:
454 ret = nv17_fence_create(drm);
455 break;
456 case NV50_CHANNEL_GPFIFO:
457 ret = nv50_fence_create(drm);
458 break;
459 case G82_CHANNEL_GPFIFO:
460 ret = nv84_fence_create(drm);
461 break;
462 case FERMI_CHANNEL_GPFIFO:
463 case KEPLER_CHANNEL_GPFIFO_A:
464 case KEPLER_CHANNEL_GPFIFO_B:
465 case MAXWELL_CHANNEL_GPFIFO_A:
466 case PASCAL_CHANNEL_GPFIFO_A:
467 case VOLTA_CHANNEL_GPFIFO_A:
468 case TURING_CHANNEL_GPFIFO_A:
469 ret = nvc0_fence_create(drm);
470 break;
471 default:
472 break;
473 }
474 }
475
476 nvif_object_sclass_put(&sclass);
477 if (ret) {
478 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
479 nouveau_accel_fini(drm);
480 return;
481 }
482
483 /* Volta requires access to a doorbell register for kickoff. */
484 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
485 ret = nvif_user_ctor(device, "drmUsermode");
486 if (ret)
487 return;
488 }
489
490 /* Allocate channels we need to support various functions. */
491 nouveau_accel_gr_init(drm);
492 nouveau_accel_ce_init(drm);
493
494 /* Initialise accelerated TTM buffer moves. */
495 nouveau_bo_move_init(drm);
496 }
497
498 static void __printf(2, 3)
nouveau_drm_errorf(struct nvif_object * object,const char * fmt,...)499 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
500 {
501 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
502 struct va_format vaf;
503 va_list va;
504
505 va_start(va, fmt);
506 vaf.fmt = fmt;
507 vaf.va = &va;
508 NV_ERROR(drm, "%pV", &vaf);
509 va_end(va);
510 }
511
512 static void __printf(2, 3)
nouveau_drm_debugf(struct nvif_object * object,const char * fmt,...)513 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
514 {
515 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
516 struct va_format vaf;
517 va_list va;
518
519 va_start(va, fmt);
520 vaf.fmt = fmt;
521 vaf.va = &va;
522 NV_DEBUG(drm, "%pV", &vaf);
523 va_end(va);
524 }
525
526 static const struct nvif_parent_func
527 nouveau_parent = {
528 .debugf = nouveau_drm_debugf,
529 .errorf = nouveau_drm_errorf,
530 };
531
532 static int
nouveau_drm_device_init(struct drm_device * dev)533 nouveau_drm_device_init(struct drm_device *dev)
534 {
535 struct nouveau_drm *drm;
536 int ret;
537
538 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
539 return -ENOMEM;
540 dev->dev_private = drm;
541 drm->dev = dev;
542
543 nvif_parent_ctor(&nouveau_parent, &drm->parent);
544 drm->master.base.object.parent = &drm->parent;
545
546 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
547 if (ret)
548 goto fail_alloc;
549
550 ret = nouveau_cli_init(drm, "DRM", &drm->client);
551 if (ret)
552 goto fail_master;
553
554 dev->irq_enabled = true;
555
556 nvxx_client(&drm->client.base)->debug =
557 nvkm_dbgopt(nouveau_debug, "DRM");
558
559 INIT_LIST_HEAD(&drm->clients);
560 mutex_init(&drm->clients_lock);
561 spin_lock_init(&drm->tile.lock);
562
563 /* workaround an odd issue on nvc1 by disabling the device's
564 * nosnoop capability. hopefully won't cause issues until a
565 * better fix is found - assuming there is one...
566 */
567 if (drm->client.device.info.chipset == 0xc1)
568 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
569
570 nouveau_vga_init(drm);
571
572 ret = nouveau_ttm_init(drm);
573 if (ret)
574 goto fail_ttm;
575
576 ret = nouveau_bios_init(dev);
577 if (ret)
578 goto fail_bios;
579
580 nouveau_accel_init(drm);
581
582 ret = nouveau_display_create(dev);
583 if (ret)
584 goto fail_dispctor;
585
586 if (dev->mode_config.num_crtc) {
587 ret = nouveau_display_init(dev, false, false);
588 if (ret)
589 goto fail_dispinit;
590 }
591
592 nouveau_debugfs_init(drm);
593 nouveau_hwmon_init(dev);
594 nouveau_svm_init(drm);
595 nouveau_dmem_init(drm);
596 nouveau_fbcon_init(dev);
597 nouveau_led_init(dev);
598
599 if (nouveau_pmops_runtime()) {
600 pm_runtime_use_autosuspend(dev->dev);
601 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
602 pm_runtime_set_active(dev->dev);
603 pm_runtime_allow(dev->dev);
604 pm_runtime_mark_last_busy(dev->dev);
605 pm_runtime_put(dev->dev);
606 }
607
608 return 0;
609
610 fail_dispinit:
611 nouveau_display_destroy(dev);
612 fail_dispctor:
613 nouveau_accel_fini(drm);
614 nouveau_bios_takedown(dev);
615 fail_bios:
616 nouveau_ttm_fini(drm);
617 fail_ttm:
618 nouveau_vga_fini(drm);
619 nouveau_cli_fini(&drm->client);
620 fail_master:
621 nouveau_cli_fini(&drm->master);
622 fail_alloc:
623 nvif_parent_dtor(&drm->parent);
624 kfree(drm);
625 return ret;
626 }
627
628 static void
nouveau_drm_device_fini(struct drm_device * dev)629 nouveau_drm_device_fini(struct drm_device *dev)
630 {
631 struct nouveau_cli *cli, *temp_cli;
632 struct nouveau_drm *drm = nouveau_drm(dev);
633
634 if (nouveau_pmops_runtime()) {
635 pm_runtime_get_sync(dev->dev);
636 pm_runtime_forbid(dev->dev);
637 }
638
639 nouveau_led_fini(dev);
640 nouveau_fbcon_fini(dev);
641 nouveau_dmem_fini(drm);
642 nouveau_svm_fini(drm);
643 nouveau_hwmon_fini(dev);
644 nouveau_debugfs_fini(drm);
645
646 if (dev->mode_config.num_crtc)
647 nouveau_display_fini(dev, false, false);
648 nouveau_display_destroy(dev);
649
650 nouveau_accel_fini(drm);
651 nouveau_bios_takedown(dev);
652
653 nouveau_ttm_fini(drm);
654 nouveau_vga_fini(drm);
655
656 /*
657 * There may be existing clients from as-yet unclosed files. For now,
658 * clean them up here rather than deferring until the file is closed,
659 * but this likely not correct if we want to support hot-unplugging
660 * properly.
661 */
662 mutex_lock(&drm->clients_lock);
663 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
664 list_del(&cli->head);
665 mutex_lock(&cli->mutex);
666 if (cli->abi16)
667 nouveau_abi16_fini(cli->abi16);
668 mutex_unlock(&cli->mutex);
669 nouveau_cli_fini(cli);
670 kfree(cli);
671 }
672 mutex_unlock(&drm->clients_lock);
673
674 nouveau_cli_fini(&drm->client);
675 nouveau_cli_fini(&drm->master);
676 nvif_parent_dtor(&drm->parent);
677 mutex_destroy(&drm->clients_lock);
678 kfree(drm);
679 }
680
681 /*
682 * On some Intel PCIe bridge controllers doing a
683 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
684 * Skipping the intermediate D3hot step seems to make it work again. This is
685 * probably caused by not meeting the expectation the involved AML code has
686 * when the GPU is put into D3hot state before invoking it.
687 *
688 * This leads to various manifestations of this issue:
689 * - AML code execution to power on the GPU hits an infinite loop (as the
690 * code waits on device memory to change).
691 * - kernel crashes, as all PCI reads return -1, which most code isn't able
692 * to handle well enough.
693 *
694 * In all cases dmesg will contain at least one line like this:
695 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
696 * followed by a lot of nouveau timeouts.
697 *
698 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
699 * documented PCI config space register 0x248 of the Intel PCIe bridge
700 * controller (0x1901) in order to change the state of the PCIe link between
701 * the PCIe port and the GPU. There are alternative code paths using other
702 * registers, which seem to work fine (executed pre Windows 8):
703 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
704 * - 0xb0 bit 0x10 (link disable)
705 * Changing the conditions inside the firmware by poking into the relevant
706 * addresses does resolve the issue, but it seemed to be ACPI private memory
707 * and not any device accessible memory at all, so there is no portable way of
708 * changing the conditions.
709 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
710 *
711 * The only systems where this behavior can be seen are hybrid graphics laptops
712 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
713 * this issue only occurs in combination with listed Intel PCIe bridge
714 * controllers and the mentioned GPUs or other devices as well.
715 *
716 * documentation on the PCIe bridge controller can be found in the
717 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
718 * Section "12 PCI Express* Controller (x16) Registers"
719 */
720
quirk_broken_nv_runpm(struct pci_dev * pdev)721 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
722 {
723 struct drm_device *dev = pci_get_drvdata(pdev);
724 struct nouveau_drm *drm = nouveau_drm(dev);
725 struct pci_dev *bridge = pci_upstream_bridge(pdev);
726
727 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
728 return;
729
730 switch (bridge->device) {
731 case 0x1901:
732 drm->old_pm_cap = pdev->pm_cap;
733 pdev->pm_cap = 0;
734 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
735 break;
736 }
737 }
738
nouveau_drm_probe(struct pci_dev * pdev,const struct pci_device_id * pent)739 static int nouveau_drm_probe(struct pci_dev *pdev,
740 const struct pci_device_id *pent)
741 {
742 struct nvkm_device *device;
743 struct drm_device *drm_dev;
744 int ret;
745
746 if (vga_switcheroo_client_probe_defer(pdev))
747 return -EPROBE_DEFER;
748
749 /* We need to check that the chipset is supported before booting
750 * fbdev off the hardware, as there's no way to put it back.
751 */
752 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
753 true, false, 0, &device);
754 if (ret)
755 return ret;
756
757 nvkm_device_del(&device);
758
759 /* Remove conflicting drivers (vesafb, efifb etc). */
760 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "nouveaufb");
761 if (ret)
762 return ret;
763
764 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
765 true, true, ~0ULL, &device);
766 if (ret)
767 return ret;
768
769 pci_set_master(pdev);
770
771 if (nouveau_atomic)
772 driver_pci.driver_features |= DRIVER_ATOMIC;
773
774 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
775 if (IS_ERR(drm_dev)) {
776 ret = PTR_ERR(drm_dev);
777 goto fail_nvkm;
778 }
779
780 ret = pci_enable_device(pdev);
781 if (ret)
782 goto fail_drm;
783
784 drm_dev->pdev = pdev;
785 pci_set_drvdata(pdev, drm_dev);
786
787 ret = nouveau_drm_device_init(drm_dev);
788 if (ret)
789 goto fail_pci;
790
791 ret = drm_dev_register(drm_dev, pent->driver_data);
792 if (ret)
793 goto fail_drm_dev_init;
794
795 quirk_broken_nv_runpm(pdev);
796 return 0;
797
798 fail_drm_dev_init:
799 nouveau_drm_device_fini(drm_dev);
800 fail_pci:
801 pci_disable_device(pdev);
802 fail_drm:
803 drm_dev_put(drm_dev);
804 fail_nvkm:
805 nvkm_device_del(&device);
806 return ret;
807 }
808
809 void
nouveau_drm_device_remove(struct drm_device * dev)810 nouveau_drm_device_remove(struct drm_device *dev)
811 {
812 struct nouveau_drm *drm = nouveau_drm(dev);
813 struct nvkm_client *client;
814 struct nvkm_device *device;
815
816 drm_dev_unplug(dev);
817
818 dev->irq_enabled = false;
819 client = nvxx_client(&drm->client.base);
820 device = nvkm_device_find(client->device);
821
822 nouveau_drm_device_fini(dev);
823 drm_dev_put(dev);
824 nvkm_device_del(&device);
825 }
826
827 static void
nouveau_drm_remove(struct pci_dev * pdev)828 nouveau_drm_remove(struct pci_dev *pdev)
829 {
830 struct drm_device *dev = pci_get_drvdata(pdev);
831 struct nouveau_drm *drm = nouveau_drm(dev);
832
833 /* revert our workaround */
834 if (drm->old_pm_cap)
835 pdev->pm_cap = drm->old_pm_cap;
836 nouveau_drm_device_remove(dev);
837 pci_disable_device(pdev);
838 }
839
840 static int
nouveau_do_suspend(struct drm_device * dev,bool runtime)841 nouveau_do_suspend(struct drm_device *dev, bool runtime)
842 {
843 struct nouveau_drm *drm = nouveau_drm(dev);
844 int ret;
845
846 nouveau_svm_suspend(drm);
847 nouveau_dmem_suspend(drm);
848 nouveau_led_suspend(dev);
849
850 if (dev->mode_config.num_crtc) {
851 NV_DEBUG(drm, "suspending console...\n");
852 nouveau_fbcon_set_suspend(dev, 1);
853 NV_DEBUG(drm, "suspending display...\n");
854 ret = nouveau_display_suspend(dev, runtime);
855 if (ret)
856 return ret;
857 }
858
859 NV_DEBUG(drm, "evicting buffers...\n");
860 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
861
862 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
863 if (drm->cechan) {
864 ret = nouveau_channel_idle(drm->cechan);
865 if (ret)
866 goto fail_display;
867 }
868
869 if (drm->channel) {
870 ret = nouveau_channel_idle(drm->channel);
871 if (ret)
872 goto fail_display;
873 }
874
875 NV_DEBUG(drm, "suspending fence...\n");
876 if (drm->fence && nouveau_fence(drm)->suspend) {
877 if (!nouveau_fence(drm)->suspend(drm)) {
878 ret = -ENOMEM;
879 goto fail_display;
880 }
881 }
882
883 NV_DEBUG(drm, "suspending object tree...\n");
884 ret = nvif_client_suspend(&drm->master.base);
885 if (ret)
886 goto fail_client;
887
888 return 0;
889
890 fail_client:
891 if (drm->fence && nouveau_fence(drm)->resume)
892 nouveau_fence(drm)->resume(drm);
893
894 fail_display:
895 if (dev->mode_config.num_crtc) {
896 NV_DEBUG(drm, "resuming display...\n");
897 nouveau_display_resume(dev, runtime);
898 }
899 return ret;
900 }
901
902 static int
nouveau_do_resume(struct drm_device * dev,bool runtime)903 nouveau_do_resume(struct drm_device *dev, bool runtime)
904 {
905 int ret = 0;
906 struct nouveau_drm *drm = nouveau_drm(dev);
907
908 NV_DEBUG(drm, "resuming object tree...\n");
909 ret = nvif_client_resume(&drm->master.base);
910 if (ret) {
911 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
912 return ret;
913 }
914
915 NV_DEBUG(drm, "resuming fence...\n");
916 if (drm->fence && nouveau_fence(drm)->resume)
917 nouveau_fence(drm)->resume(drm);
918
919 nouveau_run_vbios_init(dev);
920
921 if (dev->mode_config.num_crtc) {
922 NV_DEBUG(drm, "resuming display...\n");
923 nouveau_display_resume(dev, runtime);
924 NV_DEBUG(drm, "resuming console...\n");
925 nouveau_fbcon_set_suspend(dev, 0);
926 }
927
928 nouveau_led_resume(dev);
929 nouveau_dmem_resume(drm);
930 nouveau_svm_resume(drm);
931 return 0;
932 }
933
934 int
nouveau_pmops_suspend(struct device * dev)935 nouveau_pmops_suspend(struct device *dev)
936 {
937 struct pci_dev *pdev = to_pci_dev(dev);
938 struct drm_device *drm_dev = pci_get_drvdata(pdev);
939 int ret;
940
941 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
942 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
943 return 0;
944
945 ret = nouveau_do_suspend(drm_dev, false);
946 if (ret)
947 return ret;
948
949 pci_save_state(pdev);
950 pci_disable_device(pdev);
951 pci_set_power_state(pdev, PCI_D3hot);
952 udelay(200);
953 return 0;
954 }
955
956 int
nouveau_pmops_resume(struct device * dev)957 nouveau_pmops_resume(struct device *dev)
958 {
959 struct pci_dev *pdev = to_pci_dev(dev);
960 struct drm_device *drm_dev = pci_get_drvdata(pdev);
961 int ret;
962
963 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
964 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
965 return 0;
966
967 pci_set_power_state(pdev, PCI_D0);
968 pci_restore_state(pdev);
969 ret = pci_enable_device(pdev);
970 if (ret)
971 return ret;
972 pci_set_master(pdev);
973
974 ret = nouveau_do_resume(drm_dev, false);
975
976 /* Monitors may have been connected / disconnected during suspend */
977 nouveau_display_hpd_resume(drm_dev);
978
979 return ret;
980 }
981
982 static int
nouveau_pmops_freeze(struct device * dev)983 nouveau_pmops_freeze(struct device *dev)
984 {
985 struct pci_dev *pdev = to_pci_dev(dev);
986 struct drm_device *drm_dev = pci_get_drvdata(pdev);
987 return nouveau_do_suspend(drm_dev, false);
988 }
989
990 static int
nouveau_pmops_thaw(struct device * dev)991 nouveau_pmops_thaw(struct device *dev)
992 {
993 struct pci_dev *pdev = to_pci_dev(dev);
994 struct drm_device *drm_dev = pci_get_drvdata(pdev);
995 return nouveau_do_resume(drm_dev, false);
996 }
997
998 bool
nouveau_pmops_runtime(void)999 nouveau_pmops_runtime(void)
1000 {
1001 if (nouveau_runtime_pm == -1)
1002 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1003 return nouveau_runtime_pm == 1;
1004 }
1005
1006 static int
nouveau_pmops_runtime_suspend(struct device * dev)1007 nouveau_pmops_runtime_suspend(struct device *dev)
1008 {
1009 struct pci_dev *pdev = to_pci_dev(dev);
1010 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1011 int ret;
1012
1013 if (!nouveau_pmops_runtime()) {
1014 pm_runtime_forbid(dev);
1015 return -EBUSY;
1016 }
1017
1018 nouveau_switcheroo_optimus_dsm();
1019 ret = nouveau_do_suspend(drm_dev, true);
1020 pci_save_state(pdev);
1021 pci_disable_device(pdev);
1022 pci_ignore_hotplug(pdev);
1023 pci_set_power_state(pdev, PCI_D3cold);
1024 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1025 return ret;
1026 }
1027
1028 static int
nouveau_pmops_runtime_resume(struct device * dev)1029 nouveau_pmops_runtime_resume(struct device *dev)
1030 {
1031 struct pci_dev *pdev = to_pci_dev(dev);
1032 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1033 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1034 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1035 int ret;
1036
1037 if (!nouveau_pmops_runtime()) {
1038 pm_runtime_forbid(dev);
1039 return -EBUSY;
1040 }
1041
1042 pci_set_power_state(pdev, PCI_D0);
1043 pci_restore_state(pdev);
1044 ret = pci_enable_device(pdev);
1045 if (ret)
1046 return ret;
1047 pci_set_master(pdev);
1048
1049 ret = nouveau_do_resume(drm_dev, true);
1050 if (ret) {
1051 NV_ERROR(drm, "resume failed with: %d\n", ret);
1052 return ret;
1053 }
1054
1055 /* do magic */
1056 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1057 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1058
1059 /* Monitors may have been connected / disconnected during suspend */
1060 nouveau_display_hpd_resume(drm_dev);
1061
1062 return ret;
1063 }
1064
1065 static int
nouveau_pmops_runtime_idle(struct device * dev)1066 nouveau_pmops_runtime_idle(struct device *dev)
1067 {
1068 if (!nouveau_pmops_runtime()) {
1069 pm_runtime_forbid(dev);
1070 return -EBUSY;
1071 }
1072
1073 pm_runtime_mark_last_busy(dev);
1074 pm_runtime_autosuspend(dev);
1075 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1076 return 1;
1077 }
1078
1079 static int
nouveau_drm_open(struct drm_device * dev,struct drm_file * fpriv)1080 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1081 {
1082 struct nouveau_drm *drm = nouveau_drm(dev);
1083 struct nouveau_cli *cli;
1084 char name[32], tmpname[TASK_COMM_LEN];
1085 int ret;
1086
1087 /* need to bring up power immediately if opening device */
1088 ret = pm_runtime_get_sync(dev->dev);
1089 if (ret < 0 && ret != -EACCES) {
1090 pm_runtime_put_autosuspend(dev->dev);
1091 return ret;
1092 }
1093
1094 get_task_comm(tmpname, current);
1095 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1096
1097 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1098 ret = -ENOMEM;
1099 goto done;
1100 }
1101
1102 ret = nouveau_cli_init(drm, name, cli);
1103 if (ret)
1104 goto done;
1105
1106 cli->base.super = false;
1107
1108 fpriv->driver_priv = cli;
1109
1110 mutex_lock(&drm->clients_lock);
1111 list_add(&cli->head, &drm->clients);
1112 mutex_unlock(&drm->clients_lock);
1113
1114 done:
1115 if (ret && cli) {
1116 nouveau_cli_fini(cli);
1117 kfree(cli);
1118 }
1119
1120 pm_runtime_mark_last_busy(dev->dev);
1121 pm_runtime_put_autosuspend(dev->dev);
1122 return ret;
1123 }
1124
1125 static void
nouveau_drm_postclose(struct drm_device * dev,struct drm_file * fpriv)1126 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1127 {
1128 struct nouveau_cli *cli = nouveau_cli(fpriv);
1129 struct nouveau_drm *drm = nouveau_drm(dev);
1130 int dev_index;
1131
1132 /*
1133 * The device is gone, and as it currently stands all clients are
1134 * cleaned up in the removal codepath. In the future this may change
1135 * so that we can support hot-unplugging, but for now we immediately
1136 * return to avoid a double-free situation.
1137 */
1138 if (!drm_dev_enter(dev, &dev_index))
1139 return;
1140
1141 pm_runtime_get_sync(dev->dev);
1142
1143 mutex_lock(&cli->mutex);
1144 if (cli->abi16)
1145 nouveau_abi16_fini(cli->abi16);
1146 mutex_unlock(&cli->mutex);
1147
1148 mutex_lock(&drm->clients_lock);
1149 list_del(&cli->head);
1150 mutex_unlock(&drm->clients_lock);
1151
1152 nouveau_cli_fini(cli);
1153 kfree(cli);
1154 pm_runtime_mark_last_busy(dev->dev);
1155 pm_runtime_put_autosuspend(dev->dev);
1156 drm_dev_exit(dev_index);
1157 }
1158
1159 static const struct drm_ioctl_desc
1160 nouveau_ioctls[] = {
1161 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1162 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1163 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1164 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1165 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1166 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1167 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1168 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1169 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1170 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1171 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1172 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1173 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1174 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1175 };
1176
1177 long
nouveau_drm_ioctl(struct file * file,unsigned int cmd,unsigned long arg)1178 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1179 {
1180 struct drm_file *filp = file->private_data;
1181 struct drm_device *dev = filp->minor->dev;
1182 long ret;
1183
1184 ret = pm_runtime_get_sync(dev->dev);
1185 if (ret < 0 && ret != -EACCES) {
1186 pm_runtime_put_autosuspend(dev->dev);
1187 return ret;
1188 }
1189
1190 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1191 case DRM_NOUVEAU_NVIF:
1192 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1193 break;
1194 default:
1195 ret = drm_ioctl(file, cmd, arg);
1196 break;
1197 }
1198
1199 pm_runtime_mark_last_busy(dev->dev);
1200 pm_runtime_put_autosuspend(dev->dev);
1201 return ret;
1202 }
1203
1204 static const struct file_operations
1205 nouveau_driver_fops = {
1206 .owner = THIS_MODULE,
1207 .open = drm_open,
1208 .release = drm_release,
1209 .unlocked_ioctl = nouveau_drm_ioctl,
1210 .mmap = nouveau_ttm_mmap,
1211 .poll = drm_poll,
1212 .read = drm_read,
1213 #if defined(CONFIG_COMPAT)
1214 .compat_ioctl = nouveau_compat_ioctl,
1215 #endif
1216 .llseek = noop_llseek,
1217 };
1218
1219 static struct drm_driver
1220 driver_stub = {
1221 .driver_features =
1222 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1223 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1224 | DRIVER_KMS_LEGACY_CONTEXT
1225 #endif
1226 ,
1227
1228 .open = nouveau_drm_open,
1229 .postclose = nouveau_drm_postclose,
1230 .lastclose = nouveau_vga_lastclose,
1231
1232 #if defined(CONFIG_DEBUG_FS)
1233 .debugfs_init = nouveau_drm_debugfs_init,
1234 #endif
1235
1236 .ioctls = nouveau_ioctls,
1237 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1238 .fops = &nouveau_driver_fops,
1239
1240 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1241 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1242 .gem_prime_pin = nouveau_gem_prime_pin,
1243 .gem_prime_unpin = nouveau_gem_prime_unpin,
1244 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1245 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1246 .gem_prime_vmap = nouveau_gem_prime_vmap,
1247 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
1248
1249 .gem_free_object_unlocked = nouveau_gem_object_del,
1250 .gem_open_object = nouveau_gem_object_open,
1251 .gem_close_object = nouveau_gem_object_close,
1252
1253 .dumb_create = nouveau_display_dumb_create,
1254 .dumb_map_offset = nouveau_display_dumb_map_offset,
1255
1256 .name = DRIVER_NAME,
1257 .desc = DRIVER_DESC,
1258 #ifdef GIT_REVISION
1259 .date = GIT_REVISION,
1260 #else
1261 .date = DRIVER_DATE,
1262 #endif
1263 .major = DRIVER_MAJOR,
1264 .minor = DRIVER_MINOR,
1265 .patchlevel = DRIVER_PATCHLEVEL,
1266 };
1267
1268 static struct pci_device_id
1269 nouveau_drm_pci_table[] = {
1270 {
1271 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1272 .class = PCI_BASE_CLASS_DISPLAY << 16,
1273 .class_mask = 0xff << 16,
1274 },
1275 {
1276 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1277 .class = PCI_BASE_CLASS_DISPLAY << 16,
1278 .class_mask = 0xff << 16,
1279 },
1280 {}
1281 };
1282
nouveau_display_options(void)1283 static void nouveau_display_options(void)
1284 {
1285 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1286
1287 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1288 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1289 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1290 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1291 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1292 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1293 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1294 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1295 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1296 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1297 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1298 }
1299
1300 static const struct dev_pm_ops nouveau_pm_ops = {
1301 .suspend = nouveau_pmops_suspend,
1302 .resume = nouveau_pmops_resume,
1303 .freeze = nouveau_pmops_freeze,
1304 .thaw = nouveau_pmops_thaw,
1305 .poweroff = nouveau_pmops_freeze,
1306 .restore = nouveau_pmops_resume,
1307 .runtime_suspend = nouveau_pmops_runtime_suspend,
1308 .runtime_resume = nouveau_pmops_runtime_resume,
1309 .runtime_idle = nouveau_pmops_runtime_idle,
1310 };
1311
1312 static struct pci_driver
1313 nouveau_drm_pci_driver = {
1314 .name = "nouveau",
1315 .id_table = nouveau_drm_pci_table,
1316 .probe = nouveau_drm_probe,
1317 .remove = nouveau_drm_remove,
1318 .driver.pm = &nouveau_pm_ops,
1319 };
1320
1321 struct drm_device *
nouveau_platform_device_create(const struct nvkm_device_tegra_func * func,struct platform_device * pdev,struct nvkm_device ** pdevice)1322 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1323 struct platform_device *pdev,
1324 struct nvkm_device **pdevice)
1325 {
1326 struct drm_device *drm;
1327 int err;
1328
1329 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1330 true, true, ~0ULL, pdevice);
1331 if (err)
1332 goto err_free;
1333
1334 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1335 if (IS_ERR(drm)) {
1336 err = PTR_ERR(drm);
1337 goto err_free;
1338 }
1339
1340 err = nouveau_drm_device_init(drm);
1341 if (err)
1342 goto err_put;
1343
1344 platform_set_drvdata(pdev, drm);
1345
1346 return drm;
1347
1348 err_put:
1349 drm_dev_put(drm);
1350 err_free:
1351 nvkm_device_del(pdevice);
1352
1353 return ERR_PTR(err);
1354 }
1355
1356 static int __init
nouveau_drm_init(void)1357 nouveau_drm_init(void)
1358 {
1359 driver_pci = driver_stub;
1360 driver_platform = driver_stub;
1361
1362 nouveau_display_options();
1363
1364 if (nouveau_modeset == -1) {
1365 if (vgacon_text_force())
1366 nouveau_modeset = 0;
1367 }
1368
1369 if (!nouveau_modeset)
1370 return 0;
1371
1372 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1373 platform_driver_register(&nouveau_platform_driver);
1374 #endif
1375
1376 nouveau_register_dsm_handler();
1377 nouveau_backlight_ctor();
1378
1379 #ifdef CONFIG_PCI
1380 return pci_register_driver(&nouveau_drm_pci_driver);
1381 #else
1382 return 0;
1383 #endif
1384 }
1385
1386 static void __exit
nouveau_drm_exit(void)1387 nouveau_drm_exit(void)
1388 {
1389 if (!nouveau_modeset)
1390 return;
1391
1392 #ifdef CONFIG_PCI
1393 pci_unregister_driver(&nouveau_drm_pci_driver);
1394 #endif
1395 nouveau_backlight_dtor();
1396 nouveau_unregister_dsm_handler();
1397
1398 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1399 platform_driver_unregister(&nouveau_platform_driver);
1400 #endif
1401 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1402 mmu_notifier_synchronize();
1403 }
1404
1405 module_init(nouveau_drm_init);
1406 module_exit(nouveau_drm_exit);
1407
1408 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1409 MODULE_AUTHOR(DRIVER_AUTHOR);
1410 MODULE_DESCRIPTION(DRIVER_DESC);
1411 MODULE_LICENSE("GPL and additional rights");
1412