1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/format/u_format.h"
29 #include "util/format/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42
43 #define RANKINE_0397_CHIPSET 0x00000003
44 #define RANKINE_0497_CHIPSET 0x000001e0
45 #define RANKINE_0697_CHIPSET 0x00000010
46 #define CURIE_4097_CHIPSET 0x00000baf
47 #define CURIE_4497_CHIPSET 0x00005450
48 #define CURIE_4497_CHIPSET6X 0x00000088
49
50 static int
nv30_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)51 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52 {
53 struct nv30_screen *screen = nv30_screen(pscreen);
54 struct nouveau_object *eng3d = screen->eng3d;
55 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
56
57 switch (param) {
58 /* non-boolean capabilities */
59 case PIPE_CAP_MAX_RENDER_TARGETS:
60 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
61 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
62 return 4096;
63 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64 return 10;
65 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66 return 13;
67 case PIPE_CAP_GLSL_FEATURE_LEVEL:
68 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69 return 120;
70 case PIPE_CAP_ENDIANNESS:
71 return PIPE_ENDIAN_LITTLE;
72 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73 return 16;
74 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
75 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
76 case PIPE_CAP_MAX_VIEWPORTS:
77 return 1;
78 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79 return 2048;
80 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
81 return 8 * 1024 * 1024;
82 case PIPE_CAP_MAX_VARYINGS:
83 return 8;
84
85 /* supported capabilities */
86 case PIPE_CAP_ANISOTROPIC_FILTER:
87 case PIPE_CAP_POINT_SPRITE:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_CLEAR_SCISSORED:
100 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
103 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104 return 1;
105 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
106 return PIPE_TEXTURE_TRANSFER_BLIT;
107 /* nv35 capabilities */
108 case PIPE_CAP_DEPTH_BOUNDS_TEST:
109 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
110 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
111 case PIPE_CAP_SUPPORTED_PRIM_MODES:
112 return BITFIELD_MASK(PIPE_PRIM_MAX);
113 /* nv4x capabilities */
114 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
115 case PIPE_CAP_NPOT_TEXTURES:
116 case PIPE_CAP_CONDITIONAL_RENDER:
117 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
118 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
119 case PIPE_CAP_PRIMITIVE_RESTART:
120 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
121 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
122 /* unsupported */
123 case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
124 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
125 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
126 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
127 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
128 case PIPE_CAP_INDEP_BLEND_ENABLE:
129 case PIPE_CAP_INDEP_BLEND_FUNC:
130 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
131 case PIPE_CAP_SHADER_STENCIL_EXPORT:
132 case PIPE_CAP_VS_INSTANCEID:
133 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
134 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
135 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
136 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
137 case PIPE_CAP_MIN_TEXEL_OFFSET:
138 case PIPE_CAP_MAX_TEXEL_OFFSET:
139 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
140 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
141 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
142 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
143 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
144 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
145 case PIPE_CAP_MAX_VERTEX_STREAMS:
146 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
147 case PIPE_CAP_TEXTURE_BARRIER:
148 case PIPE_CAP_SEAMLESS_CUBE_MAP:
149 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
150 case PIPE_CAP_CUBE_MAP_ARRAY:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
152 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
153 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
154 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
155 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
156 case PIPE_CAP_START_INSTANCE:
157 case PIPE_CAP_TEXTURE_MULTISAMPLE:
158 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
159 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
160 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
163 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
164 case PIPE_CAP_VS_LAYER_VIEWPORT:
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 case PIPE_CAP_TEXTURE_GATHER_SM5:
167 case PIPE_CAP_FAKE_SW_MSAA:
168 case PIPE_CAP_TEXTURE_QUERY_LOD:
169 case PIPE_CAP_SAMPLE_SHADING:
170 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
171 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
172 case PIPE_CAP_USER_VERTEX_BUFFERS:
173 case PIPE_CAP_COMPUTE:
174 case PIPE_CAP_DRAW_INDIRECT:
175 case PIPE_CAP_MULTI_DRAW_INDIRECT:
176 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
177 case PIPE_CAP_FS_FINE_DERIVATIVE:
178 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
179 case PIPE_CAP_SAMPLER_VIEW_TARGET:
180 case PIPE_CAP_CLIP_HALFZ:
181 case PIPE_CAP_VERTEXID_NOBASE:
182 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
183 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
184 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
185 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
186 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
190 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_CLEAR_TEXTURE:
194 case PIPE_CAP_DRAW_PARAMETERS:
195 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
196 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
197 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
198 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
199 case PIPE_CAP_INVALIDATE_BUFFER:
200 case PIPE_CAP_GENERATE_MIPMAP:
201 case PIPE_CAP_STRING_MARKER:
202 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
203 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
204 case PIPE_CAP_QUERY_BUFFER_OBJECT:
205 case PIPE_CAP_QUERY_MEMORY_INFO:
206 case PIPE_CAP_PCI_GROUP:
207 case PIPE_CAP_PCI_BUS:
208 case PIPE_CAP_PCI_DEVICE:
209 case PIPE_CAP_PCI_FUNCTION:
210 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
211 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
212 case PIPE_CAP_CULL_DISTANCE:
213 case PIPE_CAP_SHADER_GROUP_VOTE:
214 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
215 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
216 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
217 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
218 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
219 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
220 case PIPE_CAP_NATIVE_FENCE_FD:
221 case PIPE_CAP_FBFETCH:
222 case PIPE_CAP_LEGACY_MATH_RULES:
223 case PIPE_CAP_DOUBLES:
224 case PIPE_CAP_INT64:
225 case PIPE_CAP_INT64_DIVMOD:
226 case PIPE_CAP_TGSI_TEX_TXF_LZ:
227 case PIPE_CAP_SHADER_CLOCK:
228 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
229 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
230 case PIPE_CAP_SHADER_BALLOT:
231 case PIPE_CAP_TES_LAYER_VIEWPORT:
232 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
233 case PIPE_CAP_POST_DEPTH_COVERAGE:
234 case PIPE_CAP_BINDLESS_TEXTURE:
235 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
236 case PIPE_CAP_QUERY_SO_OVERFLOW:
237 case PIPE_CAP_MEMOBJ:
238 case PIPE_CAP_LOAD_CONSTBUF:
239 case PIPE_CAP_TILE_RASTER_ORDER:
240 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
241 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
242 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
243 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
244 case PIPE_CAP_FENCE_SIGNAL:
245 case PIPE_CAP_CONSTBUF0_FLAGS:
246 case PIPE_CAP_PACKED_UNIFORMS:
247 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
248 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
249 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
250 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
251 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
252 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
253 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
254 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
255 case PIPE_CAP_TGSI_DIV:
256 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
257 case PIPE_CAP_IMAGE_STORE_FORMATTED:
258 return 0;
259
260 case PIPE_CAP_MAX_GS_INVOCATIONS:
261 return 32;
262 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
263 return 1 << 27;
264 case PIPE_CAP_VENDOR_ID:
265 return 0x10de;
266 case PIPE_CAP_DEVICE_ID: {
267 uint64_t device_id;
268 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
269 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
270 return -1;
271 }
272 return device_id;
273 }
274 case PIPE_CAP_ACCELERATED:
275 return 1;
276 case PIPE_CAP_VIDEO_MEMORY:
277 return dev->vram_size >> 20;
278 case PIPE_CAP_UMA:
279 return 0;
280 default:
281 return u_pipe_screen_get_param_defaults(pscreen, param);
282 }
283 }
284
285 static float
nv30_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)286 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
287 {
288 struct nv30_screen *screen = nv30_screen(pscreen);
289 struct nouveau_object *eng3d = screen->eng3d;
290
291 switch (param) {
292 case PIPE_CAPF_MIN_LINE_WIDTH:
293 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
294 case PIPE_CAPF_MIN_POINT_SIZE:
295 case PIPE_CAPF_MIN_POINT_SIZE_AA:
296 return 1;
297 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
298 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
299 return 0.1;
300 case PIPE_CAPF_MAX_LINE_WIDTH:
301 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
302 return 10.0;
303 case PIPE_CAPF_MAX_POINT_SIZE:
304 case PIPE_CAPF_MAX_POINT_SIZE_AA:
305 return 64.0;
306 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
307 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
308 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
309 return 15.0;
310 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
311 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
312 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
313 return 0.0;
314 default:
315 debug_printf("unknown paramf %d\n", param);
316 return 0;
317 }
318 }
319
320 static int
nv30_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)321 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
322 enum pipe_shader_type shader,
323 enum pipe_shader_cap param)
324 {
325 struct nv30_screen *screen = nv30_screen(pscreen);
326 struct nouveau_object *eng3d = screen->eng3d;
327
328 switch (shader) {
329 case PIPE_SHADER_VERTEX:
330 switch (param) {
331 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
332 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
333 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
334 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
335 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
336 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
337 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
338 return 0;
339 case PIPE_SHADER_CAP_MAX_INPUTS:
340 case PIPE_SHADER_CAP_MAX_OUTPUTS:
341 return 16;
342 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
343 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
344 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
345 return 1;
346 case PIPE_SHADER_CAP_MAX_TEMPS:
347 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
348 case PIPE_SHADER_CAP_PREFERRED_IR:
349 return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
350 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
351 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
352 return 0;
353 case PIPE_SHADER_CAP_CONT_SUPPORTED:
354 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
355 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
356 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
359 case PIPE_SHADER_CAP_SUBROUTINES:
360 case PIPE_SHADER_CAP_INTEGERS:
361 case PIPE_SHADER_CAP_INT64_ATOMICS:
362 case PIPE_SHADER_CAP_FP16:
363 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
364 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
365 case PIPE_SHADER_CAP_INT16:
366 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
367 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
368 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
369 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
370 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
371 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
372 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
373 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
374 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
375 return 0;
376 case PIPE_SHADER_CAP_SUPPORTED_IRS:
377 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
378 default:
379 debug_printf("unknown vertex shader param %d\n", param);
380 return 0;
381 }
382 break;
383 case PIPE_SHADER_FRAGMENT:
384 switch (param) {
385 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
386 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
387 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
388 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
389 return 4096;
390 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
391 return 0;
392 case PIPE_SHADER_CAP_MAX_INPUTS:
393 return 8; /* should be possible to do 10 with nv4x */
394 case PIPE_SHADER_CAP_MAX_OUTPUTS:
395 return 4;
396 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
397 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
398 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
399 return 1;
400 case PIPE_SHADER_CAP_MAX_TEMPS:
401 return 32;
402 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
403 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
404 return 16;
405 case PIPE_SHADER_CAP_PREFERRED_IR:
406 return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
407 case PIPE_SHADER_CAP_CONT_SUPPORTED:
408 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
409 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
410 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
411 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
412 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
413 case PIPE_SHADER_CAP_SUBROUTINES:
414 case PIPE_SHADER_CAP_INTEGERS:
415 case PIPE_SHADER_CAP_FP16:
416 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
417 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
418 case PIPE_SHADER_CAP_INT16:
419 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
420 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
421 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
422 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
423 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
424 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
425 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
426 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
427 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
428 return 0;
429 case PIPE_SHADER_CAP_SUPPORTED_IRS:
430 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
431 default:
432 debug_printf("unknown fragment shader param %d\n", param);
433 return 0;
434 }
435 break;
436 default:
437 return 0;
438 }
439 }
440
441 static bool
nv30_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)442 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
443 enum pipe_format format,
444 enum pipe_texture_target target,
445 unsigned sample_count,
446 unsigned storage_sample_count,
447 unsigned bindings)
448 {
449 if (sample_count > nv30_screen(pscreen)->max_sample_count)
450 return false;
451
452 if (!(0x00000017 & (1 << sample_count)))
453 return false;
454
455 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
456 return false;
457
458 /* No way to render to a swizzled 3d texture. We don't necessarily know if
459 * it's swizzled or not here, but we have to assume anyways.
460 */
461 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
462 return false;
463
464 /* shared is always supported */
465 bindings &= ~PIPE_BIND_SHARED;
466
467 if (bindings & PIPE_BIND_INDEX_BUFFER) {
468 if (format != PIPE_FORMAT_R8_UINT &&
469 format != PIPE_FORMAT_R16_UINT &&
470 format != PIPE_FORMAT_R32_UINT)
471 return false;
472 bindings &= ~PIPE_BIND_INDEX_BUFFER;
473 }
474
475 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
476 }
477
478 static const nir_shader_compiler_options nv30_base_compiler_options = {
479 .fuse_ffma32 = true,
480 .fuse_ffma64 = true,
481 .lower_bitops = true,
482 .lower_extract_byte = true,
483 .lower_extract_word = true,
484 .lower_fdiv = true,
485 .lower_fsat = true,
486 .lower_insert_byte = true,
487 .lower_insert_word = true,
488 .lower_fdph = true,
489 .lower_flrp32 = true,
490 .lower_flrp64 = true,
491 .lower_fmod = true,
492 .lower_fpow = true, /* In hardware as of nv40 FS */
493 .lower_rotate = true,
494 .lower_uniforms_to_ubo = true,
495 .lower_vector_cmp = true,
496 .force_indirect_unrolling = nir_var_all,
497 .force_indirect_unrolling_sampler = true,
498 .max_unroll_iterations = 32,
499 .no_integers = true,
500
501 .use_interpolated_input_intrinsics = true,
502 };
503
504 static const void *
nv30_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)505 nv30_screen_get_compiler_options(struct pipe_screen *pscreen,
506 enum pipe_shader_ir ir,
507 enum pipe_shader_type shader)
508 {
509 struct nv30_screen *screen = nv30_screen(pscreen);
510 assert(ir == PIPE_SHADER_IR_NIR);
511
512 /* The FS compiler options are different between nv30 and nv40, and are set
513 * up at screen creation time.
514 */
515 if (shader == PIPE_SHADER_FRAGMENT)
516 return &screen->fs_compiler_options;
517
518 return &nv30_base_compiler_options;
519 }
520
521 static void
nv30_screen_fence_emit(struct pipe_screen * pscreen,uint32_t * sequence)522 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
523 {
524 struct nv30_screen *screen = nv30_screen(pscreen);
525 struct nouveau_pushbuf *push = screen->base.pushbuf;
526
527 *sequence = ++screen->base.fence.sequence;
528
529 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
530 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
531 (2 /* size */ << 18) | (7 /* subchan */ << 13));
532 PUSH_DATA (push, 0);
533 PUSH_DATA (push, *sequence);
534 }
535
536 static uint32_t
nv30_screen_fence_update(struct pipe_screen * pscreen)537 nv30_screen_fence_update(struct pipe_screen *pscreen)
538 {
539 struct nv30_screen *screen = nv30_screen(pscreen);
540 struct nv04_notify *fence = screen->fence->data;
541 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
542 }
543
544 static void
nv30_screen_destroy(struct pipe_screen * pscreen)545 nv30_screen_destroy(struct pipe_screen *pscreen)
546 {
547 struct nv30_screen *screen = nv30_screen(pscreen);
548
549 if (!nouveau_drm_screen_unref(&screen->base))
550 return;
551
552 nouveau_fence_cleanup(&screen->base);
553
554 nouveau_bo_ref(NULL, &screen->notify);
555
556 nouveau_heap_destroy(&screen->query_heap);
557 nouveau_heap_destroy(&screen->vp_exec_heap);
558 nouveau_heap_destroy(&screen->vp_data_heap);
559
560 nouveau_object_del(&screen->query);
561 nouveau_object_del(&screen->fence);
562 nouveau_object_del(&screen->ntfy);
563
564 nouveau_object_del(&screen->sifm);
565 nouveau_object_del(&screen->swzsurf);
566 nouveau_object_del(&screen->surf2d);
567 nouveau_object_del(&screen->m2mf);
568 nouveau_object_del(&screen->eng3d);
569 nouveau_object_del(&screen->null);
570
571 nouveau_screen_fini(&screen->base);
572 FREE(screen);
573 }
574
575 #define FAIL_SCREEN_INIT(str, err) \
576 do { \
577 NOUVEAU_ERR(str, err); \
578 screen->base.base.context_create = NULL; \
579 return &screen->base; \
580 } while(0)
581
582 struct nouveau_screen *
nv30_screen_create(struct nouveau_device * dev)583 nv30_screen_create(struct nouveau_device *dev)
584 {
585 struct nv30_screen *screen;
586 struct pipe_screen *pscreen;
587 struct nouveau_pushbuf *push;
588 struct nv04_fifo *fifo;
589 unsigned oclass = 0;
590 int ret, i;
591
592 switch (dev->chipset & 0xf0) {
593 case 0x30:
594 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
595 oclass = NV30_3D_CLASS;
596 else
597 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
598 oclass = NV34_3D_CLASS;
599 else
600 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
601 oclass = NV35_3D_CLASS;
602 break;
603 case 0x40:
604 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
605 oclass = NV40_3D_CLASS;
606 else
607 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
608 oclass = NV44_3D_CLASS;
609 break;
610 case 0x60:
611 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
612 oclass = NV44_3D_CLASS;
613 break;
614 default:
615 break;
616 }
617
618 if (!oclass) {
619 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
620 return NULL;
621 }
622
623 screen = CALLOC_STRUCT(nv30_screen);
624 if (!screen)
625 return NULL;
626
627 pscreen = &screen->base.base;
628 pscreen->destroy = nv30_screen_destroy;
629
630 /*
631 * Some modern apps try to use msaa without keeping in mind the
632 * restrictions on videomem of older cards. Resulting in dmesg saying:
633 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
634 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
635 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
636 *
637 * Because we are running out of video memory, after which the program
638 * using the msaa visual freezes, and eventually the entire system freezes.
639 *
640 * To work around this we do not allow msaa visauls by default and allow
641 * the user to override this via NV30_MAX_MSAA.
642 */
643 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
644 if (screen->max_sample_count > 4)
645 screen->max_sample_count = 4;
646
647 pscreen->get_param = nv30_screen_get_param;
648 pscreen->get_paramf = nv30_screen_get_paramf;
649 pscreen->get_shader_param = nv30_screen_get_shader_param;
650 pscreen->context_create = nv30_context_create;
651 pscreen->is_format_supported = nv30_screen_is_format_supported;
652 pscreen->get_compiler_options = nv30_screen_get_compiler_options;
653
654 nv30_resource_screen_init(pscreen);
655 nouveau_screen_init_vdec(&screen->base);
656
657 screen->base.fence.emit = nv30_screen_fence_emit;
658 screen->base.fence.update = nv30_screen_fence_update;
659
660 ret = nouveau_screen_init(&screen->base, dev);
661 if (ret)
662 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
663
664 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
665 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
666 if (oclass == NV40_3D_CLASS) {
667 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
668 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
669 }
670
671 screen->fs_compiler_options = nv30_base_compiler_options;
672 screen->fs_compiler_options.lower_fsat = false;
673 if (oclass >= NV40_3D_CLASS)
674 screen->fs_compiler_options.lower_fpow = false;
675
676 fifo = screen->base.channel->data;
677 push = screen->base.pushbuf;
678 push->rsvd_kick = 16;
679
680 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
681 NULL, 0, &screen->null);
682 if (ret)
683 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
684
685 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
686 * this means that the address pointed at by the DMA object must
687 * be 4KiB aligned, which means this object needs to be the first
688 * one allocated on the channel.
689 */
690 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
691 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
692 .length = 32 }, sizeof(struct nv04_notify),
693 &screen->fence);
694 if (ret)
695 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
696
697 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
698 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
699 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
700 .length = 32 }, sizeof(struct nv04_notify),
701 &screen->ntfy);
702 if (ret)
703 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
704
705 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
706 * the remainder of the "notifier block" assigned by the kernel for
707 * use as query objects
708 */
709 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
710 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
711 .length = 4096 - 128 }, sizeof(struct nv04_notify),
712 &screen->query);
713 if (ret)
714 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
715
716 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
717 if (ret)
718 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
719
720 list_inithead(&screen->queries);
721
722 /* Vertex program resources (code/data), currently 6 of the constant
723 * slots are reserved to implement user clipping planes
724 */
725 if (oclass < NV40_3D_CLASS) {
726 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
727 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
728 } else {
729 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
730 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
731 }
732
733 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
734 if (ret == 0)
735 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
736 if (ret)
737 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
738
739 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
740 NULL, 0, &screen->eng3d);
741 if (ret)
742 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
743
744 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
745 PUSH_DATA (push, screen->eng3d->handle);
746 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
747 PUSH_DATA (push, screen->ntfy->handle);
748 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
749 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
750 PUSH_DATA (push, fifo->vram); /* COLOR1 */
751 PUSH_DATA (push, screen->null->handle); /* UNK190 */
752 PUSH_DATA (push, fifo->vram); /* COLOR0 */
753 PUSH_DATA (push, fifo->vram); /* ZETA */
754 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
755 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
756 PUSH_DATA (push, screen->fence->handle); /* FENCE */
757 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
758 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
759 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
760 if (screen->eng3d->oclass < NV40_3D_CLASS) {
761 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
762 PUSH_DATA (push, 0x00100000);
763 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
764 PUSH_DATA (push, 3);
765
766 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
767 PUSH_DATA (push, 0);
768 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
769 PUSH_DATA (push, fui(0.0));
770 PUSH_DATA (push, fui(0.0));
771 PUSH_DATA (push, fui(1.0));
772 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
773 for (i = 0; i < 16; i++)
774 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
775
776 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
777 PUSH_DATA (push, 0);
778 } else {
779 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
780 PUSH_DATA (push, fifo->vram);
781 PUSH_DATA (push, fifo->vram); /* COLOR3 */
782
783 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
784 PUSH_DATA (push, 0x00000004);
785
786 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
787 PUSH_DATA (push, 0x00000010);
788 PUSH_DATA (push, 0x01000100);
789 PUSH_DATA (push, 0xff800006);
790
791 /* vtxprog output routing */
792 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
793 PUSH_DATA (push, 0x06144321);
794 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
795 PUSH_DATA (push, 0xedcba987);
796 PUSH_DATA (push, 0x0000006f);
797 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
798 PUSH_DATA (push, 0x00171615);
799 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
800 PUSH_DATA (push, 0x001b1a19);
801
802 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
803 PUSH_DATA (push, 0x0020ffff);
804 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
805 PUSH_DATA (push, 0x01d300d4);
806
807 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
808 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
809 }
810
811 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
812 NULL, 0, &screen->m2mf);
813 if (ret)
814 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
815
816 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
817 PUSH_DATA (push, screen->m2mf->handle);
818 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
819 PUSH_DATA (push, screen->ntfy->handle);
820
821 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
822 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
823 if (ret)
824 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
825
826 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
827 PUSH_DATA (push, screen->surf2d->handle);
828 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
829 PUSH_DATA (push, screen->ntfy->handle);
830
831 if (dev->chipset < 0x40)
832 oclass = NV30_SURFACE_SWZ_CLASS;
833 else
834 oclass = NV40_SURFACE_SWZ_CLASS;
835
836 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
837 NULL, 0, &screen->swzsurf);
838 if (ret)
839 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
840
841 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
842 PUSH_DATA (push, screen->swzsurf->handle);
843 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
844 PUSH_DATA (push, screen->ntfy->handle);
845
846 if (dev->chipset < 0x40)
847 oclass = NV30_SIFM_CLASS;
848 else
849 oclass = NV40_SIFM_CLASS;
850
851 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
852 NULL, 0, &screen->sifm);
853 if (ret)
854 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
855
856 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
857 PUSH_DATA (push, screen->sifm->handle);
858 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
859 PUSH_DATA (push, screen->ntfy->handle);
860 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
861 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
862
863 nouveau_pushbuf_kick(push, push->channel);
864
865 nouveau_fence_new(&screen->base, &screen->base.fence.current);
866 return &screen->base;
867 }
868