1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "head.h"
23 #include "base.h"
24 #include "core.h"
25 #include "curs.h"
26 #include "ovly.h"
27 #include "crc.h"
28
29 #include <nvif/class.h>
30 #include <nvif/event.h>
31 #include <nvif/cl0046.h>
32
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_vblank.h>
36 #include "nouveau_connector.h"
37
38 void
nv50_head_flush_clr(struct nv50_head * head,struct nv50_head_atom * asyh,bool flush)39 nv50_head_flush_clr(struct nv50_head *head,
40 struct nv50_head_atom *asyh, bool flush)
41 {
42 union nv50_head_atom_mask clr = {
43 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
44 };
45 if (clr.crc) nv50_crc_atomic_clr(head);
46 if (clr.olut) head->func->olut_clr(head);
47 if (clr.core) head->func->core_clr(head);
48 if (clr.curs) head->func->curs_clr(head);
49 }
50
51 void
nv50_head_flush_set_wndw(struct nv50_head * head,struct nv50_head_atom * asyh)52 nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)
53 {
54 if (asyh->set.curs ) head->func->curs_set(head, asyh);
55 if (asyh->set.olut ) {
56 asyh->olut.offset = nv50_lut_load(&head->olut,
57 asyh->olut.buffer,
58 asyh->state.gamma_lut,
59 asyh->olut.load);
60 head->func->olut_set(head, asyh);
61 }
62 }
63
64 void
nv50_head_flush_set(struct nv50_head * head,struct nv50_head_atom * asyh)65 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
66 {
67 if (asyh->set.view ) head->func->view (head, asyh);
68 if (asyh->set.mode ) head->func->mode (head, asyh);
69 if (asyh->set.core ) head->func->core_set(head, asyh);
70 if (asyh->set.base ) head->func->base (head, asyh);
71 if (asyh->set.ovly ) head->func->ovly (head, asyh);
72 if (asyh->set.dither ) head->func->dither (head, asyh);
73 if (asyh->set.procamp) head->func->procamp (head, asyh);
74 if (asyh->set.crc ) nv50_crc_atomic_set (head, asyh);
75 if (asyh->set.or ) head->func->or (head, asyh);
76 }
77
78 static void
nv50_head_atomic_check_procamp(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)79 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
80 struct nv50_head_atom *asyh,
81 struct nouveau_conn_atom *asyc)
82 {
83 const int vib = asyc->procamp.color_vibrance - 100;
84 const int hue = asyc->procamp.vibrant_hue - 90;
85 const int adj = (vib > 0) ? 50 : 0;
86 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
87 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
88 asyh->set.procamp = true;
89 }
90
91 static void
nv50_head_atomic_check_dither(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)92 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
93 struct nv50_head_atom *asyh,
94 struct nouveau_conn_atom *asyc)
95 {
96 u32 mode = 0x00;
97
98 if (asyc->dither.mode) {
99 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
100 if (asyh->base.depth > asyh->or.bpc * 3)
101 mode = DITHERING_MODE_DYNAMIC2X2;
102 } else {
103 mode = asyc->dither.mode;
104 }
105
106 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
107 if (asyh->or.bpc >= 8)
108 mode |= DITHERING_DEPTH_8BPC;
109 } else {
110 mode |= asyc->dither.depth;
111 }
112 }
113
114 asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
115 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
116 asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
117 asyh->set.dither = true;
118 }
119
120 static void
nv50_head_atomic_check_view(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)121 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
122 struct nv50_head_atom *asyh,
123 struct nouveau_conn_atom *asyc)
124 {
125 struct drm_connector *connector = asyc->state.connector;
126 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
127 struct drm_display_mode *umode = &asyh->state.mode;
128 int mode = asyc->scaler.mode;
129 struct edid *edid;
130 int umode_vdisplay, omode_hdisplay, omode_vdisplay;
131
132 if (connector->edid_blob_ptr)
133 edid = (struct edid *)connector->edid_blob_ptr->data;
134 else
135 edid = NULL;
136
137 if (!asyc->scaler.full) {
138 if (mode == DRM_MODE_SCALE_NONE)
139 omode = umode;
140 } else {
141 /* Non-EDID LVDS/eDP mode. */
142 mode = DRM_MODE_SCALE_FULLSCREEN;
143 }
144
145 /* For the user-specified mode, we must ignore doublescan and
146 * the like, but honor frame packing.
147 */
148 umode_vdisplay = umode->vdisplay;
149 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
150 umode_vdisplay += umode->vtotal;
151 asyh->view.iW = umode->hdisplay;
152 asyh->view.iH = umode_vdisplay;
153 /* For the output mode, we can just use the stock helper. */
154 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
155 asyh->view.oW = omode_hdisplay;
156 asyh->view.oH = omode_vdisplay;
157
158 /* Add overscan compensation if necessary, will keep the aspect
159 * ratio the same as the backend mode unless overridden by the
160 * user setting both hborder and vborder properties.
161 */
162 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
163 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
164 drm_detect_hdmi_monitor(edid)))) {
165 u32 bX = asyc->scaler.underscan.hborder;
166 u32 bY = asyc->scaler.underscan.vborder;
167 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
168
169 if (bX) {
170 asyh->view.oW -= (bX * 2);
171 if (bY) asyh->view.oH -= (bY * 2);
172 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
173 } else {
174 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
175 if (bY) asyh->view.oH -= (bY * 2);
176 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
177 }
178 }
179
180 /* Handle CENTER/ASPECT scaling, taking into account the areas
181 * removed already for overscan compensation.
182 */
183 switch (mode) {
184 case DRM_MODE_SCALE_CENTER:
185 /* NOTE: This will cause scaling when the input is
186 * larger than the output.
187 */
188 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
189 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
190 break;
191 case DRM_MODE_SCALE_ASPECT:
192 /* Determine whether the scaling should be on width or on
193 * height. This is done by comparing the aspect ratios of the
194 * sizes. If the output AR is larger than input AR, that means
195 * we want to change the width (letterboxed on the
196 * left/right), otherwise on the height (letterboxed on the
197 * top/bottom).
198 *
199 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
200 * screen will have letterboxes on the left/right. However a
201 * 16:9 (1.777) AR image on that same screen will have
202 * letterboxes on the top/bottom.
203 *
204 * inputAR = iW / iH; outputAR = oW / oH
205 * outputAR > inputAR is equivalent to oW * iH > iW * oH
206 */
207 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
208 /* Recompute output width, i.e. left/right letterbox */
209 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
210 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
211 } else {
212 /* Recompute output height, i.e. top/bottom letterbox */
213 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
214 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
215 }
216 break;
217 default:
218 break;
219 }
220
221 asyh->set.view = true;
222 }
223
224 static int
nv50_head_atomic_check_lut(struct nv50_head * head,struct nv50_head_atom * asyh)225 nv50_head_atomic_check_lut(struct nv50_head *head,
226 struct nv50_head_atom *asyh)
227 {
228 struct nv50_disp *disp = nv50_disp(head->base.base.dev);
229 struct drm_property_blob *olut = asyh->state.gamma_lut;
230 int size;
231
232 /* Determine whether core output LUT should be enabled. */
233 if (olut) {
234 /* Check if any window(s) have stolen the core output LUT
235 * to as an input LUT for legacy gamma + I8 colour format.
236 */
237 if (asyh->wndw.olut) {
238 /* If any window has stolen the core output LUT,
239 * all of them must.
240 */
241 if (asyh->wndw.olut != asyh->wndw.mask)
242 return -EINVAL;
243 olut = NULL;
244 }
245 }
246
247 if (!olut) {
248 if (!head->func->olut_identity) {
249 asyh->olut.handle = 0;
250 return 0;
251 }
252 size = 0;
253 } else {
254 size = drm_color_lut_size(olut);
255 }
256
257 if (!head->func->olut(head, asyh, size)) {
258 DRM_DEBUG_KMS("Invalid olut\n");
259 return -EINVAL;
260 }
261 asyh->olut.handle = disp->core->chan.vram.handle;
262 asyh->olut.buffer = !asyh->olut.buffer;
263
264 return 0;
265 }
266
267 static void
nv50_head_atomic_check_mode(struct nv50_head * head,struct nv50_head_atom * asyh)268 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
269 {
270 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
271 struct nv50_head_mode *m = &asyh->mode;
272 u32 blankus;
273
274 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
275
276 /*
277 * DRM modes are defined in terms of a repeating interval
278 * starting with the active display area. The hardware modes
279 * are defined in terms of a repeating interval starting one
280 * unit (pixel or line) into the sync pulse. So, add bias.
281 */
282
283 m->h.active = mode->crtc_htotal;
284 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
285 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
286 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
287
288 m->v.active = mode->crtc_vtotal;
289 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
290 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
291 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
292
293 /*XXX: Safe underestimate, even "0" works */
294 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
295 blankus *= 1000;
296 blankus /= mode->crtc_clock;
297 m->v.blankus = blankus;
298
299 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
300 m->v.blank2e = m->v.active + m->v.blanke;
301 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
302 m->v.active = (m->v.active * 2) + 1;
303 m->interlace = true;
304 } else {
305 m->v.blank2e = 0;
306 m->v.blank2s = 1;
307 m->interlace = false;
308 }
309 m->clock = mode->crtc_clock;
310
311 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
312 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
313 asyh->set.or = head->func->or != NULL;
314 asyh->set.mode = true;
315 }
316
317 static int
nv50_head_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)318 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
319 {
320 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
321 struct nv50_head *head = nv50_head(crtc);
322 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
323 struct nv50_head_atom *asyh = nv50_head_atom(state);
324 struct nouveau_conn_atom *asyc = NULL;
325 struct drm_connector_state *conns;
326 struct drm_connector *conn;
327 int i, ret;
328
329 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
330 if (asyh->state.active) {
331 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
332 if (conns->crtc == crtc) {
333 asyc = nouveau_conn_atom(conns);
334 break;
335 }
336 }
337
338 if (armh->state.active) {
339 if (asyc) {
340 if (asyh->state.mode_changed)
341 asyc->set.scaler = true;
342 if (armh->base.depth != asyh->base.depth)
343 asyc->set.dither = true;
344 }
345 } else {
346 if (asyc)
347 asyc->set.mask = ~0;
348 asyh->set.mask = ~0;
349 asyh->set.or = head->func->or != NULL;
350 }
351
352 if (asyh->state.mode_changed || asyh->state.connectors_changed)
353 nv50_head_atomic_check_mode(head, asyh);
354
355 if (asyh->state.color_mgmt_changed ||
356 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) {
357 int ret = nv50_head_atomic_check_lut(head, asyh);
358 if (ret)
359 return ret;
360
361 asyh->olut.visible = asyh->olut.handle != 0;
362 }
363
364 if (asyc) {
365 if (asyc->set.scaler)
366 nv50_head_atomic_check_view(armh, asyh, asyc);
367 if (asyc->set.dither)
368 nv50_head_atomic_check_dither(armh, asyh, asyc);
369 if (asyc->set.procamp)
370 nv50_head_atomic_check_procamp(armh, asyh, asyc);
371 }
372
373 if (head->func->core_calc) {
374 head->func->core_calc(head, asyh);
375 if (!asyh->core.visible)
376 asyh->olut.visible = false;
377 }
378
379 asyh->set.base = armh->base.cpp != asyh->base.cpp;
380 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
381 } else {
382 asyh->olut.visible = false;
383 asyh->core.visible = false;
384 asyh->curs.visible = false;
385 asyh->base.cpp = 0;
386 asyh->ovly.cpp = 0;
387 }
388
389 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
390 if (asyh->core.visible) {
391 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
392 asyh->set.core = true;
393 } else
394 if (armh->core.visible) {
395 asyh->clr.core = true;
396 }
397
398 if (asyh->curs.visible) {
399 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
400 asyh->set.curs = true;
401 } else
402 if (armh->curs.visible) {
403 asyh->clr.curs = true;
404 }
405
406 if (asyh->olut.visible) {
407 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
408 asyh->set.olut = true;
409 } else
410 if (armh->olut.visible) {
411 asyh->clr.olut = true;
412 }
413 } else {
414 asyh->clr.olut = armh->olut.visible;
415 asyh->clr.core = armh->core.visible;
416 asyh->clr.curs = armh->curs.visible;
417 asyh->set.olut = asyh->olut.visible;
418 asyh->set.core = asyh->core.visible;
419 asyh->set.curs = asyh->curs.visible;
420 }
421
422 ret = nv50_crc_atomic_check_head(head, asyh, armh);
423 if (ret)
424 return ret;
425
426 if (asyh->clr.mask || asyh->set.mask)
427 nv50_atom(asyh->state.state)->lock_core = true;
428 return 0;
429 }
430
431 static const struct drm_crtc_helper_funcs
432 nv50_head_help = {
433 .atomic_check = nv50_head_atomic_check,
434 .get_scanout_position = nouveau_display_scanoutpos,
435 };
436
437 static void
nv50_head_atomic_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)438 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
439 struct drm_crtc_state *state)
440 {
441 struct nv50_head_atom *asyh = nv50_head_atom(state);
442 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
443 kfree(asyh);
444 }
445
446 static struct drm_crtc_state *
nv50_head_atomic_duplicate_state(struct drm_crtc * crtc)447 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
448 {
449 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
450 struct nv50_head_atom *asyh;
451 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
452 return NULL;
453 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
454 asyh->wndw = armh->wndw;
455 asyh->view = armh->view;
456 asyh->mode = armh->mode;
457 asyh->olut = armh->olut;
458 asyh->core = armh->core;
459 asyh->curs = armh->curs;
460 asyh->base = armh->base;
461 asyh->ovly = armh->ovly;
462 asyh->dither = armh->dither;
463 asyh->procamp = armh->procamp;
464 asyh->crc = armh->crc;
465 asyh->or = armh->or;
466 asyh->dp = armh->dp;
467 asyh->clr.mask = 0;
468 asyh->set.mask = 0;
469 return &asyh->state;
470 }
471
472 static void
nv50_head_reset(struct drm_crtc * crtc)473 nv50_head_reset(struct drm_crtc *crtc)
474 {
475 struct nv50_head_atom *asyh;
476
477 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
478 return;
479
480 if (crtc->state)
481 nv50_head_atomic_destroy_state(crtc, crtc->state);
482
483 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
484 }
485
486 static int
nv50_head_late_register(struct drm_crtc * crtc)487 nv50_head_late_register(struct drm_crtc *crtc)
488 {
489 return nv50_head_crc_late_register(nv50_head(crtc));
490 }
491
492 static void
nv50_head_destroy(struct drm_crtc * crtc)493 nv50_head_destroy(struct drm_crtc *crtc)
494 {
495 struct nv50_head *head = nv50_head(crtc);
496
497 nvif_notify_dtor(&head->base.vblank);
498 nv50_lut_fini(&head->olut);
499 drm_crtc_cleanup(crtc);
500 kfree(head);
501 }
502
503 static const struct drm_crtc_funcs
504 nv50_head_func = {
505 .reset = nv50_head_reset,
506 .gamma_set = drm_atomic_helper_legacy_gamma_set,
507 .destroy = nv50_head_destroy,
508 .set_config = drm_atomic_helper_set_config,
509 .page_flip = drm_atomic_helper_page_flip,
510 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
511 .atomic_destroy_state = nv50_head_atomic_destroy_state,
512 .enable_vblank = nouveau_display_vblank_enable,
513 .disable_vblank = nouveau_display_vblank_disable,
514 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
515 .late_register = nv50_head_late_register,
516 };
517
518 static const struct drm_crtc_funcs
519 nvd9_head_func = {
520 .reset = nv50_head_reset,
521 .gamma_set = drm_atomic_helper_legacy_gamma_set,
522 .destroy = nv50_head_destroy,
523 .set_config = drm_atomic_helper_set_config,
524 .page_flip = drm_atomic_helper_page_flip,
525 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
526 .atomic_destroy_state = nv50_head_atomic_destroy_state,
527 .enable_vblank = nouveau_display_vblank_enable,
528 .disable_vblank = nouveau_display_vblank_disable,
529 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
530 .verify_crc_source = nv50_crc_verify_source,
531 .get_crc_sources = nv50_crc_get_sources,
532 .set_crc_source = nv50_crc_set_source,
533 .late_register = nv50_head_late_register,
534 };
535
nv50_head_vblank_handler(struct nvif_notify * notify)536 static int nv50_head_vblank_handler(struct nvif_notify *notify)
537 {
538 struct nouveau_crtc *nv_crtc =
539 container_of(notify, struct nouveau_crtc, vblank);
540
541 if (drm_crtc_handle_vblank(&nv_crtc->base))
542 nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
543
544 return NVIF_NOTIFY_KEEP;
545 }
546
547 struct nv50_head *
nv50_head_create(struct drm_device * dev,int index)548 nv50_head_create(struct drm_device *dev, int index)
549 {
550 struct nouveau_drm *drm = nouveau_drm(dev);
551 struct nv50_disp *disp = nv50_disp(dev);
552 struct nv50_head *head;
553 struct nv50_wndw *base, *ovly, *curs;
554 struct nouveau_crtc *nv_crtc;
555 struct drm_crtc *crtc;
556 const struct drm_crtc_funcs *funcs;
557 int ret;
558
559 head = kzalloc(sizeof(*head), GFP_KERNEL);
560 if (!head)
561 return ERR_PTR(-ENOMEM);
562
563 head->func = disp->core->func->head;
564 head->base.index = index;
565
566 if (disp->disp->object.oclass < GF110_DISP)
567 funcs = &nv50_head_func;
568 else
569 funcs = &nvd9_head_func;
570
571 if (disp->disp->object.oclass < GV100_DISP) {
572 ret = nv50_base_new(drm, head->base.index, &base);
573 ret = nv50_ovly_new(drm, head->base.index, &ovly);
574 } else {
575 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
576 head->base.index * 2 + 0, &base);
577 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
578 head->base.index * 2 + 1, &ovly);
579 }
580 if (ret == 0)
581 ret = nv50_curs_new(drm, head->base.index, &curs);
582 if (ret) {
583 kfree(head);
584 return ERR_PTR(ret);
585 }
586
587 nv_crtc = &head->base;
588 crtc = &nv_crtc->base;
589 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
590 funcs, "head-%d", head->base.index);
591 drm_crtc_helper_add(crtc, &nv50_head_help);
592 /* Keep the legacy gamma size at 256 to avoid compatibility issues */
593 drm_mode_crtc_set_gamma_size(crtc, 256);
594 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
595 disp->disp->object.oclass >= GF110_DISP,
596 head->func->olut_size);
597
598 if (head->func->olut_set) {
599 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
600 if (ret) {
601 nv50_head_destroy(crtc);
602 return ERR_PTR(ret);
603 }
604 }
605
606 ret = nvif_notify_ctor(&disp->disp->object, "kmsVbl", nv50_head_vblank_handler,
607 false, NV04_DISP_NTFY_VBLANK,
608 &(struct nvif_notify_head_req_v0) {
609 .head = nv_crtc->index,
610 },
611 sizeof(struct nvif_notify_head_req_v0),
612 sizeof(struct nvif_notify_head_rep_v0),
613 &nv_crtc->vblank);
614 if (ret)
615 return ERR_PTR(ret);
616
617 return head;
618 }
619