1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef OTX2_TXRX_H
12 #define OTX2_TXRX_H
13
14 #include <linux/etherdevice.h>
15 #include <linux/iommu.h>
16 #include <linux/if_vlan.h>
17
18 #define LBK_CHAN_BASE 0x000
19 #define SDP_CHAN_BASE 0x700
20 #define CGX_CHAN_BASE 0x800
21
22 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
23 #define OTX2_HEAD_ROOM OTX2_ALIGN
24
25 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
26 #define OTX2_MIN_MTU 64
27 #define OTX2_MAX_MTU (9212 - OTX2_ETH_HLEN)
28
29 #define OTX2_MAX_GSO_SEGS 255
30 #define OTX2_MAX_FRAGS_IN_SQE 9
31
32 /* Rx buffer size should be in multiples of 128bytes */
33 #define RCV_FRAG_LEN1(x) \
34 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
35 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
36
37 /* Prefer 2048 byte buffers for better last level cache
38 * utilization or data distribution across regions.
39 */
40 #define RCV_FRAG_LEN(x) \
41 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
42
43 #define DMA_BUFFER_LEN(x) \
44 ((x) - OTX2_HEAD_ROOM - \
45 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
46
47 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
48 * is equal to this value.
49 */
50 #define CQ_CQE_THRESH_DEFAULT 10
51
52 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
53 * is nonzero and this much time elapses after that.
54 */
55 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
56 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
57
58 /* Min number of CQs (of the ones mapped to this CINT)
59 * with valid CQEs.
60 */
61 #define CQ_QCOUNT_DEFAULT 1
62
63 struct queue_stats {
64 u64 bytes;
65 u64 pkts;
66 };
67
68 struct otx2_rcv_queue {
69 struct queue_stats stats;
70 };
71
72 struct sg_list {
73 u16 num_segs;
74 u64 skb;
75 u64 size[OTX2_MAX_FRAGS_IN_SQE];
76 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
77 };
78
79 struct otx2_snd_queue {
80 u8 aura_id;
81 u16 head;
82 u16 sqe_size;
83 u32 sqe_cnt;
84 u16 num_sqbs;
85 u16 sqe_thresh;
86 u8 sqe_per_sqb;
87 u64 io_addr;
88 u64 *aura_fc_addr;
89 u64 *lmt_addr;
90 void *sqe_base;
91 struct qmem *sqe;
92 struct qmem *tso_hdrs;
93 struct sg_list *sg;
94 struct qmem *timestamps;
95 struct queue_stats stats;
96 u16 sqb_count;
97 u64 *sqb_ptrs;
98 } ____cacheline_aligned_in_smp;
99
100 enum cq_type {
101 CQ_RX,
102 CQ_TX,
103 CQS_PER_CINT = 2, /* RQ + SQ */
104 };
105
106 struct otx2_cq_poll {
107 void *dev;
108 #define CINT_INVALID_CQ 255
109 u8 cint_idx;
110 u8 cq_ids[CQS_PER_CINT];
111 struct napi_struct napi;
112 };
113
114 struct otx2_pool {
115 struct qmem *stack;
116 struct qmem *fc_addr;
117 u16 rbsize;
118 };
119
120 struct otx2_cq_queue {
121 u8 cq_idx;
122 u8 cq_type;
123 u8 cint_idx; /* CQ interrupt id */
124 u8 refill_task_sched;
125 u16 cqe_size;
126 u16 pool_ptrs;
127 u32 cqe_cnt;
128 u32 cq_head;
129 void *cqe_base;
130 struct qmem *cqe;
131 struct otx2_pool *rbpool;
132 } ____cacheline_aligned_in_smp;
133
134 struct otx2_qset {
135 u32 rqe_cnt;
136 u32 sqe_cnt; /* Keep these two at top */
137 #define OTX2_MAX_CQ_CNT 64
138 u16 cq_cnt;
139 u16 xqe_size;
140 struct otx2_pool *pool;
141 struct otx2_cq_poll *napi;
142 struct otx2_cq_queue *cq;
143 struct otx2_snd_queue *sq;
144 struct otx2_rcv_queue *rq;
145 };
146
147 /* Translate IOVA to physical address */
otx2_iova_to_phys(void * iommu_domain,dma_addr_t dma_addr)148 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
149 {
150 /* Translation is installed only when IOMMU is present */
151 if (likely(iommu_domain))
152 return iommu_iova_to_phys(iommu_domain, dma_addr);
153 return dma_addr;
154 }
155
156 int otx2_napi_handler(struct napi_struct *napi, int budget);
157 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
158 struct sk_buff *skb, u16 qidx);
159 #endif /* OTX2_TXRX_H */
160