1 /*
2 * Copyright (C) 2020 Icecream95 <ixn@disroot.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "pan_ir.h"
25 #include "compiler/nir/nir_builder.h"
26
27 /* OpenCL uses 64-bit types for some intrinsic functions, including
28 * global_invocation_id(). This could be worked around during conversion to
29 * MIR, except that global_invocation_id is a vec3, and the 128-bit registers
30 * on Midgard can only hold a 64-bit vec2.
31 * Rather than attempting to add hacky 64-bit vec3 support, convert these
32 * intrinsics to 32-bit and add a cast back to 64-bit, and rely on NIR not
33 * vectorizing back to vec3.
34 */
35
36 static bool
nir_lower_64bit_intrin_instr(nir_builder * b,nir_instr * instr,void * data)37 nir_lower_64bit_intrin_instr(nir_builder *b, nir_instr *instr, void *data)
38 {
39 if (instr->type != nir_instr_type_intrinsic)
40 return false;
41
42 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
43
44 switch (intr->intrinsic) {
45 case nir_intrinsic_load_global_invocation_id:
46 case nir_intrinsic_load_global_invocation_id_zero_base:
47 case nir_intrinsic_load_workgroup_id:
48 case nir_intrinsic_load_num_workgroups:
49 break;
50
51 default:
52 return false;
53 }
54
55 if (nir_dest_bit_size(intr->dest) != 64)
56 return false;
57
58 b->cursor = nir_after_instr(instr);
59
60 assert(intr->dest.is_ssa);
61 intr->dest.ssa.bit_size = 32;
62
63 nir_ssa_def *conv = nir_u2u64(b, &intr->dest.ssa);
64
65 nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, conv,
66 conv->parent_instr);
67
68 return true;
69 }
70
71 bool
pan_nir_lower_64bit_intrin(nir_shader * shader)72 pan_nir_lower_64bit_intrin(nir_shader *shader)
73 {
74 return nir_shader_instructions_pass(shader,
75 nir_lower_64bit_intrin_instr,
76 nir_metadata_block_index | nir_metadata_dominance,
77 NULL);
78 }
79