1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Support for the xscale frame buffer.
4 *
5 * Author: Jean-Frederic Clere
6 * Created: Sep 22, 2003
7 * Copyright: jfclere@sinix.net
8 */
9
10 #include <linux/fb.h>
11 #include <mach/regs-lcd.h>
12
13 /*
14 * Supported LCD connections
15 *
16 * bits 0 - 3: for LCD panel type:
17 *
18 * STN - for passive matrix
19 * DSTN - for dual scan passive matrix
20 * TFT - for active matrix
21 *
22 * bits 4 - 9 : for bus width
23 * bits 10-17 : for AC Bias Pin Frequency
24 * bit 18 : for output enable polarity
25 * bit 19 : for pixel clock edge
26 * bit 20 : for output pixel format when base is RGBT16
27 */
28 #define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
29 #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
30
31 #define LCD_TYPE_MASK 0xf
32 #define LCD_TYPE_UNKNOWN 0
33 #define LCD_TYPE_MONO_STN 1
34 #define LCD_TYPE_MONO_DSTN 2
35 #define LCD_TYPE_COLOR_STN 3
36 #define LCD_TYPE_COLOR_DSTN 4
37 #define LCD_TYPE_COLOR_TFT 5
38 #define LCD_TYPE_SMART_PANEL 6
39 #define LCD_TYPE_MAX 7
40
41 #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
42 #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
43 #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
44 #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
45 #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
46 #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
47 #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
48 #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
49 #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
50 #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
51 #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
52
53 #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
54 #define LCD_BIAS_ACTIVE_HIGH (0 << 18)
55 #define LCD_BIAS_ACTIVE_LOW (1 << 18)
56 #define LCD_PCLK_EDGE_RISE (0 << 19)
57 #define LCD_PCLK_EDGE_FALL (1 << 19)
58 #define LCD_ALTERNATE_MAPPING (1 << 20)
59
60 /*
61 * This structure describes the machine which we are running on.
62 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
63 * of linux/drivers/video/pxafb.c
64 */
65 struct pxafb_mode_info {
66 u_long pixclock;
67
68 u_short xres;
69 u_short yres;
70
71 u_char bpp;
72 u_int cmap_greyscale:1,
73 depth:8,
74 transparency:1,
75 unused:22;
76
77 /* Parallel Mode Timing */
78 u_char hsync_len;
79 u_char left_margin;
80 u_char right_margin;
81
82 u_char vsync_len;
83 u_char upper_margin;
84 u_char lower_margin;
85 u_char sync;
86
87 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
88 * Note:
89 * 1. all parameters in nanosecond (ns)
90 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
91 * in pxa27x and pxa3xx, initialize them to the same value or
92 * the larger one will be used
93 * 3. same to {rd,wr}_pulse_width
94 *
95 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
96 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
97 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
98 */
99 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
100 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
101 unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
102 unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
103 unsigned cmd_inh_time; /* Command Inhibit time between two writes */
104 unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
105 };
106
107 struct pxafb_mach_info {
108 struct pxafb_mode_info *modes;
109 unsigned int num_modes;
110
111 unsigned int lcd_conn;
112 unsigned long video_mem_size;
113
114 u_int fixed_modes:1,
115 cmap_inverse:1,
116 cmap_static:1,
117 acceleration_enabled:1,
118 unused:28;
119
120 /* The following should be defined in LCCR0
121 * LCCR0_Act or LCCR0_Pas Active or Passive
122 * LCCR0_Sngl or LCCR0_Dual Single/Dual panel
123 * LCCR0_Mono or LCCR0_Color Mono/Color
124 * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
125 * LCCR0_DMADel(Tcpu) (optional) DMA request delay
126 *
127 * The following should not be defined in LCCR0:
128 * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
129 * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
130 */
131 u_int lccr0;
132 /* The following should be defined in LCCR3
133 * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
134 * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
135 * LCCR3_Acb(X) AB Bias pin frequency
136 * LCCR3_DPC (optional) Double Pixel Clock mode (untested)
137 *
138 * The following should not be defined in LCCR3
139 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
140 */
141 u_int lccr3;
142 /* The following should be defined in LCCR4
143 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
144 *
145 * All other bits in LCCR4 should be left alone.
146 */
147 u_int lccr4;
148 void (*pxafb_backlight_power)(int);
149 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
150 void (*smart_update)(struct fb_info *);
151 };
152
153 void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
154 unsigned long pxafb_get_hsync_time(struct device *dev);
155
156 #ifdef CONFIG_FB_PXA_SMARTPANEL
157 extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
158 extern int pxafb_smart_flush(struct fb_info *info);
159 #else
pxafb_smart_queue(struct fb_info * info,uint16_t * cmds,int n)160 static inline int pxafb_smart_queue(struct fb_info *info,
161 uint16_t *cmds, int n)
162 {
163 return 0;
164 }
165
pxafb_smart_flush(struct fb_info * info)166 static inline int pxafb_smart_flush(struct fb_info *info)
167 {
168 return 0;
169 }
170 #endif
171