1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * based on amdgpu winsys.
5 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #include "radv_amdgpu_winsys.h"
28 #include <assert.h>
29 #include <stdio.h>
30 #include <stdlib.h>
31 #include <string.h>
32 #include "drm-uapi/amdgpu_drm.h"
33 #include "ac_surface.h"
34 #include "radv_amdgpu_bo.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_surface.h"
37 #include "radv_amdgpu_winsys_public.h"
38 #include "radv_debug.h"
39 #include "vk_drm_syncobj.h"
40 #include "xf86drm.h"
41
42 static bool
do_winsys_init(struct radv_amdgpu_winsys * ws,int fd)43 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
44 {
45 if (!ac_query_gpu_info(fd, ws->dev, &ws->info))
46 return false;
47
48 if (ws->info.drm_minor < 23) {
49 fprintf(stderr, "radv/amdgpu: DRM 3.23+ is required (Linux kernel 4.15+)\n");
50 return false;
51 }
52
53 ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment);
54 if (!ws->addrlib) {
55 fprintf(stderr, "radv/amdgpu: Cannot create addrlib.\n");
56 return false;
57 }
58
59 ws->info.ip[AMD_IP_SDMA].num_queues = MIN2(ws->info.ip[AMD_IP_SDMA].num_queues, MAX_RINGS_PER_TYPE);
60 ws->info.ip[AMD_IP_COMPUTE].num_queues = MIN2(ws->info.ip[AMD_IP_COMPUTE].num_queues, MAX_RINGS_PER_TYPE);
61
62 ws->use_ib_bos = ws->info.gfx_level >= GFX7;
63 return true;
64 }
65
66 static void
radv_amdgpu_winsys_query_info(struct radeon_winsys * rws,struct radeon_info * info)67 radv_amdgpu_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
68 {
69 *info = ((struct radv_amdgpu_winsys *)rws)->info;
70 }
71
72 static uint64_t
radv_amdgpu_winsys_query_value(struct radeon_winsys * rws,enum radeon_value_id value)73 radv_amdgpu_winsys_query_value(struct radeon_winsys *rws, enum radeon_value_id value)
74 {
75 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
76 struct amdgpu_heap_info heap;
77 uint64_t retval = 0;
78
79 switch (value) {
80 case RADEON_ALLOCATED_VRAM:
81 return ws->allocated_vram;
82 case RADEON_ALLOCATED_VRAM_VIS:
83 return ws->allocated_vram_vis;
84 case RADEON_ALLOCATED_GTT:
85 return ws->allocated_gtt;
86 case RADEON_TIMESTAMP:
87 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
88 return retval;
89 case RADEON_NUM_BYTES_MOVED:
90 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
91 return retval;
92 case RADEON_NUM_EVICTIONS:
93 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
94 return retval;
95 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
96 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
97 return retval;
98 case RADEON_VRAM_USAGE:
99 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
100 return heap.heap_usage;
101 case RADEON_VRAM_VIS_USAGE:
102 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
103 &heap);
104 return heap.heap_usage;
105 case RADEON_GTT_USAGE:
106 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
107 return heap.heap_usage;
108 case RADEON_GPU_TEMPERATURE:
109 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
110 return retval;
111 case RADEON_CURRENT_SCLK:
112 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
113 return retval;
114 case RADEON_CURRENT_MCLK:
115 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
116 return retval;
117 default:
118 unreachable("invalid query value");
119 }
120
121 return 0;
122 }
123
124 static bool
radv_amdgpu_winsys_read_registers(struct radeon_winsys * rws,unsigned reg_offset,unsigned num_registers,uint32_t * out)125 radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset,
126 unsigned num_registers, uint32_t *out)
127 {
128 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
129
130 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0;
131 }
132
133 static const char *
radv_amdgpu_winsys_get_chip_name(struct radeon_winsys * rws)134 radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
135 {
136 amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
137
138 return amdgpu_get_marketing_name(dev);
139 }
140
141 static simple_mtx_t winsys_creation_mutex = _SIMPLE_MTX_INITIALIZER_NP;
142 static struct hash_table *winsyses = NULL;
143
144 static void
radv_amdgpu_winsys_destroy(struct radeon_winsys * rws)145 radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
146 {
147 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
148 bool destroy = false;
149
150 simple_mtx_lock(&winsys_creation_mutex);
151 if (!--ws->refcount) {
152 _mesa_hash_table_remove_key(winsyses, ws->dev);
153
154 /* Clean the hashtable up if empty, though there is no
155 * empty function. */
156 if (_mesa_hash_table_num_entries(winsyses) == 0) {
157 _mesa_hash_table_destroy(winsyses, NULL);
158 winsyses = NULL;
159 }
160
161 destroy = true;
162 }
163 simple_mtx_unlock(&winsys_creation_mutex);
164 if (!destroy)
165 return;
166
167 u_rwlock_destroy(&ws->global_bo_list.lock);
168 free(ws->global_bo_list.bos);
169
170 if (ws->reserve_vmid)
171 amdgpu_vm_unreserve_vmid(ws->dev, 0);
172
173 u_rwlock_destroy(&ws->log_bo_list_lock);
174 ac_addrlib_destroy(ws->addrlib);
175 amdgpu_device_deinitialize(ws->dev);
176 FREE(rws);
177 }
178
179 static int
radv_amdgpu_winsys_get_fd(struct radeon_winsys * rws)180 radv_amdgpu_winsys_get_fd(struct radeon_winsys *rws)
181 {
182 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
183 return amdgpu_device_get_fd(ws->dev);
184 }
185
186 static const struct vk_sync_type *const *
radv_amdgpu_winsys_get_sync_types(struct radeon_winsys * rws)187 radv_amdgpu_winsys_get_sync_types(struct radeon_winsys *rws)
188 {
189 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
190 return ws->sync_types;
191 }
192
193 struct radeon_winsys *
radv_amdgpu_winsys_create(int fd,uint64_t debug_flags,uint64_t perftest_flags,bool reserve_vmid)194 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags, bool reserve_vmid)
195 {
196 uint32_t drm_major, drm_minor, r;
197 amdgpu_device_handle dev;
198 struct radv_amdgpu_winsys *ws = NULL;
199
200 r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
201 if (r) {
202 fprintf(stderr, "radv/amdgpu: failed to initialize device.\n");
203 return NULL;
204 }
205
206 /* We have to keep this lock till insertion. */
207 simple_mtx_lock(&winsys_creation_mutex);
208 if (!winsyses)
209 winsyses = _mesa_pointer_hash_table_create(NULL);
210 if (!winsyses) {
211 fprintf(stderr, "radv/amdgpu: failed to alloc winsys hash table.\n");
212 goto fail;
213 }
214
215 struct hash_entry *entry = _mesa_hash_table_search(winsyses, dev);
216 if (entry) {
217 ws = (struct radv_amdgpu_winsys *)entry->data;
218 ++ws->refcount;
219 }
220
221 if (ws) {
222 simple_mtx_unlock(&winsys_creation_mutex);
223 amdgpu_device_deinitialize(dev);
224
225 /* Check that options don't differ from the existing winsys. */
226 if (((debug_flags & RADV_DEBUG_ALL_BOS) && !ws->debug_all_bos) ||
227 ((debug_flags & RADV_DEBUG_HANG) && !ws->debug_log_bos) ||
228 ((debug_flags & RADV_DEBUG_NO_IBS) && ws->use_ib_bos) ||
229 (perftest_flags != ws->perftest)) {
230 fprintf(stderr, "radv/amdgpu: Found options that differ from the existing winsys.\n");
231 return NULL;
232 }
233
234 /* RADV_DEBUG_ZERO_VRAM is the only option that is allowed to be set again. */
235 if (debug_flags & RADV_DEBUG_ZERO_VRAM)
236 ws->zero_all_vram_allocs = true;
237
238 return &ws->base;
239 }
240
241 ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
242 if (!ws)
243 goto fail;
244
245 ws->refcount = 1;
246 ws->dev = dev;
247 ws->info.drm_major = drm_major;
248 ws->info.drm_minor = drm_minor;
249 if (!do_winsys_init(ws, fd))
250 goto winsys_fail;
251
252 ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
253 ws->debug_log_bos = debug_flags & RADV_DEBUG_HANG;
254 if (debug_flags & RADV_DEBUG_NO_IBS)
255 ws->use_ib_bos = false;
256
257 ws->reserve_vmid = reserve_vmid;
258 if (ws->reserve_vmid) {
259 r = amdgpu_vm_reserve_vmid(dev, 0);
260 if (r) {
261 fprintf(stderr, "radv/amdgpu: failed to reserve vmid.\n");
262 goto vmid_fail;
263 }
264 }
265 int num_sync_types = 0;
266
267 ws->syncobj_sync_type = vk_drm_syncobj_get_type(amdgpu_device_get_fd(ws->dev));
268 if (ws->syncobj_sync_type.features) {
269 ws->sync_types[num_sync_types++] = &ws->syncobj_sync_type;
270 if (!(ws->syncobj_sync_type.features & VK_SYNC_FEATURE_TIMELINE)) {
271 ws->emulated_timeline_sync_type = vk_sync_timeline_get_type(&ws->syncobj_sync_type);
272 ws->sync_types[num_sync_types++] = &ws->emulated_timeline_sync_type.sync;
273 }
274 }
275
276 ws->sync_types[num_sync_types++] = NULL;
277 assert(num_sync_types <= ARRAY_SIZE(ws->sync_types));
278
279 ws->perftest = perftest_flags;
280 ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
281 u_rwlock_init(&ws->global_bo_list.lock);
282 list_inithead(&ws->log_bo_list);
283 u_rwlock_init(&ws->log_bo_list_lock);
284 ws->base.query_info = radv_amdgpu_winsys_query_info;
285 ws->base.query_value = radv_amdgpu_winsys_query_value;
286 ws->base.read_registers = radv_amdgpu_winsys_read_registers;
287 ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
288 ws->base.destroy = radv_amdgpu_winsys_destroy;
289 ws->base.get_fd = radv_amdgpu_winsys_get_fd;
290 ws->base.get_sync_types = radv_amdgpu_winsys_get_sync_types;
291 radv_amdgpu_bo_init_functions(ws);
292 radv_amdgpu_cs_init_functions(ws);
293 radv_amdgpu_surface_init_functions(ws);
294
295 _mesa_hash_table_insert(winsyses, dev, ws);
296 simple_mtx_unlock(&winsys_creation_mutex);
297
298 return &ws->base;
299
300 vmid_fail:
301 ac_addrlib_destroy(ws->addrlib);
302 winsys_fail:
303 free(ws);
304 fail:
305 if (winsyses && _mesa_hash_table_num_entries(winsyses) == 0) {
306 _mesa_hash_table_destroy(winsyses, NULL);
307 winsyses = NULL;
308 }
309 simple_mtx_unlock(&winsys_creation_mutex);
310 amdgpu_device_deinitialize(dev);
311 return NULL;
312 }
313