1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Ralink SoC register definitions
4 *
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 */
9
10 #ifndef _RALINK_REGS_H_
11 #define _RALINK_REGS_H_
12
13 #include <linux/io.h>
14
15 enum ralink_soc_type {
16 RALINK_UNKNOWN = 0,
17 RT2880_SOC,
18 RT3883_SOC,
19 RT305X_SOC_RT3050,
20 RT305X_SOC_RT3052,
21 RT305X_SOC_RT3350,
22 RT305X_SOC_RT3352,
23 RT305X_SOC_RT5350,
24 MT762X_SOC_MT7620A,
25 MT762X_SOC_MT7620N,
26 MT762X_SOC_MT7621AT,
27 MT762X_SOC_MT7628AN,
28 MT762X_SOC_MT7688,
29 };
30 extern enum ralink_soc_type ralink_soc;
31
32 extern __iomem void *rt_sysc_membase;
33 extern __iomem void *rt_memc_membase;
34
rt_sysc_w32(u32 val,unsigned reg)35 static inline void rt_sysc_w32(u32 val, unsigned reg)
36 {
37 __raw_writel(val, rt_sysc_membase + reg);
38 }
39
rt_sysc_r32(unsigned reg)40 static inline u32 rt_sysc_r32(unsigned reg)
41 {
42 return __raw_readl(rt_sysc_membase + reg);
43 }
44
rt_sysc_m32(u32 clr,u32 set,unsigned reg)45 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
46 {
47 u32 val = rt_sysc_r32(reg) & ~clr;
48
49 __raw_writel(val | set, rt_sysc_membase + reg);
50 }
51
rt_memc_w32(u32 val,unsigned reg)52 static inline void rt_memc_w32(u32 val, unsigned reg)
53 {
54 __raw_writel(val, rt_memc_membase + reg);
55 }
56
rt_memc_r32(unsigned reg)57 static inline u32 rt_memc_r32(unsigned reg)
58 {
59 return __raw_readl(rt_memc_membase + reg);
60 }
61
62 #endif /* _RALINK_REGS_H_ */
63