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1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2004-2005 Simtec Electronics
4 //	http://www.simtec.co.uk/products/SWLINUX/
5 //	Ben Dooks <ben@simtec.co.uk>
6 //
7 // Common code for S3C24XX machines
8 
9 #include <linux/dma-mapping.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14 #include <linux/serial_core.h>
15 #include <linux/serial_s3c.h>
16 #include <clocksource/samsung_pwm.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/platform_data/clk-s3c2410.h>
21 #include <linux/platform_data/dma-s3c24xx.h>
22 #include <linux/dmaengine.h>
23 #include <linux/clk/samsung.h>
24 
25 #include "hardware-s3c24xx.h"
26 #include "map.h"
27 #include "regs-clock.h"
28 #include <asm/irq.h>
29 #include <asm/cacheflush.h>
30 #include <asm/system_info.h>
31 #include <asm/system_misc.h>
32 
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 
36 #include "regs-gpio.h"
37 #include "dma-s3c24xx.h"
38 
39 #include "cpu.h"
40 #include "devs.h"
41 #include "pwm-core.h"
42 
43 #include "s3c24xx.h"
44 
45 /* table of supported CPUs */
46 
47 static const char name_s3c2410[]  = "S3C2410";
48 static const char name_s3c2412[]  = "S3C2412";
49 static const char name_s3c2416[]  = "S3C2416/S3C2450";
50 static const char name_s3c2440[]  = "S3C2440";
51 static const char name_s3c2442[]  = "S3C2442";
52 static const char name_s3c2442b[]  = "S3C2442B";
53 static const char name_s3c2443[]  = "S3C2443";
54 static const char name_s3c2410a[] = "S3C2410A";
55 static const char name_s3c2440a[] = "S3C2440A";
56 
57 static struct cpu_table cpu_ids[] __initdata = {
58 	{
59 		.idcode		= 0x32410000,
60 		.idmask		= 0xffffffff,
61 		.map_io		= s3c2410_map_io,
62 		.init_uarts	= s3c2410_init_uarts,
63 		.init		= s3c2410_init,
64 		.name		= name_s3c2410
65 	},
66 	{
67 		.idcode		= 0x32410002,
68 		.idmask		= 0xffffffff,
69 		.map_io		= s3c2410_map_io,
70 		.init_uarts	= s3c2410_init_uarts,
71 		.init		= s3c2410a_init,
72 		.name		= name_s3c2410a
73 	},
74 	{
75 		.idcode		= 0x32440000,
76 		.idmask		= 0xffffffff,
77 		.map_io		= s3c2440_map_io,
78 		.init_uarts	= s3c244x_init_uarts,
79 		.init		= s3c2440_init,
80 		.name		= name_s3c2440
81 	},
82 	{
83 		.idcode		= 0x32440001,
84 		.idmask		= 0xffffffff,
85 		.map_io		= s3c2440_map_io,
86 		.init_uarts	= s3c244x_init_uarts,
87 		.init		= s3c2440_init,
88 		.name		= name_s3c2440a
89 	},
90 	{
91 		.idcode		= 0x32440aaa,
92 		.idmask		= 0xffffffff,
93 		.map_io		= s3c2442_map_io,
94 		.init_uarts	= s3c244x_init_uarts,
95 		.init		= s3c2442_init,
96 		.name		= name_s3c2442
97 	},
98 	{
99 		.idcode		= 0x32440aab,
100 		.idmask		= 0xffffffff,
101 		.map_io		= s3c2442_map_io,
102 		.init_uarts	= s3c244x_init_uarts,
103 		.init		= s3c2442_init,
104 		.name		= name_s3c2442b
105 	},
106 	{
107 		.idcode		= 0x32412001,
108 		.idmask		= 0xffffffff,
109 		.map_io		= s3c2412_map_io,
110 		.init_uarts	= s3c2412_init_uarts,
111 		.init		= s3c2412_init,
112 		.name		= name_s3c2412,
113 	},
114 	{			/* a newer version of the s3c2412 */
115 		.idcode		= 0x32412003,
116 		.idmask		= 0xffffffff,
117 		.map_io		= s3c2412_map_io,
118 		.init_uarts	= s3c2412_init_uarts,
119 		.init		= s3c2412_init,
120 		.name		= name_s3c2412,
121 	},
122 	{			/* a strange version of the s3c2416 */
123 		.idcode		= 0x32450003,
124 		.idmask		= 0xffffffff,
125 		.map_io		= s3c2416_map_io,
126 		.init_uarts	= s3c2416_init_uarts,
127 		.init		= s3c2416_init,
128 		.name		= name_s3c2416,
129 	},
130 	{
131 		.idcode		= 0x32443001,
132 		.idmask		= 0xffffffff,
133 		.map_io		= s3c2443_map_io,
134 		.init_uarts	= s3c2443_init_uarts,
135 		.init		= s3c2443_init,
136 		.name		= name_s3c2443,
137 	},
138 };
139 
140 /* minimal IO mapping */
141 
142 static struct map_desc s3c_iodesc[] __initdata __maybe_unused = {
143 	IODESC_ENT(GPIO),
144 	IODESC_ENT(IRQ),
145 	IODESC_ENT(MEMCTRL),
146 	IODESC_ENT(UART)
147 };
148 
149 /* read cpu identificaiton code */
150 
s3c24xx_read_idcode_v5(void)151 static unsigned long s3c24xx_read_idcode_v5(void)
152 {
153 #if defined(CONFIG_CPU_S3C2416)
154 	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
155 
156 	u32 gs = __raw_readl(S3C24XX_GSTATUS1);
157 
158 	/* test for s3c2416 or similar device */
159 	if ((gs >> 16) == 0x3245)
160 		return gs;
161 #endif
162 
163 #if defined(CONFIG_CPU_S3C2412)
164 	return __raw_readl(S3C2412_GSTATUS1);
165 #else
166 	return 1UL;	/* don't look like an 2400 */
167 #endif
168 }
169 
s3c24xx_read_idcode_v4(void)170 static unsigned long s3c24xx_read_idcode_v4(void)
171 {
172 	return __raw_readl(S3C2410_GSTATUS1);
173 }
174 
s3c24xx_default_idle(void)175 static void s3c24xx_default_idle(void)
176 {
177 	unsigned long tmp = 0;
178 	int i;
179 
180 	/* idle the system by using the idle mode which will wait for an
181 	 * interrupt to happen before restarting the system.
182 	 */
183 
184 	/* Warning: going into idle state upsets jtag scanning */
185 
186 	__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
187 		     S3C2410_CLKCON);
188 
189 	/* the samsung port seems to do a loop and then unset idle.. */
190 	for (i = 0; i < 50; i++)
191 		tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
192 
193 	/* this bit is not cleared on re-start... */
194 
195 	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
196 		     S3C2410_CLKCON);
197 }
198 
199 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
200 	.bits		= 16,
201 	.div_base	= 1,
202 	.has_tint_cstat	= false,
203 	.tclk_mask	= (1 << 4),
204 };
205 
s3c24xx_init_io(struct map_desc * mach_desc,int size)206 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
207 {
208 	arm_pm_idle = s3c24xx_default_idle;
209 
210 	/* initialise the io descriptors we need for initialisation */
211 	iotable_init(mach_desc, size);
212 	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
213 
214 	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
215 		samsung_cpu_id = s3c24xx_read_idcode_v5();
216 	} else {
217 		samsung_cpu_id = s3c24xx_read_idcode_v4();
218 	}
219 
220 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
221 
222 	samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
223 }
224 
s3c24xx_set_timer_source(unsigned int event,unsigned int source)225 void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source)
226 {
227 	s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
228 	s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
229 }
230 
s3c24xx_timer_init(void)231 void __init s3c24xx_timer_init(void)
232 {
233 	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
234 		IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
235 	};
236 
237 	samsung_pwm_clocksource_init(S3C_VA_TIMER,
238 					timer_irqs, &s3c24xx_pwm_variant);
239 }
240 
241 /* Serial port registrations */
242 
243 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
244 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
245 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
246 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
247 
248 static struct resource s3c2410_uart0_resource[] = {
249 	[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
250 	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
251 			IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
252 			NULL, IORESOURCE_IRQ)
253 };
254 
255 static struct resource s3c2410_uart1_resource[] = {
256 	[0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
257 	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
258 			IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
259 			NULL, IORESOURCE_IRQ)
260 };
261 
262 static struct resource s3c2410_uart2_resource[] = {
263 	[0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
264 	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
265 			IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
266 			NULL, IORESOURCE_IRQ)
267 };
268 
269 static struct resource s3c2410_uart3_resource[] = {
270 	[0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
271 	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
272 			IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
273 			NULL, IORESOURCE_IRQ)
274 };
275 
276 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
277 	[0] = {
278 		.resources	= s3c2410_uart0_resource,
279 		.nr_resources	= ARRAY_SIZE(s3c2410_uart0_resource),
280 	},
281 	[1] = {
282 		.resources	= s3c2410_uart1_resource,
283 		.nr_resources	= ARRAY_SIZE(s3c2410_uart1_resource),
284 	},
285 	[2] = {
286 		.resources	= s3c2410_uart2_resource,
287 		.nr_resources	= ARRAY_SIZE(s3c2410_uart2_resource),
288 	},
289 	[3] = {
290 		.resources	= s3c2410_uart3_resource,
291 		.nr_resources	= ARRAY_SIZE(s3c2410_uart3_resource),
292 	},
293 };
294 
295 #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
296 
297 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
298 	defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
299 static struct resource s3c2410_dma_resource[] = {
300 	[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
301 	[1] = DEFINE_RES_IRQ(IRQ_DMA0),
302 	[2] = DEFINE_RES_IRQ(IRQ_DMA1),
303 	[3] = DEFINE_RES_IRQ(IRQ_DMA2),
304 	[4] = DEFINE_RES_IRQ(IRQ_DMA3),
305 };
306 #endif
307 
308 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
309 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
310 	[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
311 	[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
312 	[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
313 						S3C24XX_DMA_CHANREQ(2, 2) |
314 						S3C24XX_DMA_CHANREQ(1, 3),
315 	},
316 	[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
317 	[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
318 	[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
319 	[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
320 	[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
321 	[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
322 						 S3C24XX_DMA_CHANREQ(3, 2) |
323 						 S3C24XX_DMA_CHANREQ(3, 3),
324 	},
325 	[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
326 						  S3C24XX_DMA_CHANREQ(1, 2),
327 	},
328 	[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
329 	[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
330 	[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
331 	[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
332 	[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
333 };
334 
335 static const struct dma_slave_map s3c2410_dma_slave_map[] = {
336 	{ "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
337 	{ "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
338 	{ "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
339 	{ "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
340 	{ "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
341 	/*
342 	 * The DMA request source[1] (DMACH_UARTx_SRC2) are
343 	 * not used in the UART driver.
344 	 */
345 	{ "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
346 	{ "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
347 	{ "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
348 	{ "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
349 	{ "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
350 	{ "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
351 	{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
352 	{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
353 	{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
354 	{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
355 	{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
356 	{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
357 	{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
358 	{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
359 	{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
360 	{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
361 };
362 
363 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
364 	.num_phy_channels = 4,
365 	.channels = s3c2410_dma_channels,
366 	.num_channels = DMACH_MAX,
367 	.slave_map = s3c2410_dma_slave_map,
368 	.slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
369 };
370 
371 struct platform_device s3c2410_device_dma = {
372 	.name		= "s3c2410-dma",
373 	.id		= 0,
374 	.num_resources	= ARRAY_SIZE(s3c2410_dma_resource),
375 	.resource	= s3c2410_dma_resource,
376 	.dev	= {
377 		.dma_mask = &s3c24xx_device_dma_mask,
378 		.coherent_dma_mask = DMA_BIT_MASK(32),
379 		.platform_data = &s3c2410_dma_platdata,
380 	},
381 };
382 #endif
383 
384 #ifdef CONFIG_CPU_S3C2412
385 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
386 	[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
387 	[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
388 	[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
389 	[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
390 	[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
391 	[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
392 	[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
393 	[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
394 	[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
395 	[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
396 	[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
397 	[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
398 	[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
399 	[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
400 	[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
401 	[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
402 	[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
403 	[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
404 	[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
405 	[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
406 };
407 
408 static const struct dma_slave_map s3c2412_dma_slave_map[] = {
409 	{ "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
410 	{ "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
411 	{ "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
412 	{ "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
413 	{ "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
414 	{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
415 	{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
416 	{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
417 	{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
418 	{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
419 	{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
420 	{ "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
421 	{ "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
422 	{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
423 	{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
424 	{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
425 	{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
426 	{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
427 	{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
428 	{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
429 	{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
430 };
431 
432 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
433 	.num_phy_channels = 4,
434 	.channels = s3c2412_dma_channels,
435 	.num_channels = DMACH_MAX,
436 	.slave_map = s3c2412_dma_slave_map,
437 	.slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
438 };
439 
440 struct platform_device s3c2412_device_dma = {
441 	.name		= "s3c2412-dma",
442 	.id		= 0,
443 	.num_resources	= ARRAY_SIZE(s3c2410_dma_resource),
444 	.resource	= s3c2410_dma_resource,
445 	.dev	= {
446 		.dma_mask = &s3c24xx_device_dma_mask,
447 		.coherent_dma_mask = DMA_BIT_MASK(32),
448 		.platform_data = &s3c2412_dma_platdata,
449 	},
450 };
451 #endif
452 
453 #if defined(CONFIG_CPU_S3C2440)
454 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
455 	[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
456 	[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
457 	[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
458 						S3C24XX_DMA_CHANREQ(6, 1) |
459 						S3C24XX_DMA_CHANREQ(2, 2) |
460 						S3C24XX_DMA_CHANREQ(1, 3),
461 	},
462 	[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
463 	[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
464 	[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
465 	[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
466 	[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
467 	[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
468 						 S3C24XX_DMA_CHANREQ(3, 2) |
469 						 S3C24XX_DMA_CHANREQ(3, 3),
470 	},
471 	[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
472 						  S3C24XX_DMA_CHANREQ(1, 2),
473 	},
474 	[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
475 						   S3C24XX_DMA_CHANREQ(0, 2),
476 	},
477 	[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
478 						  S3C24XX_DMA_CHANREQ(5, 2),
479 	},
480 	[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
481 						  S3C24XX_DMA_CHANREQ(6, 3),
482 	},
483 	[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
484 						  S3C24XX_DMA_CHANREQ(5, 3),
485 	},
486 	[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
487 	[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
488 	[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
489 	[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
490 };
491 
492 static const struct dma_slave_map s3c2440_dma_slave_map[] = {
493 	/* TODO: DMACH_XD0 */
494 	/* TODO: DMACH_XD1 */
495 	{ "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
496 	{ "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
497 	{ "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
498 	{ "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
499 	{ "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
500 	{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
501 	{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
502 	{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
503 	{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
504 	{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
505 	{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
506 	{ "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
507 	{ "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
508 	/* TODO: DMACH_TIMER */
509 	{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
510 	{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
511 	{ "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
512 	{ "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
513 	{ "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
514 	{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
515 	{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
516 	{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
517 	{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
518 	{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
519 	{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
520 	{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
521 	{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
522 };
523 
524 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
525 	.num_phy_channels = 4,
526 	.channels = s3c2440_dma_channels,
527 	.num_channels = DMACH_MAX,
528 	.slave_map = s3c2440_dma_slave_map,
529 	.slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
530 };
531 
532 struct platform_device s3c2440_device_dma = {
533 	.name		= "s3c2410-dma",
534 	.id		= 0,
535 	.num_resources	= ARRAY_SIZE(s3c2410_dma_resource),
536 	.resource	= s3c2410_dma_resource,
537 	.dev	= {
538 		.dma_mask = &s3c24xx_device_dma_mask,
539 		.coherent_dma_mask = DMA_BIT_MASK(32),
540 		.platform_data = &s3c2440_dma_platdata,
541 	},
542 };
543 #endif
544 
545 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
546 static struct resource s3c2443_dma_resource[] = {
547 	[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
548 	[1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
549 	[2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
550 	[3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
551 	[4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
552 	[5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
553 	[6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
554 };
555 
556 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
557 	[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
558 	[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
559 	[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
560 	[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
561 	[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
562 	[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
563 	[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
564 	[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
565 	[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
566 	[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
567 	[DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
568 	[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
569 	[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
570 	[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
571 	[DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
572 	[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
573 	[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
574 	[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
575 	[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
576 	[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
577 	[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
578 };
579 
580 static const struct dma_slave_map s3c2443_dma_slave_map[] = {
581 	{ "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
582 	{ "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
583 	{ "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
584 	{ "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
585 	{ "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
586 	{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
587 	{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
588 	{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
589 	{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
590 	{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
591 	{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
592 	{ "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
593 	{ "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
594 	{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
595 	{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
596 };
597 
598 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
599 	.num_phy_channels = 6,
600 	.channels = s3c2443_dma_channels,
601 	.num_channels = DMACH_MAX,
602 	.slave_map = s3c2443_dma_slave_map,
603 	.slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
604 };
605 
606 struct platform_device s3c2443_device_dma = {
607 	.name		= "s3c2443-dma",
608 	.id		= 0,
609 	.num_resources	= ARRAY_SIZE(s3c2443_dma_resource),
610 	.resource	= s3c2443_dma_resource,
611 	.dev	= {
612 		.dma_mask = &s3c24xx_device_dma_mask,
613 		.coherent_dma_mask = DMA_BIT_MASK(32),
614 		.platform_data = &s3c2443_dma_platdata,
615 	},
616 };
617 #endif
618 
619 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
s3c2410_init_clocks(int xtal)620 void __init s3c2410_init_clocks(int xtal)
621 {
622 	s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
623 }
624 #endif
625 
626 #ifdef CONFIG_CPU_S3C2412
s3c2412_init_clocks(int xtal)627 void __init s3c2412_init_clocks(int xtal)
628 {
629 	s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
630 }
631 #endif
632 
633 #ifdef CONFIG_CPU_S3C2416
s3c2416_init_clocks(int xtal)634 void __init s3c2416_init_clocks(int xtal)
635 {
636 	s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
637 }
638 #endif
639 
640 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
s3c2440_init_clocks(int xtal)641 void __init s3c2440_init_clocks(int xtal)
642 {
643 	s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
644 }
645 #endif
646 
647 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
s3c2442_init_clocks(int xtal)648 void __init s3c2442_init_clocks(int xtal)
649 {
650 	s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
651 }
652 #endif
653 
654 #ifdef CONFIG_CPU_S3C2443
s3c2443_init_clocks(int xtal)655 void __init s3c2443_init_clocks(int xtal)
656 {
657 	s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
658 }
659 #endif
660 
661 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
662 	defined(CONFIG_CPU_S3C2442)
663 static struct resource s3c2410_dclk_resource[] = {
664 	[0] = DEFINE_RES_MEM(0x56000084, 0x4),
665 };
666 
667 static struct s3c2410_clk_platform_data s3c_clk_platform_data = {
668 	.modify_misccr = s3c2410_modify_misccr,
669 };
670 
671 struct platform_device s3c2410_device_dclk = {
672 	.name		= "s3c2410-dclk",
673 	.id		= 0,
674 	.num_resources	= ARRAY_SIZE(s3c2410_dclk_resource),
675 	.resource	= s3c2410_dclk_resource,
676 	.dev		= {
677 		.platform_data = &s3c_clk_platform_data,
678 	},
679 };
680 #endif
681