1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * Copyright 2020 Valve Corporation 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef AC_RGP_H 27 #define AC_RGP_H 28 29 #include <stdint.h> 30 #include "compiler/shader_enums.h" 31 #include "util/list.h" 32 #include "util/simple_mtx.h" 33 34 struct radeon_info; 35 struct ac_thread_trace; 36 struct ac_thread_trace_data; 37 struct ac_spm_trace_data; 38 39 enum rgp_hardware_stages { 40 RGP_HW_STAGE_VS = 0, 41 RGP_HW_STAGE_LS, 42 RGP_HW_STAGE_HS, 43 RGP_HW_STAGE_ES, 44 RGP_HW_STAGE_GS, 45 RGP_HW_STAGE_PS, 46 RGP_HW_STAGE_CS, 47 RGP_HW_STAGE_MAX, 48 }; 49 50 struct rgp_shader_data { 51 uint64_t hash[2]; 52 uint32_t code_size; 53 uint8_t *code; 54 uint32_t vgpr_count; 55 uint32_t sgpr_count; 56 uint32_t scratch_memory_size; 57 uint32_t wavefront_size; 58 uint64_t base_address; 59 uint32_t elf_symbol_offset; 60 uint32_t hw_stage; 61 uint32_t is_combined; 62 }; 63 64 struct rgp_code_object_record { 65 uint32_t shader_stages_mask; 66 struct rgp_shader_data shader_data[MESA_VULKAN_SHADER_STAGES]; 67 uint32_t num_shaders_combined; /* count combined shaders as one count */ 68 uint64_t pipeline_hash[2]; 69 struct list_head list; 70 }; 71 72 struct rgp_code_object { 73 uint32_t record_count; 74 struct list_head record; 75 simple_mtx_t lock; 76 }; 77 78 enum rgp_loader_event_type 79 { 80 RGP_LOAD_TO_GPU_MEMORY = 0, 81 RGP_UNLOAD_FROM_GPU_MEMORY, 82 }; 83 84 struct rgp_loader_events_record { 85 uint32_t loader_event_type; 86 uint32_t reserved; 87 uint64_t base_address; 88 uint64_t code_object_hash[2]; 89 uint64_t time_stamp; 90 struct list_head list; 91 }; 92 93 struct rgp_loader_events { 94 uint32_t record_count; 95 struct list_head record; 96 simple_mtx_t lock; 97 }; 98 99 struct rgp_pso_correlation_record { 100 uint64_t api_pso_hash; 101 uint64_t pipeline_hash[2]; 102 char api_level_obj_name[64]; 103 struct list_head list; 104 }; 105 106 struct rgp_pso_correlation { 107 uint32_t record_count; 108 struct list_head record; 109 simple_mtx_t lock; 110 }; 111 112 enum sqtt_queue_type { 113 SQTT_QUEUE_TYPE_UNKNOWN = 0x0, 114 SQTT_QUEUE_TYPE_UNIVERSAL = 0x1, 115 SQTT_QUEUE_TYPE_COMPUTE = 0x2, 116 SQTT_QUEUE_TYPE_DMA = 0x3, 117 }; 118 119 enum sqtt_engine_type { 120 SQTT_ENGINE_TYPE_UNKNOWN = 0x0, 121 SQTT_ENGINE_TYPE_UNIVERSAL = 0x1, 122 SQTT_ENGINE_TYPE_COMPUTE = 0x2, 123 SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = 0x3, 124 SQTT_ENGINE_TYPE_DMA = 0x4, 125 SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = 0x7, 126 SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = 0x8, 127 }; 128 129 struct sqtt_queue_hardware_info { 130 union { 131 struct { 132 enum sqtt_queue_type queue_type : 8; 133 enum sqtt_engine_type engine_type : 8; 134 uint32_t reserved : 16; 135 }; 136 uint32_t value; 137 }; 138 }; 139 140 struct rgp_queue_info_record { 141 uint64_t queue_id; 142 uint64_t queue_context; 143 struct sqtt_queue_hardware_info hardware_info; 144 uint32_t reserved; 145 struct list_head list; 146 }; 147 148 struct rgp_queue_info { 149 uint32_t record_count; 150 struct list_head record; 151 simple_mtx_t lock; 152 }; 153 154 enum sqtt_queue_event_type { 155 SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT, 156 SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE, 157 SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE, 158 SQTT_QUEUE_TIMING_EVENT_PRESENT 159 }; 160 161 struct rgp_queue_event_record { 162 enum sqtt_queue_event_type event_type; 163 uint32_t sqtt_cb_id; 164 uint64_t frame_index; 165 uint32_t queue_info_index; 166 uint32_t submit_sub_index; 167 uint64_t api_id; 168 uint64_t cpu_timestamp; 169 uint64_t gpu_timestamps[2]; 170 struct list_head list; 171 }; 172 173 struct rgp_queue_event { 174 uint32_t record_count; 175 struct list_head record; 176 simple_mtx_t lock; 177 }; 178 179 struct rgp_clock_calibration_record { 180 uint64_t cpu_timestamp; 181 uint64_t gpu_timestamp; 182 struct list_head list; 183 }; 184 185 struct rgp_clock_calibration { 186 uint32_t record_count; 187 struct list_head record; 188 simple_mtx_t lock; 189 }; 190 191 int 192 ac_dump_rgp_capture(struct radeon_info *info, 193 struct ac_thread_trace *thread_trace, 194 const struct ac_spm_trace_data *spm_trace); 195 196 void 197 ac_rgp_file_write_elf_object(FILE *output, size_t file_elf_start, 198 struct rgp_code_object_record *record, 199 uint32_t *written_size, uint32_t flags); 200 201 #endif 202