1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
8
9 #include <linux/bitops.h>
10 #include <linux/mtd/cfi.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/spi/spi-mem.h>
13
14 /*
15 * Note on opcode nomenclature: some opcodes have a format like
16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
17 * of I/O lines used for the opcode, address, and data (respectively). The
18 * FUNCTION has an optional suffix of '4', to represent an opcode which
19 * requires a 4-byte (32-bit) address.
20 */
21
22 /* Flash opcodes. */
23 #define SPINOR_OP_WRDI 0x04 /* Write disable */
24 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
28 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
29 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
30 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
37 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
40 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
41 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
45 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
47 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
48 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
49 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
50 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
51 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
52 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
53 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
54
55 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
56 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
57 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
58 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
59 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
60 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
61 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
62 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
63 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
64 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
65 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
66 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
67 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
68 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
69 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
70 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
71 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
72
73 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
74 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
75 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
76 #define SPINOR_OP_READ_1_4_4_DTR 0xed
77
78 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
79 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
80 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
81
82 /* Used for SST flashes only. */
83 #define SPINOR_OP_BP 0x02 /* Byte program */
84 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
85
86 /* Used for S3AN flashes only */
87 #define SPINOR_OP_XSE 0x50 /* Sector erase */
88 #define SPINOR_OP_XPP 0x82 /* Page program */
89 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
90
91 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
92 #define XSR_RDY BIT(7) /* Ready */
93
94
95 /* Used for Macronix and Winbond flashes. */
96 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
97 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
98
99 /* Used for Spansion flashes only. */
100 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
101 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
102
103 /* Used for Micron flashes only. */
104 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
105 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
106
107 /* Status Register bits. */
108 #define SR_WIP BIT(0) /* Write in progress */
109 #define SR_WEL BIT(1) /* Write enable latch */
110 /* meaning of other SR_* bits may differ between vendors */
111 #define SR_BP0 BIT(2) /* Block protect 0 */
112 #define SR_BP1 BIT(3) /* Block protect 1 */
113 #define SR_BP2 BIT(4) /* Block protect 2 */
114 #define SR_BP3 BIT(5) /* Block protect 3 */
115 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
116 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
117 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
118 #define SR_SRWD BIT(7) /* SR write protect */
119 /* Spansion/Cypress specific status bits */
120 #define SR_E_ERR BIT(5)
121 #define SR_P_ERR BIT(6)
122
123 #define SR1_QUAD_EN_BIT6 BIT(6)
124
125 #define SR_BP_SHIFT 2
126
127 /* Enhanced Volatile Configuration Register bits */
128 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
129
130 /* Flag Status Register bits */
131 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
132 #define FSR_E_ERR BIT(5) /* Erase operation status */
133 #define FSR_P_ERR BIT(4) /* Program operation status */
134 #define FSR_PT_ERR BIT(1) /* Protection error bit */
135
136 /* Status Register 2 bits. */
137 #define SR2_QUAD_EN_BIT1 BIT(1)
138 #define SR2_QUAD_EN_BIT7 BIT(7)
139
140 /* Supported SPI protocols */
141 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
142 #define SNOR_PROTO_INST_SHIFT 16
143 #define SNOR_PROTO_INST(_nbits) \
144 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
145 SNOR_PROTO_INST_MASK)
146
147 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
148 #define SNOR_PROTO_ADDR_SHIFT 8
149 #define SNOR_PROTO_ADDR(_nbits) \
150 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
151 SNOR_PROTO_ADDR_MASK)
152
153 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
154 #define SNOR_PROTO_DATA_SHIFT 0
155 #define SNOR_PROTO_DATA(_nbits) \
156 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
157 SNOR_PROTO_DATA_MASK)
158
159 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
160
161 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
162 (SNOR_PROTO_INST(_inst_nbits) | \
163 SNOR_PROTO_ADDR(_addr_nbits) | \
164 SNOR_PROTO_DATA(_data_nbits))
165 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
166 (SNOR_PROTO_IS_DTR | \
167 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
168
169 enum spi_nor_protocol {
170 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
171 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
172 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
173 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
174 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
175 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
176 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
177 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
178 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
179 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
180
181 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
182 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
183 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
184 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
185 };
186
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)187 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
188 {
189 return !!(proto & SNOR_PROTO_IS_DTR);
190 }
191
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)192 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
193 {
194 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
195 SNOR_PROTO_INST_SHIFT;
196 }
197
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)198 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
199 {
200 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
201 SNOR_PROTO_ADDR_SHIFT;
202 }
203
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)204 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
205 {
206 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
207 SNOR_PROTO_DATA_SHIFT;
208 }
209
spi_nor_get_protocol_width(enum spi_nor_protocol proto)210 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
211 {
212 return spi_nor_get_protocol_data_nbits(proto);
213 }
214
215 /**
216 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
217 * supported by the SPI controller (bus master).
218 * @mask: the bitmask listing all the supported hw capabilies
219 */
220 struct spi_nor_hwcaps {
221 u32 mask;
222 };
223
224 /*
225 *(Fast) Read capabilities.
226 * MUST be ordered by priority: the higher bit position, the higher priority.
227 * As a matter of performances, it is relevant to use Octal SPI protocols first,
228 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
229 * (Slow) Read.
230 */
231 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
232 #define SNOR_HWCAPS_READ BIT(0)
233 #define SNOR_HWCAPS_READ_FAST BIT(1)
234 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
235
236 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
237 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
238 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
239 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
240 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
241
242 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
243 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
244 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
245 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
246 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
247
248 #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
249 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
250 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
251 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
252 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
253
254 /*
255 * Page Program capabilities.
256 * MUST be ordered by priority: the higher bit position, the higher priority.
257 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
258 * legacy SPI 1-1-1 protocol.
259 * Note that Dual Page Programs are not supported because there is no existing
260 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
261 * implements such commands.
262 */
263 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
264 #define SNOR_HWCAPS_PP BIT(16)
265
266 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
267 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
268 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
269 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
270
271 #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
272 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
273 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
274 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
275
276 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
277 SNOR_HWCAPS_READ_4_4_4 | \
278 SNOR_HWCAPS_READ_8_8_8 | \
279 SNOR_HWCAPS_PP_4_4_4 | \
280 SNOR_HWCAPS_PP_8_8_8)
281
282 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
283 SNOR_HWCAPS_READ_1_2_2_DTR | \
284 SNOR_HWCAPS_READ_1_4_4_DTR | \
285 SNOR_HWCAPS_READ_1_8_8_DTR)
286
287 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
288 SNOR_HWCAPS_PP_MASK)
289
290 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
291 struct spi_nor;
292
293 /**
294 * struct spi_nor_controller_ops - SPI NOR controller driver specific
295 * operations.
296 * @prepare: [OPTIONAL] do some preparations for the
297 * read/write/erase/lock/unlock operations.
298 * @unprepare: [OPTIONAL] do some post work after the
299 * read/write/erase/lock/unlock operations.
300 * @read_reg: read out the register.
301 * @write_reg: write data to the register.
302 * @read: read data from the SPI NOR.
303 * @write: write data to the SPI NOR.
304 * @erase: erase a sector of the SPI NOR at the offset @offs; if
305 * not provided by the driver, SPI NOR will send the erase
306 * opcode via write_reg().
307 */
308 struct spi_nor_controller_ops {
309 int (*prepare)(struct spi_nor *nor);
310 void (*unprepare)(struct spi_nor *nor);
311 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
312 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
313 size_t len);
314
315 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
316 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
317 const u8 *buf);
318 int (*erase)(struct spi_nor *nor, loff_t offs);
319 };
320
321 /*
322 * Forward declarations that are used internally by the core and manufacturer
323 * drivers.
324 */
325 struct flash_info;
326 struct spi_nor_manufacturer;
327 struct spi_nor_flash_parameter;
328
329 /**
330 * struct spi_nor - Structure for defining the SPI NOR layer
331 * @mtd: an mtd_info structure
332 * @lock: the lock for the read/write/erase/lock/unlock operations
333 * @dev: pointer to an SPI device or an SPI NOR controller device
334 * @spimem: pointer to the SPI memory device
335 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
336 * layer is not DMA-able
337 * @bouncebuf_size: size of the bounce buffer
338 * @info: SPI NOR part JEDEC MFR ID and other info
339 * @manufacturer: SPI NOR manufacturer
340 * @page_size: the page size of the SPI NOR
341 * @addr_width: number of address bytes
342 * @erase_opcode: the opcode for erasing a sector
343 * @read_opcode: the read opcode
344 * @read_dummy: the dummy needed by the read operation
345 * @program_opcode: the program opcode
346 * @sst_write_second: used by the SST write operation
347 * @flags: flag options for the current SPI NOR (SNOR_F_*)
348 * @read_proto: the SPI protocol for read operations
349 * @write_proto: the SPI protocol for write operations
350 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
351 * @controller_ops: SPI NOR controller driver specific operations.
352 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
353 * The structure includes legacy flash parameters and
354 * settings that can be overwritten by the spi_nor_fixups
355 * hooks, or dynamically when parsing the SFDP tables.
356 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
357 * @priv: pointer to the private data
358 */
359 struct spi_nor {
360 struct mtd_info mtd;
361 struct mutex lock;
362 struct device *dev;
363 struct spi_mem *spimem;
364 u8 *bouncebuf;
365 size_t bouncebuf_size;
366 const struct flash_info *info;
367 const struct spi_nor_manufacturer *manufacturer;
368 u32 page_size;
369 u8 addr_width;
370 u8 erase_opcode;
371 u8 read_opcode;
372 u8 read_dummy;
373 u8 program_opcode;
374 enum spi_nor_protocol read_proto;
375 enum spi_nor_protocol write_proto;
376 enum spi_nor_protocol reg_proto;
377 bool sst_write_second;
378 u32 flags;
379
380 const struct spi_nor_controller_ops *controller_ops;
381
382 struct spi_nor_flash_parameter *params;
383
384 struct {
385 struct spi_mem_dirmap_desc *rdesc;
386 struct spi_mem_dirmap_desc *wdesc;
387 } dirmap;
388
389 void *priv;
390 };
391
spi_nor_set_flash_node(struct spi_nor * nor,struct device_node * np)392 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
393 struct device_node *np)
394 {
395 mtd_set_of_node(&nor->mtd, np);
396 }
397
spi_nor_get_flash_node(struct spi_nor * nor)398 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
399 {
400 return mtd_get_of_node(&nor->mtd);
401 }
402
403 /**
404 * spi_nor_scan() - scan the SPI NOR
405 * @nor: the spi_nor structure
406 * @name: the chip type name
407 * @hwcaps: the hardware capabilities supported by the controller driver
408 *
409 * The drivers can use this fuction to scan the SPI NOR.
410 * In the scanning, it will try to get all the necessary information to
411 * fill the mtd_info{} and the spi_nor{}.
412 *
413 * The chip type name can be provided through the @name parameter.
414 *
415 * Return: 0 for success, others for failure.
416 */
417 int spi_nor_scan(struct spi_nor *nor, const char *name,
418 const struct spi_nor_hwcaps *hwcaps);
419
420 /**
421 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
422 * @nor: the spi_nor structure
423 */
424 void spi_nor_restore(struct spi_nor *nor);
425
426 #endif
427