1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #ifndef TU_PIPELINE_H
11 #define TU_PIPELINE_H
12
13 #include "tu_common.h"
14
15 #include "tu_cs.h"
16 #include "tu_descriptor_set.h"
17 #include "tu_shader.h"
18 #include "tu_suballoc.h"
19
20 enum tu_dynamic_state
21 {
22 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
23 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
24 TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
25 TU_DYNAMIC_STATE_RB_STENCIL_CNTL,
26 TU_DYNAMIC_STATE_VB_STRIDE,
27 TU_DYNAMIC_STATE_RASTERIZER_DISCARD,
28 TU_DYNAMIC_STATE_BLEND,
29 TU_DYNAMIC_STATE_COUNT,
30 /* no associated draw state: */
31 TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY = TU_DYNAMIC_STATE_COUNT,
32 TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE,
33 TU_DYNAMIC_STATE_LOGIC_OP,
34 TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE,
35 /* re-use the line width enum as it uses GRAS_SU_CNTL: */
36 TU_DYNAMIC_STATE_GRAS_SU_CNTL = VK_DYNAMIC_STATE_LINE_WIDTH,
37 };
38
39 struct cache_entry;
40
41 struct tu_pipeline_cache
42 {
43 struct vk_object_base base;
44
45 struct tu_device *device;
46 pthread_mutex_t mutex;
47
48 uint32_t total_size;
49 uint32_t table_size;
50 uint32_t kernel_count;
51 struct cache_entry **hash_table;
52 bool modified;
53
54 VkAllocationCallbacks alloc;
55 };
56 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, base, VkPipelineCache,
57 VK_OBJECT_TYPE_PIPELINE_CACHE)
58
59 struct tu_lrz_pipeline
60 {
61 uint32_t force_disable_mask;
62 bool fs_has_kill;
63 bool force_late_z;
64 bool early_fragment_tests;
65 };
66
67 struct tu_compiled_shaders
68 {
69 struct vk_pipeline_cache_object base;
70
71 struct tu_push_constant_range push_consts[MESA_SHADER_STAGES];
72 uint8_t active_desc_sets;
73 bool multi_pos_output;
74
75 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
76 };
77
78 extern const struct vk_pipeline_cache_object_ops tu_shaders_ops;
79
80 static bool inline
tu6_shared_constants_enable(const struct tu_pipeline_layout * layout,const struct ir3_compiler * compiler)81 tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
82 const struct ir3_compiler *compiler)
83 {
84 return layout->push_constant_size > 0 &&
85 layout->push_constant_size <= (compiler->shared_consts_size * 16);
86 }
87
88 struct tu_program_descriptor_linkage
89 {
90 struct ir3_const_state const_state;
91
92 uint32_t constlen;
93
94 struct tu_push_constant_range push_consts;
95 };
96
97 struct tu_pipeline_executable {
98 gl_shader_stage stage;
99
100 struct ir3_info stats;
101 bool is_binning;
102
103 char *nir_from_spirv;
104 char *nir_final;
105 char *disasm;
106 };
107
108 struct tu_pipeline
109 {
110 struct vk_object_base base;
111
112 struct tu_cs cs;
113 struct tu_suballoc_bo bo;
114
115 /* Separate BO for private memory since it should GPU writable */
116 struct tu_bo *pvtmem_bo;
117
118 bool need_indirect_descriptor_sets;
119 VkShaderStageFlags active_stages;
120 uint32_t active_desc_sets;
121
122 /* mask of enabled dynamic states
123 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
124 */
125 uint32_t dynamic_state_mask;
126 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
127
128 /* for dynamic states which use the same register: */
129 uint32_t gras_su_cntl, gras_su_cntl_mask;
130 uint32_t rb_depth_cntl, rb_depth_cntl_mask;
131 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask;
132 uint32_t pc_raster_cntl, pc_raster_cntl_mask;
133 uint32_t vpc_unknown_9107, vpc_unknown_9107_mask;
134 uint32_t stencil_wrmask;
135
136 unsigned num_rts;
137 uint32_t rb_mrt_control[MAX_RTS], rb_mrt_control_mask;
138 uint32_t rb_mrt_blend_control[MAX_RTS];
139 uint32_t sp_blend_cntl, sp_blend_cntl_mask;
140 uint32_t rb_blend_cntl, rb_blend_cntl_mask;
141 uint32_t color_write_enable, blend_enable;
142 bool logic_op_enabled, rop_reads_dst;
143 bool rasterizer_discard;
144
145 bool rb_depth_cntl_disable;
146
147 enum a5xx_line_mode line_mode;
148
149 /* draw states for the pipeline */
150 struct tu_draw_state load_state, rast_state;
151 struct tu_draw_state prim_order_state_sysmem, prim_order_state_gmem;
152
153 /* for vertex buffers state */
154 uint32_t num_vbs;
155
156 struct tu_push_constant_range shared_consts;
157
158 struct
159 {
160 struct tu_draw_state config_state;
161 struct tu_draw_state state;
162 struct tu_draw_state binning_state;
163
164 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
165 } program;
166
167 struct
168 {
169 struct tu_draw_state state;
170 struct tu_draw_state binning_state;
171 } vi;
172
173 struct
174 {
175 enum pc_di_primtype primtype;
176 bool primitive_restart;
177 } ia;
178
179 struct
180 {
181 uint32_t patch_type;
182 uint32_t param_stride;
183 bool upper_left_domain_origin;
184 } tess;
185
186 struct
187 {
188 uint32_t local_size[3];
189 uint32_t subgroup_size;
190 } compute;
191
192 bool provoking_vertex_last;
193
194 struct tu_lrz_pipeline lrz;
195
196 /* In other words - framebuffer fetch support */
197 bool raster_order_attachment_access;
198 bool subpass_feedback_loop_ds;
199
200 bool z_negative_one_to_one;
201
202 /* memory bandwidth cost (in bytes) for color attachments */
203 uint32_t color_bandwidth_per_sample;
204
205 uint32_t depth_cpp_per_sample;
206 uint32_t stencil_cpp_per_sample;
207
208 void *executables_mem_ctx;
209 /* tu_pipeline_executable */
210 struct util_dynarray executables;
211 };
212 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
213 VK_OBJECT_TYPE_PIPELINE)
214
215 void
216 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport, uint32_t num_viewport,
217 bool z_negative_one_to_one);
218
219 void
220 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scs, uint32_t scissor_count);
221
222 void
223 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
224
225 void
226 tu6_emit_depth_bias(struct tu_cs *cs,
227 float constant_factor,
228 float clamp,
229 float slope_factor);
230
231 uint32_t tu6_rb_mrt_control_rop(VkLogicOp op, bool *rop_reads_dst);
232
233 struct tu_pvtmem_config {
234 uint64_t iova;
235 uint32_t per_fiber_size;
236 uint32_t per_sp_size;
237 bool per_wave;
238 };
239
240 void
241 tu6_emit_xs_config(struct tu_cs *cs,
242 gl_shader_stage stage,
243 const struct ir3_shader_variant *xs);
244
245 void
246 tu6_emit_xs(struct tu_cs *cs,
247 gl_shader_stage stage,
248 const struct ir3_shader_variant *xs,
249 const struct tu_pvtmem_config *pvtmem,
250 uint64_t binary_iova);
251
252 void
253 tu6_emit_vpc(struct tu_cs *cs,
254 const struct ir3_shader_variant *vs,
255 const struct ir3_shader_variant *hs,
256 const struct ir3_shader_variant *ds,
257 const struct ir3_shader_variant *gs,
258 const struct ir3_shader_variant *fs,
259 uint32_t patch_control_points);
260
261 void
262 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
263
264 #endif /* TU_PIPELINE_H */
265