1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/device.h>
8 #include <linux/kobject.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/sys_soc.h>
18
19 #include <soc/tegra/common.h>
20 #include <soc/tegra/fuse.h>
21
22 #include "fuse.h"
23
24 struct tegra_sku_info tegra_sku_info;
25 EXPORT_SYMBOL(tegra_sku_info);
26
27 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
28 [TEGRA_REVISION_UNKNOWN] = "unknown",
29 [TEGRA_REVISION_A01] = "A01",
30 [TEGRA_REVISION_A02] = "A02",
31 [TEGRA_REVISION_A03] = "A03",
32 [TEGRA_REVISION_A03p] = "A03 prime",
33 [TEGRA_REVISION_A04] = "A04",
34 };
35
36 static const struct of_device_id car_match[] __initconst = {
37 { .compatible = "nvidia,tegra20-car", },
38 { .compatible = "nvidia,tegra30-car", },
39 { .compatible = "nvidia,tegra114-car", },
40 { .compatible = "nvidia,tegra124-car", },
41 { .compatible = "nvidia,tegra132-car", },
42 { .compatible = "nvidia,tegra210-car", },
43 {},
44 };
45
46 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
47 .base = NULL,
48 .soc = NULL,
49 };
50
51 static const struct of_device_id tegra_fuse_match[] = {
52 #ifdef CONFIG_ARCH_TEGRA_234_SOC
53 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
54 #endif
55 #ifdef CONFIG_ARCH_TEGRA_194_SOC
56 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
57 #endif
58 #ifdef CONFIG_ARCH_TEGRA_186_SOC
59 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
60 #endif
61 #ifdef CONFIG_ARCH_TEGRA_210_SOC
62 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
63 #endif
64 #ifdef CONFIG_ARCH_TEGRA_132_SOC
65 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
66 #endif
67 #ifdef CONFIG_ARCH_TEGRA_124_SOC
68 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
69 #endif
70 #ifdef CONFIG_ARCH_TEGRA_114_SOC
71 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
72 #endif
73 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
74 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
75 #endif
76 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
77 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
78 #endif
79 { /* sentinel */ }
80 };
81
tegra_fuse_read(void * priv,unsigned int offset,void * value,size_t bytes)82 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
83 size_t bytes)
84 {
85 unsigned int count = bytes / 4, i;
86 struct tegra_fuse *fuse = priv;
87 u32 *buffer = value;
88
89 for (i = 0; i < count; i++)
90 buffer[i] = fuse->read(fuse, offset + i * 4);
91
92 return 0;
93 }
94
95 static const struct nvmem_cell_info tegra_fuse_cells[] = {
96 {
97 .name = "tsensor-cpu1",
98 .offset = 0x084,
99 .bytes = 4,
100 .bit_offset = 0,
101 .nbits = 32,
102 }, {
103 .name = "tsensor-cpu2",
104 .offset = 0x088,
105 .bytes = 4,
106 .bit_offset = 0,
107 .nbits = 32,
108 }, {
109 .name = "tsensor-cpu0",
110 .offset = 0x098,
111 .bytes = 4,
112 .bit_offset = 0,
113 .nbits = 32,
114 }, {
115 .name = "xusb-pad-calibration",
116 .offset = 0x0f0,
117 .bytes = 4,
118 .bit_offset = 0,
119 .nbits = 32,
120 }, {
121 .name = "tsensor-cpu3",
122 .offset = 0x12c,
123 .bytes = 4,
124 .bit_offset = 0,
125 .nbits = 32,
126 }, {
127 .name = "sata-calibration",
128 .offset = 0x124,
129 .bytes = 1,
130 .bit_offset = 0,
131 .nbits = 2,
132 }, {
133 .name = "tsensor-gpu",
134 .offset = 0x154,
135 .bytes = 4,
136 .bit_offset = 0,
137 .nbits = 32,
138 }, {
139 .name = "tsensor-mem0",
140 .offset = 0x158,
141 .bytes = 4,
142 .bit_offset = 0,
143 .nbits = 32,
144 }, {
145 .name = "tsensor-mem1",
146 .offset = 0x15c,
147 .bytes = 4,
148 .bit_offset = 0,
149 .nbits = 32,
150 }, {
151 .name = "tsensor-pllx",
152 .offset = 0x160,
153 .bytes = 4,
154 .bit_offset = 0,
155 .nbits = 32,
156 }, {
157 .name = "tsensor-common",
158 .offset = 0x180,
159 .bytes = 4,
160 .bit_offset = 0,
161 .nbits = 32,
162 }, {
163 .name = "tsensor-realignment",
164 .offset = 0x1fc,
165 .bytes = 4,
166 .bit_offset = 0,
167 .nbits = 32,
168 }, {
169 .name = "gpu-calibration",
170 .offset = 0x204,
171 .bytes = 4,
172 .bit_offset = 0,
173 .nbits = 32,
174 }, {
175 .name = "xusb-pad-calibration-ext",
176 .offset = 0x250,
177 .bytes = 4,
178 .bit_offset = 0,
179 .nbits = 32,
180 },
181 };
182
tegra_fuse_probe(struct platform_device * pdev)183 static int tegra_fuse_probe(struct platform_device *pdev)
184 {
185 void __iomem *base = fuse->base;
186 struct nvmem_config nvmem;
187 struct resource *res;
188 int err;
189
190 /* take over the memory region from the early initialization */
191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
192 fuse->phys = res->start;
193 fuse->base = devm_ioremap_resource(&pdev->dev, res);
194 if (IS_ERR(fuse->base)) {
195 err = PTR_ERR(fuse->base);
196 fuse->base = base;
197 return err;
198 }
199
200 fuse->clk = devm_clk_get(&pdev->dev, "fuse");
201 if (IS_ERR(fuse->clk)) {
202 if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
203 dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
204 PTR_ERR(fuse->clk));
205
206 fuse->base = base;
207 return PTR_ERR(fuse->clk);
208 }
209
210 platform_set_drvdata(pdev, fuse);
211 fuse->dev = &pdev->dev;
212
213 if (fuse->soc->probe) {
214 err = fuse->soc->probe(fuse);
215 if (err < 0)
216 goto restore;
217 }
218
219 memset(&nvmem, 0, sizeof(nvmem));
220 nvmem.dev = &pdev->dev;
221 nvmem.name = "fuse";
222 nvmem.id = -1;
223 nvmem.owner = THIS_MODULE;
224 nvmem.cells = tegra_fuse_cells;
225 nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
226 nvmem.type = NVMEM_TYPE_OTP;
227 nvmem.read_only = true;
228 nvmem.root_only = true;
229 nvmem.reg_read = tegra_fuse_read;
230 nvmem.size = fuse->soc->info->size;
231 nvmem.word_size = 4;
232 nvmem.stride = 4;
233 nvmem.priv = fuse;
234
235 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
236 if (IS_ERR(fuse->nvmem)) {
237 err = PTR_ERR(fuse->nvmem);
238 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
239 err);
240 goto restore;
241 }
242
243 /* release the early I/O memory mapping */
244 iounmap(base);
245
246 return 0;
247
248 restore:
249 fuse->base = base;
250 return err;
251 }
252
253 static struct platform_driver tegra_fuse_driver = {
254 .driver = {
255 .name = "tegra-fuse",
256 .of_match_table = tegra_fuse_match,
257 .suppress_bind_attrs = true,
258 },
259 .probe = tegra_fuse_probe,
260 };
261 builtin_platform_driver(tegra_fuse_driver);
262
tegra_fuse_read_spare(unsigned int spare)263 u32 __init tegra_fuse_read_spare(unsigned int spare)
264 {
265 unsigned int offset = fuse->soc->info->spare + spare * 4;
266
267 return fuse->read_early(fuse, offset) & 1;
268 }
269
tegra_fuse_read_early(unsigned int offset)270 u32 __init tegra_fuse_read_early(unsigned int offset)
271 {
272 return fuse->read_early(fuse, offset);
273 }
274
tegra_fuse_readl(unsigned long offset,u32 * value)275 int tegra_fuse_readl(unsigned long offset, u32 *value)
276 {
277 if (!fuse->read || !fuse->clk)
278 return -EPROBE_DEFER;
279
280 if (IS_ERR(fuse->clk))
281 return PTR_ERR(fuse->clk);
282
283 *value = fuse->read(fuse, offset);
284
285 return 0;
286 }
287 EXPORT_SYMBOL(tegra_fuse_readl);
288
tegra_enable_fuse_clk(void __iomem * base)289 static void tegra_enable_fuse_clk(void __iomem *base)
290 {
291 u32 reg;
292
293 reg = readl_relaxed(base + 0x48);
294 reg |= 1 << 28;
295 writel(reg, base + 0x48);
296
297 /*
298 * Enable FUSE clock. This needs to be hardcoded because the clock
299 * subsystem is not active during early boot.
300 */
301 reg = readl(base + 0x14);
302 reg |= 1 << 7;
303 writel(reg, base + 0x14);
304 }
305
major_show(struct device * dev,struct device_attribute * attr,char * buf)306 static ssize_t major_show(struct device *dev, struct device_attribute *attr,
307 char *buf)
308 {
309 return sprintf(buf, "%d\n", tegra_get_major_rev());
310 }
311
312 static DEVICE_ATTR_RO(major);
313
minor_show(struct device * dev,struct device_attribute * attr,char * buf)314 static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
315 char *buf)
316 {
317 return sprintf(buf, "%d\n", tegra_get_minor_rev());
318 }
319
320 static DEVICE_ATTR_RO(minor);
321
322 static struct attribute *tegra_soc_attr[] = {
323 &dev_attr_major.attr,
324 &dev_attr_minor.attr,
325 NULL,
326 };
327
328 const struct attribute_group tegra_soc_attr_group = {
329 .attrs = tegra_soc_attr,
330 };
331
332 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
333 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
platform_show(struct device * dev,struct device_attribute * attr,char * buf)334 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
335 char *buf)
336 {
337 /*
338 * Displays the value in the 'pre_si_platform' field of the HIDREV
339 * register for Tegra194 devices. A value of 0 indicates that the
340 * platform type is silicon and all other non-zero values indicate
341 * the type of simulation platform is being used.
342 */
343 return sprintf(buf, "%d\n", tegra_get_platform());
344 }
345
346 static DEVICE_ATTR_RO(platform);
347
348 static struct attribute *tegra194_soc_attr[] = {
349 &dev_attr_major.attr,
350 &dev_attr_minor.attr,
351 &dev_attr_platform.attr,
352 NULL,
353 };
354
355 const struct attribute_group tegra194_soc_attr_group = {
356 .attrs = tegra194_soc_attr,
357 };
358 #endif
359
tegra_soc_device_register(void)360 struct device * __init tegra_soc_device_register(void)
361 {
362 struct soc_device_attribute *attr;
363 struct soc_device *dev;
364
365 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
366 if (!attr)
367 return NULL;
368
369 attr->family = kasprintf(GFP_KERNEL, "Tegra");
370 attr->revision = kasprintf(GFP_KERNEL, "%s",
371 tegra_revision_name[tegra_sku_info.revision]);
372 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
373 attr->custom_attr_group = fuse->soc->soc_attr_group;
374
375 dev = soc_device_register(attr);
376 if (IS_ERR(dev)) {
377 kfree(attr->soc_id);
378 kfree(attr->revision);
379 kfree(attr->family);
380 kfree(attr);
381 return ERR_CAST(dev);
382 }
383
384 return soc_device_to_device(dev);
385 }
386
tegra_init_fuse(void)387 static int __init tegra_init_fuse(void)
388 {
389 const struct of_device_id *match;
390 struct device_node *np;
391 struct resource regs;
392
393 tegra_init_apbmisc();
394
395 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
396 if (!np) {
397 /*
398 * Fall back to legacy initialization for 32-bit ARM only. All
399 * 64-bit ARM device tree files for Tegra are required to have
400 * a FUSE node.
401 *
402 * This is for backwards-compatibility with old device trees
403 * that didn't contain a FUSE node.
404 */
405 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
406 u8 chip = tegra_get_chip_id();
407
408 regs.start = 0x7000f800;
409 regs.end = 0x7000fbff;
410 regs.flags = IORESOURCE_MEM;
411
412 switch (chip) {
413 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
414 case TEGRA20:
415 fuse->soc = &tegra20_fuse_soc;
416 break;
417 #endif
418
419 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
420 case TEGRA30:
421 fuse->soc = &tegra30_fuse_soc;
422 break;
423 #endif
424
425 #ifdef CONFIG_ARCH_TEGRA_114_SOC
426 case TEGRA114:
427 fuse->soc = &tegra114_fuse_soc;
428 break;
429 #endif
430
431 #ifdef CONFIG_ARCH_TEGRA_124_SOC
432 case TEGRA124:
433 fuse->soc = &tegra124_fuse_soc;
434 break;
435 #endif
436
437 default:
438 pr_warn("Unsupported SoC: %02x\n", chip);
439 break;
440 }
441 } else {
442 /*
443 * At this point we're not running on Tegra, so play
444 * nice with multi-platform kernels.
445 */
446 return 0;
447 }
448 } else {
449 /*
450 * Extract information from the device tree if we've found a
451 * matching node.
452 */
453 if (of_address_to_resource(np, 0, ®s) < 0) {
454 pr_err("failed to get FUSE register\n");
455 return -ENXIO;
456 }
457
458 fuse->soc = match->data;
459 }
460
461 np = of_find_matching_node(NULL, car_match);
462 if (np) {
463 void __iomem *base = of_iomap(np, 0);
464 if (base) {
465 tegra_enable_fuse_clk(base);
466 iounmap(base);
467 } else {
468 pr_err("failed to map clock registers\n");
469 return -ENXIO;
470 }
471 }
472
473 fuse->base = ioremap(regs.start, resource_size(®s));
474 if (!fuse->base) {
475 pr_err("failed to map FUSE registers\n");
476 return -ENXIO;
477 }
478
479 fuse->soc->init(fuse);
480
481 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
482 tegra_revision_name[tegra_sku_info.revision],
483 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
484 tegra_sku_info.soc_process_id);
485 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
486 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
487
488 if (fuse->soc->lookups) {
489 size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
490
491 fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
492 if (!fuse->lookups)
493 return -ENOMEM;
494
495 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
496 }
497
498 return 0;
499 }
500 early_initcall(tegra_init_fuse);
501
502 #ifdef CONFIG_ARM64
tegra_init_soc(void)503 static int __init tegra_init_soc(void)
504 {
505 struct device_node *np;
506 struct device *soc;
507
508 /* make sure we're running on Tegra */
509 np = of_find_matching_node(NULL, tegra_fuse_match);
510 if (!np)
511 return 0;
512
513 of_node_put(np);
514
515 soc = tegra_soc_device_register();
516 if (IS_ERR(soc)) {
517 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
518 return PTR_ERR(soc);
519 }
520
521 return 0;
522 }
523 device_initcall(tegra_init_soc);
524 #endif
525