1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <linux/clk.h>
39 #include <linux/component.h>
40 #include <linux/i2c.h>
41 #include <linux/of_address.h>
42 #include <linux/of_gpio.h>
43 #include <linux/of_platform.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/rational.h>
46 #include <linux/reset.h>
47 #include <sound/dmaengine_pcm.h>
48 #include <sound/pcm_drm_eld.h>
49 #include <sound/pcm_params.h>
50 #include <sound/soc.h>
51 #include "media/cec.h"
52 #include "vc4_drv.h"
53 #include "vc4_hdmi.h"
54 #include "vc4_hdmi_regs.h"
55 #include "vc4_regs.h"
56
57 #define VC5_HDMI_HORZA_HFP_SHIFT 16
58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
59 #define VC5_HDMI_HORZA_VPOS BIT(15)
60 #define VC5_HDMI_HORZA_HPOS BIT(14)
61 #define VC5_HDMI_HORZA_HAP_SHIFT 0
62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
63
64 #define VC5_HDMI_HORZB_HBP_SHIFT 16
65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
66 #define VC5_HDMI_HORZB_HSP_SHIFT 0
67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
68
69 #define VC5_HDMI_VERTA_VSP_SHIFT 24
70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
71 #define VC5_HDMI_VERTA_VFP_SHIFT 16
72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
73 #define VC5_HDMI_VERTA_VAL_SHIFT 0
74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
75
76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
78
79 # define VC4_HD_M_SW_RST BIT(2)
80 # define VC4_HD_M_ENABLE BIT(0)
81
82 #define HSM_MIN_CLOCK_FREQ 120000000
83 #define CEC_CLOCK_FREQ 40000
84 #define VC4_HSM_MID_CLOCK 149985000
85
86 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
87
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)88 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
89 {
90 struct drm_info_node *node = (struct drm_info_node *)m->private;
91 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
92 struct drm_printer p = drm_seq_file_printer(m);
93
94 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
95 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
96
97 return 0;
98 }
99
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)100 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
101 {
102 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
103 udelay(1);
104 HDMI_WRITE(HDMI_M_CTL, 0);
105
106 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
107
108 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
109 VC4_HDMI_SW_RESET_HDMI |
110 VC4_HDMI_SW_RESET_FORMAT_DETECT);
111
112 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
113 }
114
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)115 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
116 {
117 reset_control_reset(vc4_hdmi->reset);
118
119 HDMI_WRITE(HDMI_DVP_CTL, 0);
120
121 HDMI_WRITE(HDMI_CLOCK_STOP,
122 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
123 }
124
125 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)126 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
127 {
128 u16 clk_cnt;
129 u32 value;
130
131 value = HDMI_READ(HDMI_CEC_CNTRL_1);
132 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
133
134 /*
135 * Set the clock divider: the hsm_clock rate and this divider
136 * setting will give a 40 kHz CEC clock.
137 */
138 clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
139 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
140 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
141 }
142 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)143 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
144 #endif
145
146 static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector * connector,bool force)147 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
148 {
149 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
150 bool connected = false;
151
152 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
153
154 if (vc4_hdmi->hpd_gpio) {
155 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
156 vc4_hdmi->hpd_active_low)
157 connected = true;
158 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
159 connected = true;
160 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
161 connected = true;
162 }
163
164 if (connected) {
165 if (connector->status != connector_status_connected) {
166 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
167
168 if (edid) {
169 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
170 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
171 kfree(edid);
172 }
173 }
174
175 pm_runtime_put(&vc4_hdmi->pdev->dev);
176 return connector_status_connected;
177 }
178
179 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
180 pm_runtime_put(&vc4_hdmi->pdev->dev);
181 return connector_status_disconnected;
182 }
183
vc4_hdmi_connector_destroy(struct drm_connector * connector)184 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
185 {
186 drm_connector_unregister(connector);
187 drm_connector_cleanup(connector);
188 }
189
vc4_hdmi_connector_get_modes(struct drm_connector * connector)190 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
191 {
192 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
193 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
194 int ret = 0;
195 struct edid *edid;
196
197 edid = drm_get_edid(connector, vc4_hdmi->ddc);
198 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
199 if (!edid)
200 return -ENODEV;
201
202 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
203
204 drm_connector_update_edid_property(connector, edid);
205 ret = drm_add_edid_modes(connector, edid);
206 kfree(edid);
207
208 return ret;
209 }
210
vc4_hdmi_connector_reset(struct drm_connector * connector)211 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
212 {
213 drm_atomic_helper_connector_reset(connector);
214
215 if (connector->state)
216 drm_atomic_helper_connector_tv_reset(connector);
217 }
218
219 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
220 .detect = vc4_hdmi_connector_detect,
221 .fill_modes = drm_helper_probe_single_connector_modes,
222 .destroy = vc4_hdmi_connector_destroy,
223 .reset = vc4_hdmi_connector_reset,
224 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
225 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
226 };
227
228 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
229 .get_modes = vc4_hdmi_connector_get_modes,
230 };
231
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)232 static int vc4_hdmi_connector_init(struct drm_device *dev,
233 struct vc4_hdmi *vc4_hdmi)
234 {
235 struct drm_connector *connector = &vc4_hdmi->connector;
236 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
237 int ret;
238
239 drm_connector_init_with_ddc(dev, connector,
240 &vc4_hdmi_connector_funcs,
241 DRM_MODE_CONNECTOR_HDMIA,
242 vc4_hdmi->ddc);
243 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
244
245 /* Create and attach TV margin props to this connector. */
246 ret = drm_mode_create_tv_margin_properties(dev);
247 if (ret)
248 return ret;
249
250 drm_connector_attach_tv_margin_properties(connector);
251
252 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
253 DRM_CONNECTOR_POLL_DISCONNECT);
254
255 connector->interlace_allowed = 1;
256 connector->doublescan_allowed = 0;
257
258 drm_connector_attach_encoder(connector, encoder);
259
260 return 0;
261 }
262
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type)263 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
264 enum hdmi_infoframe_type type)
265 {
266 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
267 u32 packet_id = type - 0x80;
268
269 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
270 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
271
272 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
273 BIT(packet_id)), 100);
274 }
275
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)276 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
277 union hdmi_infoframe *frame)
278 {
279 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
280 u32 packet_id = frame->any.type - 0x80;
281 const struct vc4_hdmi_register *ram_packet_start =
282 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
283 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
284 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
285 ram_packet_start->reg);
286 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
287 ssize_t len, i;
288 int ret;
289
290 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
291 VC4_HDMI_RAM_PACKET_ENABLE),
292 "Packet RAM has to be on to store the packet.");
293
294 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
295 if (len < 0)
296 return;
297
298 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
299 if (ret) {
300 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
301 return;
302 }
303
304 for (i = 0; i < len; i += 7) {
305 writel(buffer[i + 0] << 0 |
306 buffer[i + 1] << 8 |
307 buffer[i + 2] << 16,
308 base + packet_reg);
309 packet_reg += 4;
310
311 writel(buffer[i + 3] << 0 |
312 buffer[i + 4] << 8 |
313 buffer[i + 5] << 16 |
314 buffer[i + 6] << 24,
315 base + packet_reg);
316 packet_reg += 4;
317 }
318
319 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
320 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
321 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
322 BIT(packet_id)), 100);
323 if (ret)
324 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
325 }
326
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)327 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
328 {
329 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
330 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
331 struct drm_connector *connector = &vc4_hdmi->connector;
332 struct drm_connector_state *cstate = connector->state;
333 struct drm_crtc *crtc = encoder->crtc;
334 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
335 union hdmi_infoframe frame;
336 int ret;
337
338 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
339 connector, mode);
340 if (ret < 0) {
341 DRM_ERROR("couldn't fill AVI infoframe\n");
342 return;
343 }
344
345 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
346 connector, mode,
347 vc4_encoder->limited_rgb_range ?
348 HDMI_QUANTIZATION_RANGE_LIMITED :
349 HDMI_QUANTIZATION_RANGE_FULL);
350
351 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
352
353 vc4_hdmi_write_infoframe(encoder, &frame);
354 }
355
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)356 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
357 {
358 union hdmi_infoframe frame;
359 int ret;
360
361 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
362 if (ret < 0) {
363 DRM_ERROR("couldn't fill SPD infoframe\n");
364 return;
365 }
366
367 frame.spd.sdi = HDMI_SPD_SDI_PC;
368
369 vc4_hdmi_write_infoframe(encoder, &frame);
370 }
371
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)372 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
373 {
374 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
375 union hdmi_infoframe frame;
376 int ret;
377
378 ret = hdmi_audio_infoframe_init(&frame.audio);
379
380 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
381 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
382 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
383 frame.audio.channels = vc4_hdmi->audio.channels;
384
385 vc4_hdmi_write_infoframe(encoder, &frame);
386 }
387
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)388 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
389 {
390 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
391
392 vc4_hdmi_set_avi_infoframe(encoder);
393 vc4_hdmi_set_spd_infoframe(encoder);
394 /*
395 * If audio was streaming, then we need to reenabled the audio
396 * infoframe here during encoder_enable.
397 */
398 if (vc4_hdmi->audio.streaming)
399 vc4_hdmi_set_audio_infoframe(encoder);
400 }
401
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder)402 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
403 {
404 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
405
406 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
407
408 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
409 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
410
411 HDMI_WRITE(HDMI_VID_CTL,
412 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
413 }
414
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder)415 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
416 {
417 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
418 int ret;
419
420 if (vc4_hdmi->variant->phy_disable)
421 vc4_hdmi->variant->phy_disable(vc4_hdmi);
422
423 HDMI_WRITE(HDMI_VID_CTL,
424 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
425
426 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
427 clk_disable_unprepare(vc4_hdmi->pixel_clock);
428
429 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
430 if (ret < 0)
431 DRM_ERROR("Failed to release power domain: %d\n", ret);
432 }
433
vc4_hdmi_encoder_disable(struct drm_encoder * encoder)434 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
435 {
436 }
437
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)438 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
439 {
440 u32 csc_ctl;
441
442 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
443 VC4_HD_CSC_CTL_ORDER);
444
445 if (enable) {
446 /* CEA VICs other than #1 requre limited range RGB
447 * output unless overridden by an AVI infoframe.
448 * Apply a colorspace conversion to squash 0-255 down
449 * to 16-235. The matrix here is:
450 *
451 * [ 0 0 0.8594 16]
452 * [ 0 0.8594 0 16]
453 * [ 0.8594 0 0 16]
454 * [ 0 0 0 1]
455 */
456 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
457 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
458 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
459 VC4_HD_CSC_CTL_MODE);
460
461 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
462 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
463 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
464 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
465 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
466 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
467 }
468
469 /* The RGB order applies even when CSC is disabled. */
470 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
471 }
472
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)473 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
474 {
475 u32 csc_ctl;
476
477 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
478
479 if (enable) {
480 /* CEA VICs other than #1 requre limited range RGB
481 * output unless overridden by an AVI infoframe.
482 * Apply a colorspace conversion to squash 0-255 down
483 * to 16-235. The matrix here is:
484 *
485 * [ 0.8594 0 0 16]
486 * [ 0 0.8594 0 16]
487 * [ 0 0 0.8594 16]
488 * [ 0 0 0 1]
489 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
490 */
491 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
492 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
493 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
494 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
495 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
496 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
497 } else {
498 /* Still use the matrix for full range, but make it unity.
499 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
500 */
501 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
502 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
503 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
504 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
505 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
506 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
507 }
508
509 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
510 }
511
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)512 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
513 struct drm_display_mode *mode)
514 {
515 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
516 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
517 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
518 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
519 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
520 VC4_HDMI_VERTA_VSP) |
521 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
522 VC4_HDMI_VERTA_VFP) |
523 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
524 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
525 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
526 interlaced,
527 VC4_HDMI_VERTB_VBP));
528 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
529 VC4_SET_FIELD(mode->crtc_vtotal -
530 mode->crtc_vsync_end,
531 VC4_HDMI_VERTB_VBP));
532
533 HDMI_WRITE(HDMI_HORZA,
534 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
535 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
536 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
537 VC4_HDMI_HORZA_HAP));
538
539 HDMI_WRITE(HDMI_HORZB,
540 VC4_SET_FIELD((mode->htotal -
541 mode->hsync_end) * pixel_rep,
542 VC4_HDMI_HORZB_HBP) |
543 VC4_SET_FIELD((mode->hsync_end -
544 mode->hsync_start) * pixel_rep,
545 VC4_HDMI_HORZB_HSP) |
546 VC4_SET_FIELD((mode->hsync_start -
547 mode->hdisplay) * pixel_rep,
548 VC4_HDMI_HORZB_HFP));
549
550 HDMI_WRITE(HDMI_VERTA0, verta);
551 HDMI_WRITE(HDMI_VERTA1, verta);
552
553 HDMI_WRITE(HDMI_VERTB0, vertb_even);
554 HDMI_WRITE(HDMI_VERTB1, vertb);
555 }
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)556 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
557 struct drm_display_mode *mode)
558 {
559 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
560 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
561 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
562 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
563 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
564 VC5_HDMI_VERTA_VSP) |
565 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
566 VC5_HDMI_VERTA_VFP) |
567 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
568 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
569 VC5_HDMI_VERTB_VSPO) |
570 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
571 VC4_HDMI_VERTB_VBP));
572 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
573 VC4_SET_FIELD(mode->crtc_vtotal -
574 mode->crtc_vsync_end - interlaced,
575 VC4_HDMI_VERTB_VBP));
576
577 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
578 HDMI_WRITE(HDMI_HORZA,
579 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
580 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
581 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
582 VC5_HDMI_HORZA_HAP) |
583 VC4_SET_FIELD((mode->hsync_start -
584 mode->hdisplay) * pixel_rep,
585 VC5_HDMI_HORZA_HFP));
586
587 HDMI_WRITE(HDMI_HORZB,
588 VC4_SET_FIELD((mode->htotal -
589 mode->hsync_end) * pixel_rep,
590 VC5_HDMI_HORZB_HBP) |
591 VC4_SET_FIELD((mode->hsync_end -
592 mode->hsync_start) * pixel_rep,
593 VC5_HDMI_HORZB_HSP));
594
595 HDMI_WRITE(HDMI_VERTA0, verta);
596 HDMI_WRITE(HDMI_VERTA1, verta);
597
598 HDMI_WRITE(HDMI_VERTB0, vertb_even);
599 HDMI_WRITE(HDMI_VERTB1, vertb);
600
601 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
602 }
603
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)604 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
605 {
606 u32 drift;
607 int ret;
608
609 drift = HDMI_READ(HDMI_FIFO_CTL);
610 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
611
612 HDMI_WRITE(HDMI_FIFO_CTL,
613 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
614 HDMI_WRITE(HDMI_FIFO_CTL,
615 drift | VC4_HDMI_FIFO_CTL_RECENTER);
616 usleep_range(1000, 1100);
617 HDMI_WRITE(HDMI_FIFO_CTL,
618 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
619 HDMI_WRITE(HDMI_FIFO_CTL,
620 drift | VC4_HDMI_FIFO_CTL_RECENTER);
621
622 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
623 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
624 WARN_ONCE(ret, "Timeout waiting for "
625 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
626 }
627
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder)628 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
629 {
630 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
631 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
632 unsigned long pixel_rate, hsm_rate;
633 int ret;
634
635 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
636 if (ret < 0) {
637 DRM_ERROR("Failed to retain power domain: %d\n", ret);
638 return;
639 }
640
641 pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
642 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
643 if (ret) {
644 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
645 return;
646 }
647
648 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
649 if (ret) {
650 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
651 return;
652 }
653
654 /*
655 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
656 * be faster than pixel clock, infinitesimally faster, tested in
657 * simulation. Otherwise, exact value is unimportant for HDMI
658 * operation." This conflicts with bcm2835's vc4 documentation, which
659 * states HSM's clock has to be at least 108% of the pixel clock.
660 *
661 * Real life tests reveal that vc4's firmware statement holds up, and
662 * users are able to use pixel clocks closer to HSM's, namely for
663 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
664 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
665 * 162MHz.
666 *
667 * Additionally, the AXI clock needs to be at least 25% of
668 * pixel clock, but HSM ends up being the limiting factor.
669 */
670 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
671 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
672 if (ret) {
673 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
674 return;
675 }
676
677 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
678
679 /*
680 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
681 * at 300MHz.
682 */
683 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
684 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
685 if (ret) {
686 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
687 clk_disable_unprepare(vc4_hdmi->pixel_clock);
688 return;
689 }
690
691 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
692 if (ret) {
693 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
694 clk_disable_unprepare(vc4_hdmi->pixel_clock);
695 return;
696 }
697
698 if (vc4_hdmi->variant->phy_init)
699 vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
700
701 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
702 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
703 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
704 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
705
706 if (vc4_hdmi->variant->set_timings)
707 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
708 }
709
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder)710 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
711 {
712 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
713 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
714 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
715
716 if (vc4_encoder->hdmi_monitor &&
717 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
718 if (vc4_hdmi->variant->csc_setup)
719 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
720
721 vc4_encoder->limited_rgb_range = true;
722 } else {
723 if (vc4_hdmi->variant->csc_setup)
724 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
725
726 vc4_encoder->limited_rgb_range = false;
727 }
728
729 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
730 }
731
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder)732 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
733 {
734 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
735 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
736 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
737 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
738 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
739 int ret;
740
741 HDMI_WRITE(HDMI_VID_CTL,
742 VC4_HD_VID_CTL_ENABLE |
743 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
744 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
745 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
746 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
747
748 HDMI_WRITE(HDMI_VID_CTL,
749 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
750
751 if (vc4_encoder->hdmi_monitor) {
752 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
753 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
754 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
755
756 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
757 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
758 WARN_ONCE(ret, "Timeout waiting for "
759 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
760 } else {
761 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
762 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
763 ~(VC4_HDMI_RAM_PACKET_ENABLE));
764 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
765 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
766 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
767
768 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
769 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
770 WARN_ONCE(ret, "Timeout waiting for "
771 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
772 }
773
774 if (vc4_encoder->hdmi_monitor) {
775 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
776 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
777 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
778 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
779 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
780
781 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
782 VC4_HDMI_RAM_PACKET_ENABLE);
783
784 vc4_hdmi_set_infoframes(encoder);
785 }
786
787 vc4_hdmi_recenter_fifo(vc4_hdmi);
788 }
789
vc4_hdmi_encoder_enable(struct drm_encoder * encoder)790 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
791 {
792 }
793
794 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
795 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
796
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)797 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
798 struct drm_crtc_state *crtc_state,
799 struct drm_connector_state *conn_state)
800 {
801 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
802 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
803 unsigned long long pixel_rate = mode->clock * 1000;
804 unsigned long long tmds_rate;
805
806 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
807 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
808 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
809 (mode->hsync_end % 2) || (mode->htotal % 2)))
810 return -EINVAL;
811
812 /*
813 * The 1440p@60 pixel rate is in the same range than the first
814 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
815 * bandwidth). Slightly lower the frequency to bring it out of
816 * the WiFi range.
817 */
818 tmds_rate = pixel_rate * 10;
819 if (vc4_hdmi->disable_wifi_frequencies &&
820 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
821 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
822 mode->clock = 238560;
823 pixel_rate = mode->clock * 1000;
824 }
825
826 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
827 pixel_rate = pixel_rate * 2;
828
829 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
830 return -EINVAL;
831
832 return 0;
833 }
834
835 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)836 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
837 const struct drm_display_mode *mode)
838 {
839 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
840
841 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
842 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
843 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
844 (mode->hsync_end % 2) || (mode->htotal % 2)))
845 return MODE_H_ILLEGAL;
846
847 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
848 return MODE_CLOCK_HIGH;
849
850 return MODE_OK;
851 }
852
853 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
854 .atomic_check = vc4_hdmi_encoder_atomic_check,
855 .mode_valid = vc4_hdmi_encoder_mode_valid,
856 .disable = vc4_hdmi_encoder_disable,
857 .enable = vc4_hdmi_encoder_enable,
858 };
859
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)860 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
861 {
862 int i;
863 u32 channel_map = 0;
864
865 for (i = 0; i < 8; i++) {
866 if (channel_mask & BIT(i))
867 channel_map |= i << (3 * i);
868 }
869 return channel_map;
870 }
871
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)872 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
873 {
874 int i;
875 u32 channel_map = 0;
876
877 for (i = 0; i < 8; i++) {
878 if (channel_mask & BIT(i))
879 channel_map |= i << (4 * i);
880 }
881 return channel_map;
882 }
883
884 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi)885 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
886 {
887 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
888 unsigned long n, m;
889
890 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
891 VC4_HD_MAI_SMP_N_MASK >>
892 VC4_HD_MAI_SMP_N_SHIFT,
893 (VC4_HD_MAI_SMP_M_MASK >>
894 VC4_HD_MAI_SMP_M_SHIFT) + 1,
895 &n, &m);
896
897 HDMI_WRITE(HDMI_MAI_SMP,
898 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
899 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
900 }
901
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi)902 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
903 {
904 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
905 struct drm_crtc *crtc = encoder->crtc;
906 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
907 u32 samplerate = vc4_hdmi->audio.samplerate;
908 u32 n, cts;
909 u64 tmp;
910
911 n = 128 * samplerate / 1000;
912 tmp = (u64)(mode->clock * 1000) * n;
913 do_div(tmp, 128 * samplerate);
914 cts = tmp;
915
916 HDMI_WRITE(HDMI_CRP_CFG,
917 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
918 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
919
920 /*
921 * We could get slightly more accurate clocks in some cases by
922 * providing a CTS_1 value. The two CTS values are alternated
923 * between based on the period fields
924 */
925 HDMI_WRITE(HDMI_CTS_0, cts);
926 HDMI_WRITE(HDMI_CTS_1, cts);
927 }
928
dai_to_hdmi(struct snd_soc_dai * dai)929 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
930 {
931 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
932
933 return snd_soc_card_get_drvdata(card);
934 }
935
vc4_hdmi_audio_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)936 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
937 struct snd_soc_dai *dai)
938 {
939 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
940 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
941 struct drm_connector *connector = &vc4_hdmi->connector;
942 int ret;
943
944 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
945 return -EINVAL;
946
947 vc4_hdmi->audio.substream = substream;
948
949 /*
950 * If the HDMI encoder hasn't probed, or the encoder is
951 * currently in DVI mode, treat the codec dai as missing.
952 */
953 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
954 VC4_HDMI_RAM_PACKET_ENABLE))
955 return -ENODEV;
956
957 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
958 if (ret)
959 return ret;
960
961 return 0;
962 }
963
vc4_hdmi_audio_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)964 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
965 {
966 return 0;
967 }
968
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)969 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
970 {
971 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
972 struct device *dev = &vc4_hdmi->pdev->dev;
973 int ret;
974
975 vc4_hdmi->audio.streaming = false;
976 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
977 if (ret)
978 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
979
980 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
981 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
982 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
983 }
984
vc4_hdmi_audio_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)985 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
986 struct snd_soc_dai *dai)
987 {
988 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
989
990 if (substream != vc4_hdmi->audio.substream)
991 return;
992
993 vc4_hdmi_audio_reset(vc4_hdmi);
994
995 vc4_hdmi->audio.substream = NULL;
996 }
997
998 /* HDMI audio codec callbacks */
vc4_hdmi_audio_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)999 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1000 struct snd_pcm_hw_params *params,
1001 struct snd_soc_dai *dai)
1002 {
1003 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1004 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1005 struct device *dev = &vc4_hdmi->pdev->dev;
1006 u32 audio_packet_config, channel_mask;
1007 u32 channel_map;
1008
1009 if (substream != vc4_hdmi->audio.substream)
1010 return -EINVAL;
1011
1012 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1013 params_rate(params), params_width(params),
1014 params_channels(params));
1015
1016 vc4_hdmi->audio.channels = params_channels(params);
1017 vc4_hdmi->audio.samplerate = params_rate(params);
1018
1019 HDMI_WRITE(HDMI_MAI_CTL,
1020 VC4_HD_MAI_CTL_RESET |
1021 VC4_HD_MAI_CTL_FLUSH |
1022 VC4_HD_MAI_CTL_DLATE |
1023 VC4_HD_MAI_CTL_ERRORE |
1024 VC4_HD_MAI_CTL_ERRORF);
1025
1026 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1027
1028 /* The B frame identifier should match the value used by alsa-lib (8) */
1029 audio_packet_config =
1030 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1031 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1032 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1033
1034 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1035 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1036 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1037
1038 /* Set the MAI threshold */
1039 HDMI_WRITE(HDMI_MAI_THR,
1040 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1041 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1042 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1043 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1044
1045 HDMI_WRITE(HDMI_MAI_CONFIG,
1046 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1047 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1048
1049 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1050 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1051 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1052 vc4_hdmi_set_n_cts(vc4_hdmi);
1053
1054 vc4_hdmi_set_audio_infoframe(encoder);
1055
1056 return 0;
1057 }
1058
vc4_hdmi_audio_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1059 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1060 struct snd_soc_dai *dai)
1061 {
1062 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1063
1064 switch (cmd) {
1065 case SNDRV_PCM_TRIGGER_START:
1066 vc4_hdmi->audio.streaming = true;
1067
1068 if (vc4_hdmi->variant->phy_rng_enable)
1069 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1070
1071 HDMI_WRITE(HDMI_MAI_CTL,
1072 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1073 VC4_HD_MAI_CTL_CHNUM) |
1074 VC4_HD_MAI_CTL_WHOLSMP |
1075 VC4_HD_MAI_CTL_CHALIGN |
1076 VC4_HD_MAI_CTL_ENABLE);
1077 break;
1078 case SNDRV_PCM_TRIGGER_STOP:
1079 HDMI_WRITE(HDMI_MAI_CTL,
1080 VC4_HD_MAI_CTL_DLATE |
1081 VC4_HD_MAI_CTL_ERRORE |
1082 VC4_HD_MAI_CTL_ERRORF);
1083
1084 if (vc4_hdmi->variant->phy_rng_disable)
1085 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1086
1087 vc4_hdmi->audio.streaming = false;
1088
1089 break;
1090 default:
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096
1097 static inline struct vc4_hdmi *
snd_component_to_hdmi(struct snd_soc_component * component)1098 snd_component_to_hdmi(struct snd_soc_component *component)
1099 {
1100 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1101
1102 return snd_soc_card_get_drvdata(card);
1103 }
1104
vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1105 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1106 struct snd_ctl_elem_info *uinfo)
1107 {
1108 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1109 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1110 struct drm_connector *connector = &vc4_hdmi->connector;
1111
1112 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1113 uinfo->count = sizeof(connector->eld);
1114
1115 return 0;
1116 }
1117
vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1118 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1119 struct snd_ctl_elem_value *ucontrol)
1120 {
1121 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1122 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1123 struct drm_connector *connector = &vc4_hdmi->connector;
1124
1125 memcpy(ucontrol->value.bytes.data, connector->eld,
1126 sizeof(connector->eld));
1127
1128 return 0;
1129 }
1130
1131 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1132 {
1133 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1134 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1135 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1136 .name = "ELD",
1137 .info = vc4_hdmi_audio_eld_ctl_info,
1138 .get = vc4_hdmi_audio_eld_ctl_get,
1139 },
1140 };
1141
1142 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1143 SND_SOC_DAPM_OUTPUT("TX"),
1144 };
1145
1146 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1147 { "TX", NULL, "Playback" },
1148 };
1149
1150 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1151 .name = "vc4-hdmi-codec-dai-component",
1152 .controls = vc4_hdmi_audio_controls,
1153 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1154 .dapm_widgets = vc4_hdmi_audio_widgets,
1155 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1156 .dapm_routes = vc4_hdmi_audio_routes,
1157 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1158 .idle_bias_on = 1,
1159 .use_pmdown_time = 1,
1160 .endianness = 1,
1161 .non_legacy_dai_naming = 1,
1162 };
1163
1164 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1165 .startup = vc4_hdmi_audio_startup,
1166 .shutdown = vc4_hdmi_audio_shutdown,
1167 .hw_params = vc4_hdmi_audio_hw_params,
1168 .set_fmt = vc4_hdmi_audio_set_fmt,
1169 .trigger = vc4_hdmi_audio_trigger,
1170 };
1171
1172 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1173 .name = "vc4-hdmi-hifi",
1174 .playback = {
1175 .stream_name = "Playback",
1176 .channels_min = 2,
1177 .channels_max = 8,
1178 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1179 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1180 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1181 SNDRV_PCM_RATE_192000,
1182 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1183 },
1184 };
1185
1186 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1187 .name = "vc4-hdmi-cpu-dai-component",
1188 };
1189
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)1190 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1191 {
1192 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1193
1194 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1195
1196 return 0;
1197 }
1198
1199 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1200 .name = "vc4-hdmi-cpu-dai",
1201 .probe = vc4_hdmi_audio_cpu_dai_probe,
1202 .playback = {
1203 .stream_name = "Playback",
1204 .channels_min = 1,
1205 .channels_max = 8,
1206 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1207 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1208 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1209 SNDRV_PCM_RATE_192000,
1210 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1211 },
1212 .ops = &vc4_hdmi_audio_dai_ops,
1213 };
1214
1215 static const struct snd_dmaengine_pcm_config pcm_conf = {
1216 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1217 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1218 };
1219
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)1220 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1221 {
1222 const struct vc4_hdmi_register *mai_data =
1223 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1224 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1225 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1226 struct device *dev = &vc4_hdmi->pdev->dev;
1227 const __be32 *addr;
1228 int index, len;
1229 int ret;
1230
1231 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
1232 dev_warn(dev,
1233 "'dmas' DT property is missing or empty, no HDMI audio\n");
1234 return 0;
1235 }
1236
1237 if (mai_data->reg != VC4_HD) {
1238 WARN_ONCE(true, "MAI isn't in the HD block\n");
1239 return -EINVAL;
1240 }
1241
1242 /*
1243 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1244 * the bus address specified in the DT, because the physical address
1245 * (the one returned by platform_get_resource()) is not appropriate
1246 * for DMA transfers.
1247 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1248 */
1249 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1250 /* Before BCM2711, we don't have a named register range */
1251 if (index < 0)
1252 index = 1;
1253
1254 addr = of_get_address(dev->of_node, index, NULL, NULL);
1255
1256 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1257 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1258 vc4_hdmi->audio.dma_data.maxburst = 2;
1259
1260 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1261 if (ret) {
1262 dev_err(dev, "Could not register PCM component: %d\n", ret);
1263 return ret;
1264 }
1265
1266 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1267 &vc4_hdmi_audio_cpu_dai_drv, 1);
1268 if (ret) {
1269 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1270 return ret;
1271 }
1272
1273 /* register component and codec dai */
1274 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1275 &vc4_hdmi_audio_codec_dai_drv, 1);
1276 if (ret) {
1277 dev_err(dev, "Could not register component: %d\n", ret);
1278 return ret;
1279 }
1280
1281 dai_link->cpus = &vc4_hdmi->audio.cpu;
1282 dai_link->codecs = &vc4_hdmi->audio.codec;
1283 dai_link->platforms = &vc4_hdmi->audio.platform;
1284
1285 dai_link->num_cpus = 1;
1286 dai_link->num_codecs = 1;
1287 dai_link->num_platforms = 1;
1288
1289 dai_link->name = "MAI";
1290 dai_link->stream_name = "MAI PCM";
1291 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1292 dai_link->cpus->dai_name = dev_name(dev);
1293 dai_link->codecs->name = dev_name(dev);
1294 dai_link->platforms->name = dev_name(dev);
1295
1296 card->dai_link = dai_link;
1297 card->num_links = 1;
1298 card->name = vc4_hdmi->variant->card_name;
1299 card->driver_name = "vc4-hdmi";
1300 card->dev = dev;
1301 card->owner = THIS_MODULE;
1302
1303 /*
1304 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1305 * stores a pointer to the snd card object in dev->driver_data. This
1306 * means we cannot use it for something else. The hdmi back-pointer is
1307 * now stored in card->drvdata and should be retrieved with
1308 * snd_soc_card_get_drvdata() if needed.
1309 */
1310 snd_soc_card_set_drvdata(card, vc4_hdmi);
1311 ret = devm_snd_soc_register_card(dev, card);
1312 if (ret)
1313 dev_err(dev, "Could not register sound card: %d\n", ret);
1314
1315 return ret;
1316
1317 }
1318
1319 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_thread(int irq,void * priv)1320 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1321 {
1322 struct vc4_hdmi *vc4_hdmi = priv;
1323
1324 if (vc4_hdmi->cec_irq_was_rx) {
1325 if (vc4_hdmi->cec_rx_msg.len)
1326 cec_received_msg(vc4_hdmi->cec_adap,
1327 &vc4_hdmi->cec_rx_msg);
1328 } else if (vc4_hdmi->cec_tx_ok) {
1329 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1330 0, 0, 0, 0);
1331 } else {
1332 /*
1333 * This CEC implementation makes 1 retry, so if we
1334 * get a NACK, then that means it made 2 attempts.
1335 */
1336 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1337 0, 2, 0, 0);
1338 }
1339 return IRQ_HANDLED;
1340 }
1341
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)1342 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1343 {
1344 struct drm_device *dev = vc4_hdmi->connector.dev;
1345 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1346 unsigned int i;
1347
1348 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1349 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1350
1351 if (msg->len > 16) {
1352 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1353 return;
1354 }
1355
1356 for (i = 0; i < msg->len; i += 4) {
1357 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1358
1359 msg->msg[i] = val & 0xff;
1360 msg->msg[i + 1] = (val >> 8) & 0xff;
1361 msg->msg[i + 2] = (val >> 16) & 0xff;
1362 msg->msg[i + 3] = (val >> 24) & 0xff;
1363 }
1364 }
1365
vc4_cec_irq_handler(int irq,void * priv)1366 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1367 {
1368 struct vc4_hdmi *vc4_hdmi = priv;
1369 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1370 u32 cntrl1, cntrl5;
1371
1372 if (!(stat & VC4_HDMI_CPU_CEC))
1373 return IRQ_NONE;
1374 vc4_hdmi->cec_rx_msg.len = 0;
1375 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1376 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1377 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1378 if (vc4_hdmi->cec_irq_was_rx) {
1379 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1380 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1381 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1382 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1383 } else {
1384 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1385 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1386 }
1387 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1388 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1389
1390 return IRQ_WAKE_THREAD;
1391 }
1392
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)1393 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1394 {
1395 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1396 /* clock period in microseconds */
1397 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1398 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1399
1400 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1401 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1402 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1403 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1404 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1405
1406 if (enable) {
1407 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1408 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1409 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1410 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1411 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1412 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1413 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1414 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1415 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1416 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1417 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1418 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1419 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1420 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1421 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1422 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1423 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1424 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1425 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1426
1427 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1428 } else {
1429 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1430 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1431 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1432 }
1433 return 0;
1434 }
1435
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1436 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1437 {
1438 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1439
1440 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1441 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1442 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1443 return 0;
1444 }
1445
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1446 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1447 u32 signal_free_time, struct cec_msg *msg)
1448 {
1449 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1450 struct drm_device *dev = vc4_hdmi->connector.dev;
1451 u32 val;
1452 unsigned int i;
1453
1454 if (msg->len > 16) {
1455 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1456 return -ENOMEM;
1457 }
1458
1459 for (i = 0; i < msg->len; i += 4)
1460 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1461 (msg->msg[i]) |
1462 (msg->msg[i + 1] << 8) |
1463 (msg->msg[i + 2] << 16) |
1464 (msg->msg[i + 3] << 24));
1465
1466 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1467 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1468 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1469 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1470 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1471 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1472
1473 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1474 return 0;
1475 }
1476
1477 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1478 .adap_enable = vc4_hdmi_cec_adap_enable,
1479 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1480 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1481 };
1482
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1483 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1484 {
1485 struct cec_connector_info conn_info;
1486 struct platform_device *pdev = vc4_hdmi->pdev;
1487 u32 value;
1488 int ret;
1489
1490 if (!vc4_hdmi->variant->cec_available)
1491 return 0;
1492
1493 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1494 vc4_hdmi, "vc4",
1495 CEC_CAP_DEFAULTS |
1496 CEC_CAP_CONNECTOR_INFO, 1);
1497 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1498 if (ret < 0)
1499 return ret;
1500
1501 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1502 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1503
1504 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1505
1506 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1507 /* Set the logical address to Unregistered */
1508 value |= VC4_HDMI_CEC_ADDR_MASK;
1509 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1510
1511 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1512
1513 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1514 vc4_cec_irq_handler,
1515 vc4_cec_irq_handler_thread, 0,
1516 "vc4 hdmi cec", vc4_hdmi);
1517 if (ret)
1518 goto err_delete_cec_adap;
1519
1520 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1521 if (ret < 0)
1522 goto err_delete_cec_adap;
1523
1524 return 0;
1525
1526 err_delete_cec_adap:
1527 cec_delete_adapter(vc4_hdmi->cec_adap);
1528
1529 return ret;
1530 }
1531
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1532 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1533 {
1534 cec_unregister_adapter(vc4_hdmi->cec_adap);
1535 }
1536 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1537 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1538 {
1539 return 0;
1540 }
1541
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1542 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1543
1544 #endif
1545
vc4_hdmi_build_regset(struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)1546 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1547 struct debugfs_regset32 *regset,
1548 enum vc4_hdmi_regs reg)
1549 {
1550 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1551 struct debugfs_reg32 *regs, *new_regs;
1552 unsigned int count = 0;
1553 unsigned int i;
1554
1555 regs = kcalloc(variant->num_registers, sizeof(*regs),
1556 GFP_KERNEL);
1557 if (!regs)
1558 return -ENOMEM;
1559
1560 for (i = 0; i < variant->num_registers; i++) {
1561 const struct vc4_hdmi_register *field = &variant->registers[i];
1562
1563 if (field->reg != reg)
1564 continue;
1565
1566 regs[count].name = field->name;
1567 regs[count].offset = field->offset;
1568 count++;
1569 }
1570
1571 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1572 if (!new_regs)
1573 return -ENOMEM;
1574
1575 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1576 regset->regs = new_regs;
1577 regset->nregs = count;
1578
1579 return 0;
1580 }
1581
vc4_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1582 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1583 {
1584 struct platform_device *pdev = vc4_hdmi->pdev;
1585 struct device *dev = &pdev->dev;
1586 int ret;
1587
1588 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1589 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1590 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1591
1592 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1593 if (IS_ERR(vc4_hdmi->hd_regs))
1594 return PTR_ERR(vc4_hdmi->hd_regs);
1595
1596 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1597 if (ret)
1598 return ret;
1599
1600 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1601 if (ret)
1602 return ret;
1603
1604 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1605 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1606 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1607 if (ret != -EPROBE_DEFER)
1608 DRM_ERROR("Failed to get pixel clock\n");
1609 return ret;
1610 }
1611
1612 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1613 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1614 DRM_ERROR("Failed to get HDMI state machine clock\n");
1615 return PTR_ERR(vc4_hdmi->hsm_clock);
1616 }
1617 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1618
1619 return 0;
1620 }
1621
vc5_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1622 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1623 {
1624 struct platform_device *pdev = vc4_hdmi->pdev;
1625 struct device *dev = &pdev->dev;
1626 struct resource *res;
1627
1628 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1629 if (!res)
1630 return -ENODEV;
1631
1632 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1633 resource_size(res));
1634 if (!vc4_hdmi->hdmicore_regs)
1635 return -ENOMEM;
1636
1637 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1638 if (!res)
1639 return -ENODEV;
1640
1641 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1642 if (!vc4_hdmi->hd_regs)
1643 return -ENOMEM;
1644
1645 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1646 if (!res)
1647 return -ENODEV;
1648
1649 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1650 if (!vc4_hdmi->cec_regs)
1651 return -ENOMEM;
1652
1653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1654 if (!res)
1655 return -ENODEV;
1656
1657 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1658 if (!vc4_hdmi->csc_regs)
1659 return -ENOMEM;
1660
1661 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1662 if (!res)
1663 return -ENODEV;
1664
1665 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1666 if (!vc4_hdmi->dvp_regs)
1667 return -ENOMEM;
1668
1669 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1670 if (!res)
1671 return -ENODEV;
1672
1673 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1674 if (!vc4_hdmi->phy_regs)
1675 return -ENOMEM;
1676
1677 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1678 if (!res)
1679 return -ENODEV;
1680
1681 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1682 if (!vc4_hdmi->ram_regs)
1683 return -ENOMEM;
1684
1685 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1686 if (!res)
1687 return -ENODEV;
1688
1689 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1690 if (!vc4_hdmi->rm_regs)
1691 return -ENOMEM;
1692
1693 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1694 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1695 DRM_ERROR("Failed to get HDMI state machine clock\n");
1696 return PTR_ERR(vc4_hdmi->hsm_clock);
1697 }
1698
1699 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1700 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1701 DRM_ERROR("Failed to get pixel bvb clock\n");
1702 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1703 }
1704
1705 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1706 if (IS_ERR(vc4_hdmi->audio_clock)) {
1707 DRM_ERROR("Failed to get audio clock\n");
1708 return PTR_ERR(vc4_hdmi->audio_clock);
1709 }
1710
1711 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1712 if (IS_ERR(vc4_hdmi->reset)) {
1713 DRM_ERROR("Failed to get HDMI reset line\n");
1714 return PTR_ERR(vc4_hdmi->reset);
1715 }
1716
1717 return 0;
1718 }
1719
1720 #ifdef CONFIG_PM
vc4_hdmi_runtime_suspend(struct device * dev)1721 static int vc4_hdmi_runtime_suspend(struct device *dev)
1722 {
1723 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1724
1725 clk_disable_unprepare(vc4_hdmi->hsm_clock);
1726
1727 return 0;
1728 }
1729
vc4_hdmi_runtime_resume(struct device * dev)1730 static int vc4_hdmi_runtime_resume(struct device *dev)
1731 {
1732 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1733 int ret;
1734
1735 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
1736 if (ret)
1737 return ret;
1738
1739 return 0;
1740 }
1741 #endif
1742
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)1743 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1744 {
1745 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1746 struct platform_device *pdev = to_platform_device(dev);
1747 struct drm_device *drm = dev_get_drvdata(master);
1748 struct vc4_hdmi *vc4_hdmi;
1749 struct drm_encoder *encoder;
1750 struct device_node *ddc_node;
1751 u32 value;
1752 int ret;
1753
1754 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1755 if (!vc4_hdmi)
1756 return -ENOMEM;
1757
1758 dev_set_drvdata(dev, vc4_hdmi);
1759 encoder = &vc4_hdmi->encoder.base.base;
1760 vc4_hdmi->encoder.base.type = variant->encoder_type;
1761 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1762 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1763 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1764 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1765 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1766 vc4_hdmi->pdev = pdev;
1767 vc4_hdmi->variant = variant;
1768
1769 ret = variant->init_resources(vc4_hdmi);
1770 if (ret)
1771 return ret;
1772
1773 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1774 if (!ddc_node) {
1775 DRM_ERROR("Failed to find ddc node in device tree\n");
1776 return -ENODEV;
1777 }
1778
1779 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1780 of_node_put(ddc_node);
1781 if (!vc4_hdmi->ddc) {
1782 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1783 return -EPROBE_DEFER;
1784 }
1785
1786 /* Only use the GPIO HPD pin if present in the DT, otherwise
1787 * we'll use the HDMI core's register.
1788 */
1789 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1790 enum of_gpio_flags hpd_gpio_flags;
1791
1792 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1793 "hpd-gpios", 0,
1794 &hpd_gpio_flags);
1795 if (vc4_hdmi->hpd_gpio < 0) {
1796 ret = vc4_hdmi->hpd_gpio;
1797 goto err_put_ddc;
1798 }
1799
1800 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1801 }
1802
1803 vc4_hdmi->disable_wifi_frequencies =
1804 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
1805
1806 /*
1807 * If we boot without any cable connected to the HDMI connector,
1808 * the firmware will skip the HSM initialization and leave it
1809 * with a rate of 0, resulting in a bus lockup when we're
1810 * accessing the registers even if it's enabled.
1811 *
1812 * Let's put a sensible default at runtime_resume so that we
1813 * don't end up in this situation.
1814 */
1815 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
1816 if (ret)
1817 goto err_put_ddc;
1818
1819 if (vc4_hdmi->variant->reset)
1820 vc4_hdmi->variant->reset(vc4_hdmi);
1821
1822 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
1823 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
1824 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
1825 clk_prepare_enable(vc4_hdmi->pixel_clock);
1826 clk_prepare_enable(vc4_hdmi->hsm_clock);
1827 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1828 }
1829
1830 pm_runtime_enable(dev);
1831
1832 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1833 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1834
1835 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1836 if (ret)
1837 goto err_destroy_encoder;
1838
1839 ret = vc4_hdmi_cec_init(vc4_hdmi);
1840 if (ret)
1841 goto err_destroy_conn;
1842
1843 ret = vc4_hdmi_audio_init(vc4_hdmi);
1844 if (ret)
1845 goto err_free_cec;
1846
1847 vc4_debugfs_add_file(drm, variant->debugfs_name,
1848 vc4_hdmi_debugfs_regs,
1849 vc4_hdmi);
1850
1851 return 0;
1852
1853 err_free_cec:
1854 vc4_hdmi_cec_exit(vc4_hdmi);
1855 err_destroy_conn:
1856 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1857 err_destroy_encoder:
1858 drm_encoder_cleanup(encoder);
1859 pm_runtime_disable(dev);
1860 err_put_ddc:
1861 put_device(&vc4_hdmi->ddc->dev);
1862
1863 return ret;
1864 }
1865
vc4_hdmi_unbind(struct device * dev,struct device * master,void * data)1866 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1867 void *data)
1868 {
1869 struct vc4_hdmi *vc4_hdmi;
1870
1871 /*
1872 * ASoC makes it a bit hard to retrieve a pointer to the
1873 * vc4_hdmi structure. Registering the card will overwrite our
1874 * device drvdata with a pointer to the snd_soc_card structure,
1875 * which can then be used to retrieve whatever drvdata we want
1876 * to associate.
1877 *
1878 * However, that doesn't fly in the case where we wouldn't
1879 * register an ASoC card (because of an old DT that is missing
1880 * the dmas properties for example), then the card isn't
1881 * registered and the device drvdata wouldn't be set.
1882 *
1883 * We can deal with both cases by making sure a snd_soc_card
1884 * pointer and a vc4_hdmi structure are pointing to the same
1885 * memory address, so we can treat them indistinctly without any
1886 * issue.
1887 */
1888 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
1889 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
1890 vc4_hdmi = dev_get_drvdata(dev);
1891
1892 kfree(vc4_hdmi->hdmi_regset.regs);
1893 kfree(vc4_hdmi->hd_regset.regs);
1894
1895 vc4_hdmi_cec_exit(vc4_hdmi);
1896 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1897 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
1898
1899 pm_runtime_disable(dev);
1900
1901 put_device(&vc4_hdmi->ddc->dev);
1902 }
1903
1904 static const struct component_ops vc4_hdmi_ops = {
1905 .bind = vc4_hdmi_bind,
1906 .unbind = vc4_hdmi_unbind,
1907 };
1908
vc4_hdmi_dev_probe(struct platform_device * pdev)1909 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1910 {
1911 return component_add(&pdev->dev, &vc4_hdmi_ops);
1912 }
1913
vc4_hdmi_dev_remove(struct platform_device * pdev)1914 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1915 {
1916 component_del(&pdev->dev, &vc4_hdmi_ops);
1917 return 0;
1918 }
1919
1920 static const struct vc4_hdmi_variant bcm2835_variant = {
1921 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1922 .debugfs_name = "hdmi_regs",
1923 .card_name = "vc4-hdmi",
1924 .max_pixel_clock = 162000000,
1925 .cec_available = true,
1926 .registers = vc4_hdmi_fields,
1927 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
1928
1929 .init_resources = vc4_hdmi_init_resources,
1930 .csc_setup = vc4_hdmi_csc_setup,
1931 .reset = vc4_hdmi_reset,
1932 .set_timings = vc4_hdmi_set_timings,
1933 .phy_init = vc4_hdmi_phy_init,
1934 .phy_disable = vc4_hdmi_phy_disable,
1935 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
1936 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
1937 .channel_map = vc4_hdmi_channel_map,
1938 };
1939
1940 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1941 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
1942 .debugfs_name = "hdmi0_regs",
1943 .card_name = "vc4-hdmi-0",
1944 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
1945 .registers = vc5_hdmi_hdmi0_fields,
1946 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1947 .phy_lane_mapping = {
1948 PHY_LANE_0,
1949 PHY_LANE_1,
1950 PHY_LANE_2,
1951 PHY_LANE_CK,
1952 },
1953 .unsupported_odd_h_timings = true,
1954
1955 .init_resources = vc5_hdmi_init_resources,
1956 .csc_setup = vc5_hdmi_csc_setup,
1957 .reset = vc5_hdmi_reset,
1958 .set_timings = vc5_hdmi_set_timings,
1959 .phy_init = vc5_hdmi_phy_init,
1960 .phy_disable = vc5_hdmi_phy_disable,
1961 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
1962 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
1963 .channel_map = vc5_hdmi_channel_map,
1964 };
1965
1966 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1967 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
1968 .debugfs_name = "hdmi1_regs",
1969 .card_name = "vc4-hdmi-1",
1970 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
1971 .registers = vc5_hdmi_hdmi1_fields,
1972 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1973 .phy_lane_mapping = {
1974 PHY_LANE_1,
1975 PHY_LANE_0,
1976 PHY_LANE_CK,
1977 PHY_LANE_2,
1978 },
1979 .unsupported_odd_h_timings = true,
1980
1981 .init_resources = vc5_hdmi_init_resources,
1982 .csc_setup = vc5_hdmi_csc_setup,
1983 .reset = vc5_hdmi_reset,
1984 .set_timings = vc5_hdmi_set_timings,
1985 .phy_init = vc5_hdmi_phy_init,
1986 .phy_disable = vc5_hdmi_phy_disable,
1987 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
1988 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
1989 .channel_map = vc5_hdmi_channel_map,
1990 };
1991
1992 static const struct of_device_id vc4_hdmi_dt_match[] = {
1993 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
1994 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
1995 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
1996 {}
1997 };
1998
1999 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2000 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2001 vc4_hdmi_runtime_resume,
2002 NULL)
2003 };
2004
2005 struct platform_driver vc4_hdmi_driver = {
2006 .probe = vc4_hdmi_dev_probe,
2007 .remove = vc4_hdmi_dev_remove,
2008 .driver = {
2009 .name = "vc4_hdmi",
2010 .of_match_table = vc4_hdmi_dt_match,
2011 .pm = &vc4_hdmi_pm_ops,
2012 },
2013 };
2014