1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/format/u_format.h"
33 #include "util/u_hash_table.h"
34 #include "util/u_screen.h"
35 #include "util/u_transfer_helper.h"
36 #include "util/ralloc.h"
37
38 #include <xf86drm.h>
39 #include "drm-uapi/drm_fourcc.h"
40 #include "drm-uapi/vc4_drm.h"
41 #include "vc4_screen.h"
42 #include "vc4_context.h"
43 #include "vc4_resource.h"
44
45 static const struct debug_named_value vc4_debug_options[] = {
46 { "cl", VC4_DEBUG_CL,
47 "Dump command list during creation" },
48 { "surf", VC4_DEBUG_SURFACE,
49 "Dump surface layouts" },
50 { "qpu", VC4_DEBUG_QPU,
51 "Dump generated QPU instructions" },
52 { "qir", VC4_DEBUG_QIR,
53 "Dump QPU IR during program compile" },
54 { "nir", VC4_DEBUG_NIR,
55 "Dump NIR during program compile" },
56 { "tgsi", VC4_DEBUG_TGSI,
57 "Dump TGSI during program compile" },
58 { "shaderdb", VC4_DEBUG_SHADERDB,
59 "Dump program compile information for shader-db analysis" },
60 { "perf", VC4_DEBUG_PERF,
61 "Print during performance-related events" },
62 { "norast", VC4_DEBUG_NORAST,
63 "Skip actual hardware execution of commands" },
64 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
65 "Flush after each draw call" },
66 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
67 "Wait for finish after each flush" },
68 #ifdef USE_VC4_SIMULATOR
69 { "dump", VC4_DEBUG_DUMP,
70 "Write a GPU command stream trace file" },
71 #endif
72 { NULL }
73 };
74
75 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
76 uint32_t vc4_debug;
77
78 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)79 vc4_screen_get_name(struct pipe_screen *pscreen)
80 {
81 struct vc4_screen *screen = vc4_screen(pscreen);
82
83 if (!screen->name) {
84 screen->name = ralloc_asprintf(screen,
85 "VC4 V3D %d.%d",
86 screen->v3d_ver / 10,
87 screen->v3d_ver % 10);
88 }
89
90 return screen->name;
91 }
92
93 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)94 vc4_screen_get_vendor(struct pipe_screen *pscreen)
95 {
96 return "Broadcom";
97 }
98
99 static void
vc4_screen_destroy(struct pipe_screen * pscreen)100 vc4_screen_destroy(struct pipe_screen *pscreen)
101 {
102 struct vc4_screen *screen = vc4_screen(pscreen);
103
104 _mesa_hash_table_destroy(screen->bo_handles, NULL);
105 vc4_bufmgr_destroy(pscreen);
106 slab_destroy_parent(&screen->transfer_pool);
107 if (screen->ro)
108 screen->ro->destroy(screen->ro);
109
110 #ifdef USE_VC4_SIMULATOR
111 vc4_simulator_destroy(screen);
112 #endif
113
114 u_transfer_helper_destroy(pscreen->transfer_helper);
115
116 close(screen->fd);
117 ralloc_free(pscreen);
118 }
119
120 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)121 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
122 {
123 struct drm_vc4_get_param p = {
124 .param = feature,
125 };
126 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
127
128 if (ret != 0)
129 return false;
130
131 return p.value;
132 }
133
134 static int
vc4_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)135 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
136 {
137 struct vc4_screen *screen = vc4_screen(pscreen);
138
139 switch (param) {
140 /* Supported features (boolean caps). */
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
142 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
143 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
144 case PIPE_CAP_NPOT_TEXTURES:
145 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
146 case PIPE_CAP_TEXTURE_MULTISAMPLE:
147 case PIPE_CAP_TEXTURE_SWIZZLE:
148 case PIPE_CAP_TEXTURE_BARRIER:
149 case PIPE_CAP_TGSI_TEXCOORD:
150 return 1;
151
152 case PIPE_CAP_NATIVE_FENCE_FD:
153 return screen->has_syncobj;
154
155 case PIPE_CAP_TILE_RASTER_ORDER:
156 return vc4_has_feature(screen,
157 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
158
159 /* lying for GL 2.0 */
160 case PIPE_CAP_POINT_SPRITE:
161 return 1;
162
163 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
164 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
165 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
166 return 1;
167
168 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
169 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
170 return 1;
171
172 /* Texturing. */
173 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
174 return 2048;
175 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
176 return VC4_MAX_MIP_LEVELS;
177 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
178 return 0;
179
180 case PIPE_CAP_MAX_VARYINGS:
181 return 8;
182
183 case PIPE_CAP_VENDOR_ID:
184 return 0x14E4;
185 case PIPE_CAP_ACCELERATED:
186 return 1;
187 case PIPE_CAP_VIDEO_MEMORY: {
188 uint64_t system_memory;
189
190 if (!os_get_total_physical_memory(&system_memory))
191 return 0;
192
193 return (int)(system_memory >> 20);
194 }
195 case PIPE_CAP_UMA:
196 return 1;
197
198 case PIPE_CAP_ALPHA_TEST:
199 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
200 case PIPE_CAP_TWO_SIDED_COLOR:
201 case PIPE_CAP_TEXRECT:
202 case PIPE_CAP_IMAGE_STORE_FORMATTED:
203 return 0;
204
205 case PIPE_CAP_SUPPORTED_PRIM_MODES:
206 return screen->prim_types;
207
208 default:
209 return u_pipe_screen_get_param_defaults(pscreen, param);
210 }
211 }
212
213 static float
vc4_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)214 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
215 {
216 switch (param) {
217 case PIPE_CAPF_MIN_LINE_WIDTH:
218 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
219 case PIPE_CAPF_MIN_POINT_SIZE:
220 case PIPE_CAPF_MIN_POINT_SIZE_AA:
221 return 1;
222
223 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
224 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
225 return 0.1;
226
227 case PIPE_CAPF_MAX_LINE_WIDTH:
228 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
229 return 32;
230
231 case PIPE_CAPF_MAX_POINT_SIZE:
232 case PIPE_CAPF_MAX_POINT_SIZE_AA:
233 return 512.0f;
234
235 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
236 return 0.0f;
237 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
238 return 0.0f;
239
240 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
241 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
242 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
243 return 0.0f;
244 default:
245 fprintf(stderr, "unknown paramf %d\n", param);
246 return 0;
247 }
248 }
249
250 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)251 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
252 enum pipe_shader_type shader,
253 enum pipe_shader_cap param)
254 {
255 if (shader != PIPE_SHADER_VERTEX &&
256 shader != PIPE_SHADER_FRAGMENT) {
257 return 0;
258 }
259
260 /* this is probably not totally correct.. but it's a start: */
261 switch (param) {
262 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
263 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
264 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
265 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
266 return 16384;
267
268 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
269 return vc4_screen(pscreen)->has_control_flow;
270
271 case PIPE_SHADER_CAP_MAX_INPUTS:
272 return 8;
273 case PIPE_SHADER_CAP_MAX_OUTPUTS:
274 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
275 case PIPE_SHADER_CAP_MAX_TEMPS:
276 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
277 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
278 return 16 * 1024 * sizeof(float);
279 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
280 return 1;
281 case PIPE_SHADER_CAP_CONT_SUPPORTED:
282 return 0;
283 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
284 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
285 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
286 return 0;
287 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
288 return 1;
289 case PIPE_SHADER_CAP_SUBROUTINES:
290 return 0;
291 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
292 return 0;
293 case PIPE_SHADER_CAP_INTEGERS:
294 return 1;
295 case PIPE_SHADER_CAP_INT64_ATOMICS:
296 case PIPE_SHADER_CAP_FP16:
297 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
298 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
299 case PIPE_SHADER_CAP_INT16:
300 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
301 case PIPE_SHADER_CAP_DROUND_SUPPORTED:
302 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
303 case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
304 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
305 return 0;
306 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
307 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
308 return VC4_MAX_TEXTURE_SAMPLERS;
309 case PIPE_SHADER_CAP_PREFERRED_IR:
310 return PIPE_SHADER_IR_NIR;
311 case PIPE_SHADER_CAP_SUPPORTED_IRS:
312 return 1 << PIPE_SHADER_IR_NIR;
313 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
314 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
315 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
316 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
317 return 0;
318 default:
319 fprintf(stderr, "unknown shader param %d\n", param);
320 return 0;
321 }
322 return 0;
323 }
324
325 static bool
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)326 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
327 enum pipe_format format,
328 enum pipe_texture_target target,
329 unsigned sample_count,
330 unsigned storage_sample_count,
331 unsigned usage)
332 {
333 struct vc4_screen *screen = vc4_screen(pscreen);
334
335 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
336 return false;
337
338 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
339 return false;
340
341 if (target >= PIPE_MAX_TEXTURE_TYPES) {
342 return false;
343 }
344
345 if (usage & PIPE_BIND_VERTEX_BUFFER) {
346 switch (format) {
347 case PIPE_FORMAT_R32G32B32A32_FLOAT:
348 case PIPE_FORMAT_R32G32B32_FLOAT:
349 case PIPE_FORMAT_R32G32_FLOAT:
350 case PIPE_FORMAT_R32_FLOAT:
351 case PIPE_FORMAT_R32G32B32A32_SNORM:
352 case PIPE_FORMAT_R32G32B32_SNORM:
353 case PIPE_FORMAT_R32G32_SNORM:
354 case PIPE_FORMAT_R32_SNORM:
355 case PIPE_FORMAT_R32G32B32A32_SSCALED:
356 case PIPE_FORMAT_R32G32B32_SSCALED:
357 case PIPE_FORMAT_R32G32_SSCALED:
358 case PIPE_FORMAT_R32_SSCALED:
359 case PIPE_FORMAT_R16G16B16A16_UNORM:
360 case PIPE_FORMAT_R16G16B16_UNORM:
361 case PIPE_FORMAT_R16G16_UNORM:
362 case PIPE_FORMAT_R16_UNORM:
363 case PIPE_FORMAT_R16G16B16A16_SNORM:
364 case PIPE_FORMAT_R16G16B16_SNORM:
365 case PIPE_FORMAT_R16G16_SNORM:
366 case PIPE_FORMAT_R16_SNORM:
367 case PIPE_FORMAT_R16G16B16A16_USCALED:
368 case PIPE_FORMAT_R16G16B16_USCALED:
369 case PIPE_FORMAT_R16G16_USCALED:
370 case PIPE_FORMAT_R16_USCALED:
371 case PIPE_FORMAT_R16G16B16A16_SSCALED:
372 case PIPE_FORMAT_R16G16B16_SSCALED:
373 case PIPE_FORMAT_R16G16_SSCALED:
374 case PIPE_FORMAT_R16_SSCALED:
375 case PIPE_FORMAT_R8G8B8A8_UNORM:
376 case PIPE_FORMAT_R8G8B8_UNORM:
377 case PIPE_FORMAT_R8G8_UNORM:
378 case PIPE_FORMAT_R8_UNORM:
379 case PIPE_FORMAT_R8G8B8A8_SNORM:
380 case PIPE_FORMAT_R8G8B8_SNORM:
381 case PIPE_FORMAT_R8G8_SNORM:
382 case PIPE_FORMAT_R8_SNORM:
383 case PIPE_FORMAT_R8G8B8A8_USCALED:
384 case PIPE_FORMAT_R8G8B8_USCALED:
385 case PIPE_FORMAT_R8G8_USCALED:
386 case PIPE_FORMAT_R8_USCALED:
387 case PIPE_FORMAT_R8G8B8A8_SSCALED:
388 case PIPE_FORMAT_R8G8B8_SSCALED:
389 case PIPE_FORMAT_R8G8_SSCALED:
390 case PIPE_FORMAT_R8_SSCALED:
391 break;
392 default:
393 return false;
394 }
395 }
396
397 if ((usage & PIPE_BIND_RENDER_TARGET) &&
398 !vc4_rt_format_supported(format)) {
399 return false;
400 }
401
402 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
403 (!vc4_tex_format_supported(format) ||
404 (format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
405 return false;
406 }
407
408 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
409 format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
410 format != PIPE_FORMAT_X8Z24_UNORM) {
411 return false;
412 }
413
414 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
415 format != PIPE_FORMAT_R8_UINT &&
416 format != PIPE_FORMAT_R16_UINT) {
417 return false;
418 }
419
420 return true;
421 }
422
vc4_get_modifiers(struct pipe_screen * pscreen,int * num)423 static const uint64_t *vc4_get_modifiers(struct pipe_screen *pscreen, int *num)
424 {
425 struct vc4_screen *screen = vc4_screen(pscreen);
426 static const uint64_t all_modifiers[] = {
427 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
428 DRM_FORMAT_MOD_LINEAR,
429 };
430 int m;
431
432 /* We support both modifiers (tiled and linear) for all sampler
433 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
434 * we shouldn't advertise the tiled formats.
435 */
436 if (screen->has_tiling_ioctl) {
437 m = 0;
438 *num = 2;
439 } else{
440 m = 1;
441 *num = 1;
442 }
443
444 return &all_modifiers[m];
445 }
446
447 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)448 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
449 enum pipe_format format, int max,
450 uint64_t *modifiers,
451 unsigned int *external_only,
452 int *count)
453 {
454 const uint64_t *available_modifiers;
455 int i;
456 bool tex_will_lower;
457 int num_modifiers;
458
459 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
460
461 if (!modifiers) {
462 *count = num_modifiers;
463 return;
464 }
465
466 *count = MIN2(max, num_modifiers);
467 tex_will_lower = !vc4_tex_format_supported(format);
468 for (i = 0; i < *count; i++) {
469 modifiers[i] = available_modifiers[i];
470 if (external_only)
471 external_only[i] = tex_will_lower;
472 }
473 }
474
475 static bool
vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)476 vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
477 uint64_t modifier,
478 enum pipe_format format,
479 bool *external_only)
480 {
481 const uint64_t *available_modifiers;
482 int i, num_modifiers;
483
484 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
485
486 for (i = 0; i < num_modifiers; i++) {
487 if (modifier == available_modifiers[i]) {
488 if (external_only)
489 *external_only = !vc4_tex_format_supported(format);
490
491 return true;
492 }
493 }
494
495 return false;
496 }
497
498 static bool
vc4_get_chip_info(struct vc4_screen * screen)499 vc4_get_chip_info(struct vc4_screen *screen)
500 {
501 struct drm_vc4_get_param ident0 = {
502 .param = DRM_VC4_PARAM_V3D_IDENT0,
503 };
504 struct drm_vc4_get_param ident1 = {
505 .param = DRM_VC4_PARAM_V3D_IDENT1,
506 };
507 int ret;
508
509 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
510 if (ret != 0) {
511 if (errno == EINVAL) {
512 /* Backwards compatibility with 2835 kernels which
513 * only do V3D 2.1.
514 */
515 screen->v3d_ver = 21;
516 return true;
517 } else {
518 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
519 strerror(errno));
520 return false;
521 }
522 }
523 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
524 if (ret != 0) {
525 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
526 strerror(errno));
527 return false;
528 }
529
530 uint32_t major = (ident0.value >> 24) & 0xff;
531 uint32_t minor = (ident1.value >> 0) & 0xf;
532 screen->v3d_ver = major * 10 + minor;
533
534 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
535 fprintf(stderr,
536 "V3D %d.%d not supported by this version of Mesa.\n",
537 screen->v3d_ver / 10,
538 screen->v3d_ver % 10);
539 return false;
540 }
541
542 return true;
543 }
544
545 struct pipe_screen *
vc4_screen_create(int fd,struct renderonly * ro)546 vc4_screen_create(int fd, struct renderonly *ro)
547 {
548 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
549 uint64_t syncobj_cap = 0;
550 struct pipe_screen *pscreen;
551 int err;
552
553 pscreen = &screen->base;
554
555 pscreen->destroy = vc4_screen_destroy;
556 pscreen->get_param = vc4_screen_get_param;
557 pscreen->get_paramf = vc4_screen_get_paramf;
558 pscreen->get_shader_param = vc4_screen_get_shader_param;
559 pscreen->context_create = vc4_context_create;
560 pscreen->is_format_supported = vc4_screen_is_format_supported;
561
562 screen->fd = fd;
563 screen->ro = ro;
564
565 list_inithead(&screen->bo_cache.time_list);
566 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
567 screen->bo_handles = util_hash_table_create_ptr_keys();
568
569 screen->has_control_flow =
570 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
571 screen->has_etc1 =
572 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
573 screen->has_threaded_fs =
574 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
575 screen->has_madvise =
576 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
577 screen->has_perfmon_ioctl =
578 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
579
580 err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
581 if (err == 0 && syncobj_cap)
582 screen->has_syncobj = true;
583
584 if (!vc4_get_chip_info(screen))
585 goto fail;
586
587 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
588
589 vc4_fence_screen_init(screen);
590
591 vc4_debug = debug_get_option_vc4_debug();
592
593 #ifdef USE_VC4_SIMULATOR
594 vc4_simulator_init(screen);
595 #endif
596
597 vc4_resource_screen_init(pscreen);
598
599 pscreen->get_name = vc4_screen_get_name;
600 pscreen->get_vendor = vc4_screen_get_vendor;
601 pscreen->get_device_vendor = vc4_screen_get_vendor;
602 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
603 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
604 pscreen->is_dmabuf_modifier_supported = vc4_screen_is_dmabuf_modifier_supported;
605
606 if (screen->has_perfmon_ioctl) {
607 pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
608 pscreen->get_driver_query_info = vc4_get_driver_query_info;
609 }
610
611 /* Generate the bitmask of supported draw primitives. */
612 screen->prim_types = BITFIELD_BIT(PIPE_PRIM_POINTS) |
613 BITFIELD_BIT(PIPE_PRIM_LINES) |
614 BITFIELD_BIT(PIPE_PRIM_LINE_LOOP) |
615 BITFIELD_BIT(PIPE_PRIM_LINE_STRIP) |
616 BITFIELD_BIT(PIPE_PRIM_TRIANGLES) |
617 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_STRIP) |
618 BITFIELD_BIT(PIPE_PRIM_TRIANGLE_FAN);
619
620
621 return pscreen;
622
623 fail:
624 close(fd);
625 ralloc_free(pscreen);
626 return NULL;
627 }
628