1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_MAX 303 }; 304 305 /* Valid range for general commands that don't work over an object */ 306 enum { 307 MLX5_CMD_OP_GENERAL_START = 0xb00, 308 MLX5_CMD_OP_GENERAL_END = 0xd00, 309 }; 310 311 struct mlx5_ifc_flow_table_fields_supported_bits { 312 u8 outer_dmac[0x1]; 313 u8 outer_smac[0x1]; 314 u8 outer_ether_type[0x1]; 315 u8 outer_ip_version[0x1]; 316 u8 outer_first_prio[0x1]; 317 u8 outer_first_cfi[0x1]; 318 u8 outer_first_vid[0x1]; 319 u8 outer_ipv4_ttl[0x1]; 320 u8 outer_second_prio[0x1]; 321 u8 outer_second_cfi[0x1]; 322 u8 outer_second_vid[0x1]; 323 u8 reserved_at_b[0x1]; 324 u8 outer_sip[0x1]; 325 u8 outer_dip[0x1]; 326 u8 outer_frag[0x1]; 327 u8 outer_ip_protocol[0x1]; 328 u8 outer_ip_ecn[0x1]; 329 u8 outer_ip_dscp[0x1]; 330 u8 outer_udp_sport[0x1]; 331 u8 outer_udp_dport[0x1]; 332 u8 outer_tcp_sport[0x1]; 333 u8 outer_tcp_dport[0x1]; 334 u8 outer_tcp_flags[0x1]; 335 u8 outer_gre_protocol[0x1]; 336 u8 outer_gre_key[0x1]; 337 u8 outer_vxlan_vni[0x1]; 338 u8 outer_geneve_vni[0x1]; 339 u8 outer_geneve_oam[0x1]; 340 u8 outer_geneve_protocol_type[0x1]; 341 u8 outer_geneve_opt_len[0x1]; 342 u8 reserved_at_1e[0x1]; 343 u8 source_eswitch_port[0x1]; 344 345 u8 inner_dmac[0x1]; 346 u8 inner_smac[0x1]; 347 u8 inner_ether_type[0x1]; 348 u8 inner_ip_version[0x1]; 349 u8 inner_first_prio[0x1]; 350 u8 inner_first_cfi[0x1]; 351 u8 inner_first_vid[0x1]; 352 u8 reserved_at_27[0x1]; 353 u8 inner_second_prio[0x1]; 354 u8 inner_second_cfi[0x1]; 355 u8 inner_second_vid[0x1]; 356 u8 reserved_at_2b[0x1]; 357 u8 inner_sip[0x1]; 358 u8 inner_dip[0x1]; 359 u8 inner_frag[0x1]; 360 u8 inner_ip_protocol[0x1]; 361 u8 inner_ip_ecn[0x1]; 362 u8 inner_ip_dscp[0x1]; 363 u8 inner_udp_sport[0x1]; 364 u8 inner_udp_dport[0x1]; 365 u8 inner_tcp_sport[0x1]; 366 u8 inner_tcp_dport[0x1]; 367 u8 inner_tcp_flags[0x1]; 368 u8 reserved_at_37[0x9]; 369 370 u8 geneve_tlv_option_0_data[0x1]; 371 u8 reserved_at_41[0x4]; 372 u8 outer_first_mpls_over_udp[0x4]; 373 u8 outer_first_mpls_over_gre[0x4]; 374 u8 inner_first_mpls[0x4]; 375 u8 outer_first_mpls[0x4]; 376 u8 reserved_at_55[0x2]; 377 u8 outer_esp_spi[0x1]; 378 u8 reserved_at_58[0x2]; 379 u8 bth_dst_qp[0x1]; 380 u8 reserved_at_5b[0x5]; 381 382 u8 reserved_at_60[0x18]; 383 u8 metadata_reg_c_7[0x1]; 384 u8 metadata_reg_c_6[0x1]; 385 u8 metadata_reg_c_5[0x1]; 386 u8 metadata_reg_c_4[0x1]; 387 u8 metadata_reg_c_3[0x1]; 388 u8 metadata_reg_c_2[0x1]; 389 u8 metadata_reg_c_1[0x1]; 390 u8 metadata_reg_c_0[0x1]; 391 }; 392 393 struct mlx5_ifc_flow_table_prop_layout_bits { 394 u8 ft_support[0x1]; 395 u8 reserved_at_1[0x1]; 396 u8 flow_counter[0x1]; 397 u8 flow_modify_en[0x1]; 398 u8 modify_root[0x1]; 399 u8 identified_miss_table_mode[0x1]; 400 u8 flow_table_modify[0x1]; 401 u8 reformat[0x1]; 402 u8 decap[0x1]; 403 u8 reserved_at_9[0x1]; 404 u8 pop_vlan[0x1]; 405 u8 push_vlan[0x1]; 406 u8 reserved_at_c[0x1]; 407 u8 pop_vlan_2[0x1]; 408 u8 push_vlan_2[0x1]; 409 u8 reformat_and_vlan_action[0x1]; 410 u8 reserved_at_10[0x1]; 411 u8 sw_owner[0x1]; 412 u8 reformat_l3_tunnel_to_l2[0x1]; 413 u8 reformat_l2_to_l3_tunnel[0x1]; 414 u8 reformat_and_modify_action[0x1]; 415 u8 ignore_flow_level[0x1]; 416 u8 reserved_at_16[0x1]; 417 u8 table_miss_action_domain[0x1]; 418 u8 termination_table[0x1]; 419 u8 reformat_and_fwd_to_table[0x1]; 420 u8 reserved_at_1a[0x2]; 421 u8 ipsec_encrypt[0x1]; 422 u8 ipsec_decrypt[0x1]; 423 u8 sw_owner_v2[0x1]; 424 u8 reserved_at_1f[0x1]; 425 426 u8 termination_table_raw_traffic[0x1]; 427 u8 reserved_at_21[0x1]; 428 u8 log_max_ft_size[0x6]; 429 u8 log_max_modify_header_context[0x8]; 430 u8 max_modify_header_actions[0x8]; 431 u8 max_ft_level[0x8]; 432 433 u8 reserved_at_40[0x20]; 434 435 u8 reserved_at_60[0x18]; 436 u8 log_max_ft_num[0x8]; 437 438 u8 reserved_at_80[0x10]; 439 u8 log_max_flow_counter[0x8]; 440 u8 log_max_destination[0x8]; 441 442 u8 reserved_at_a0[0x18]; 443 u8 log_max_flow[0x8]; 444 445 u8 reserved_at_c0[0x40]; 446 447 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 450 }; 451 452 struct mlx5_ifc_odp_per_transport_service_cap_bits { 453 u8 send[0x1]; 454 u8 receive[0x1]; 455 u8 write[0x1]; 456 u8 read[0x1]; 457 u8 atomic[0x1]; 458 u8 srq_receive[0x1]; 459 u8 reserved_at_6[0x1a]; 460 }; 461 462 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 463 u8 smac_47_16[0x20]; 464 465 u8 smac_15_0[0x10]; 466 u8 ethertype[0x10]; 467 468 u8 dmac_47_16[0x20]; 469 470 u8 dmac_15_0[0x10]; 471 u8 first_prio[0x3]; 472 u8 first_cfi[0x1]; 473 u8 first_vid[0xc]; 474 475 u8 ip_protocol[0x8]; 476 u8 ip_dscp[0x6]; 477 u8 ip_ecn[0x2]; 478 u8 cvlan_tag[0x1]; 479 u8 svlan_tag[0x1]; 480 u8 frag[0x1]; 481 u8 ip_version[0x4]; 482 u8 tcp_flags[0x9]; 483 484 u8 tcp_sport[0x10]; 485 u8 tcp_dport[0x10]; 486 487 u8 reserved_at_c0[0x18]; 488 u8 ttl_hoplimit[0x8]; 489 490 u8 udp_sport[0x10]; 491 u8 udp_dport[0x10]; 492 493 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 496 }; 497 498 struct mlx5_ifc_nvgre_key_bits { 499 u8 hi[0x18]; 500 u8 lo[0x8]; 501 }; 502 503 union mlx5_ifc_gre_key_bits { 504 struct mlx5_ifc_nvgre_key_bits nvgre; 505 u8 key[0x20]; 506 }; 507 508 struct mlx5_ifc_fte_match_set_misc_bits { 509 u8 gre_c_present[0x1]; 510 u8 reserved_at_1[0x1]; 511 u8 gre_k_present[0x1]; 512 u8 gre_s_present[0x1]; 513 u8 source_vhca_port[0x4]; 514 u8 source_sqn[0x18]; 515 516 u8 source_eswitch_owner_vhca_id[0x10]; 517 u8 source_port[0x10]; 518 519 u8 outer_second_prio[0x3]; 520 u8 outer_second_cfi[0x1]; 521 u8 outer_second_vid[0xc]; 522 u8 inner_second_prio[0x3]; 523 u8 inner_second_cfi[0x1]; 524 u8 inner_second_vid[0xc]; 525 526 u8 outer_second_cvlan_tag[0x1]; 527 u8 inner_second_cvlan_tag[0x1]; 528 u8 outer_second_svlan_tag[0x1]; 529 u8 inner_second_svlan_tag[0x1]; 530 u8 reserved_at_64[0xc]; 531 u8 gre_protocol[0x10]; 532 533 union mlx5_ifc_gre_key_bits gre_key; 534 535 u8 vxlan_vni[0x18]; 536 u8 reserved_at_b8[0x8]; 537 538 u8 geneve_vni[0x18]; 539 u8 reserved_at_d8[0x7]; 540 u8 geneve_oam[0x1]; 541 542 u8 reserved_at_e0[0xc]; 543 u8 outer_ipv6_flow_label[0x14]; 544 545 u8 reserved_at_100[0xc]; 546 u8 inner_ipv6_flow_label[0x14]; 547 548 u8 reserved_at_120[0xa]; 549 u8 geneve_opt_len[0x6]; 550 u8 geneve_protocol_type[0x10]; 551 552 u8 reserved_at_140[0x8]; 553 u8 bth_dst_qp[0x18]; 554 u8 reserved_at_160[0x20]; 555 u8 outer_esp_spi[0x20]; 556 u8 reserved_at_1a0[0x60]; 557 }; 558 559 struct mlx5_ifc_fte_match_mpls_bits { 560 u8 mpls_label[0x14]; 561 u8 mpls_exp[0x3]; 562 u8 mpls_s_bos[0x1]; 563 u8 mpls_ttl[0x8]; 564 }; 565 566 struct mlx5_ifc_fte_match_set_misc2_bits { 567 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 568 569 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 574 575 u8 metadata_reg_c_7[0x20]; 576 577 u8 metadata_reg_c_6[0x20]; 578 579 u8 metadata_reg_c_5[0x20]; 580 581 u8 metadata_reg_c_4[0x20]; 582 583 u8 metadata_reg_c_3[0x20]; 584 585 u8 metadata_reg_c_2[0x20]; 586 587 u8 metadata_reg_c_1[0x20]; 588 589 u8 metadata_reg_c_0[0x20]; 590 591 u8 metadata_reg_a[0x20]; 592 593 u8 reserved_at_1a0[0x60]; 594 }; 595 596 struct mlx5_ifc_fte_match_set_misc3_bits { 597 u8 inner_tcp_seq_num[0x20]; 598 599 u8 outer_tcp_seq_num[0x20]; 600 601 u8 inner_tcp_ack_num[0x20]; 602 603 u8 outer_tcp_ack_num[0x20]; 604 605 u8 reserved_at_80[0x8]; 606 u8 outer_vxlan_gpe_vni[0x18]; 607 608 u8 outer_vxlan_gpe_next_protocol[0x8]; 609 u8 outer_vxlan_gpe_flags[0x8]; 610 u8 reserved_at_b0[0x10]; 611 612 u8 icmp_header_data[0x20]; 613 614 u8 icmpv6_header_data[0x20]; 615 616 u8 icmp_type[0x8]; 617 u8 icmp_code[0x8]; 618 u8 icmpv6_type[0x8]; 619 u8 icmpv6_code[0x8]; 620 621 u8 geneve_tlv_option_0_data[0x20]; 622 623 u8 reserved_at_140[0xc0]; 624 }; 625 626 struct mlx5_ifc_cmd_pas_bits { 627 u8 pa_h[0x20]; 628 629 u8 pa_l[0x14]; 630 u8 reserved_at_34[0xc]; 631 }; 632 633 struct mlx5_ifc_uint64_bits { 634 u8 hi[0x20]; 635 636 u8 lo[0x20]; 637 }; 638 639 enum { 640 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 641 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 642 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 643 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 644 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 645 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 646 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 647 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 648 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 649 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 650 }; 651 652 struct mlx5_ifc_ads_bits { 653 u8 fl[0x1]; 654 u8 free_ar[0x1]; 655 u8 reserved_at_2[0xe]; 656 u8 pkey_index[0x10]; 657 658 u8 reserved_at_20[0x8]; 659 u8 grh[0x1]; 660 u8 mlid[0x7]; 661 u8 rlid[0x10]; 662 663 u8 ack_timeout[0x5]; 664 u8 reserved_at_45[0x3]; 665 u8 src_addr_index[0x8]; 666 u8 reserved_at_50[0x4]; 667 u8 stat_rate[0x4]; 668 u8 hop_limit[0x8]; 669 670 u8 reserved_at_60[0x4]; 671 u8 tclass[0x8]; 672 u8 flow_label[0x14]; 673 674 u8 rgid_rip[16][0x8]; 675 676 u8 reserved_at_100[0x4]; 677 u8 f_dscp[0x1]; 678 u8 f_ecn[0x1]; 679 u8 reserved_at_106[0x1]; 680 u8 f_eth_prio[0x1]; 681 u8 ecn[0x2]; 682 u8 dscp[0x6]; 683 u8 udp_sport[0x10]; 684 685 u8 dei_cfi[0x1]; 686 u8 eth_prio[0x3]; 687 u8 sl[0x4]; 688 u8 vhca_port_num[0x8]; 689 u8 rmac_47_32[0x10]; 690 691 u8 rmac_31_0[0x20]; 692 }; 693 694 struct mlx5_ifc_flow_table_nic_cap_bits { 695 u8 nic_rx_multi_path_tirs[0x1]; 696 u8 nic_rx_multi_path_tirs_fts[0x1]; 697 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 698 u8 reserved_at_3[0x4]; 699 u8 sw_owner_reformat_supported[0x1]; 700 u8 reserved_at_8[0x18]; 701 702 u8 encap_general_header[0x1]; 703 u8 reserved_at_21[0xa]; 704 u8 log_max_packet_reformat_context[0x5]; 705 u8 reserved_at_30[0x6]; 706 u8 max_encap_header_size[0xa]; 707 u8 reserved_at_40[0x1c0]; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 710 711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 714 715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 716 717 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 718 719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 720 721 u8 reserved_at_e00[0x1200]; 722 723 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 724 725 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 726 727 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 728 729 u8 reserved_at_20c0[0x5f40]; 730 }; 731 732 enum { 733 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 734 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 735 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 736 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 737 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 738 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 739 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 740 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 741 }; 742 743 struct mlx5_ifc_flow_table_eswitch_cap_bits { 744 u8 fdb_to_vport_reg_c_id[0x8]; 745 u8 reserved_at_8[0xd]; 746 u8 fdb_modify_header_fwd_to_table[0x1]; 747 u8 reserved_at_16[0x1]; 748 u8 flow_source[0x1]; 749 u8 reserved_at_18[0x2]; 750 u8 multi_fdb_encap[0x1]; 751 u8 egress_acl_forward_to_vport[0x1]; 752 u8 fdb_multi_path_to_table[0x1]; 753 u8 reserved_at_1d[0x3]; 754 755 u8 reserved_at_20[0x1e0]; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 758 759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 760 761 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 762 763 u8 reserved_at_800[0x1000]; 764 765 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 766 767 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 768 769 u8 sw_steering_uplink_icm_address_rx[0x40]; 770 771 u8 sw_steering_uplink_icm_address_tx[0x40]; 772 773 u8 reserved_at_1900[0x6700]; 774 }; 775 776 enum { 777 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 778 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 779 }; 780 781 struct mlx5_ifc_e_switch_cap_bits { 782 u8 vport_svlan_strip[0x1]; 783 u8 vport_cvlan_strip[0x1]; 784 u8 vport_svlan_insert[0x1]; 785 u8 vport_cvlan_insert_if_not_exist[0x1]; 786 u8 vport_cvlan_insert_overwrite[0x1]; 787 u8 reserved_at_5[0x3]; 788 u8 esw_uplink_ingress_acl[0x1]; 789 u8 reserved_at_9[0x10]; 790 u8 esw_functions_changed[0x1]; 791 u8 reserved_at_1a[0x1]; 792 u8 ecpf_vport_exists[0x1]; 793 u8 counter_eswitch_affinity[0x1]; 794 u8 merged_eswitch[0x1]; 795 u8 nic_vport_node_guid_modify[0x1]; 796 u8 nic_vport_port_guid_modify[0x1]; 797 798 u8 vxlan_encap_decap[0x1]; 799 u8 nvgre_encap_decap[0x1]; 800 u8 reserved_at_22[0x1]; 801 u8 log_max_fdb_encap_uplink[0x5]; 802 u8 reserved_at_21[0x3]; 803 u8 log_max_packet_reformat_context[0x5]; 804 u8 reserved_2b[0x6]; 805 u8 max_encap_header_size[0xa]; 806 807 u8 reserved_at_40[0xb]; 808 u8 log_max_esw_sf[0x5]; 809 u8 esw_sf_base_id[0x10]; 810 811 u8 reserved_at_60[0x7a0]; 812 813 }; 814 815 struct mlx5_ifc_qos_cap_bits { 816 u8 packet_pacing[0x1]; 817 u8 esw_scheduling[0x1]; 818 u8 esw_bw_share[0x1]; 819 u8 esw_rate_limit[0x1]; 820 u8 reserved_at_4[0x1]; 821 u8 packet_pacing_burst_bound[0x1]; 822 u8 packet_pacing_typical_size[0x1]; 823 u8 reserved_at_7[0x4]; 824 u8 packet_pacing_uid[0x1]; 825 u8 reserved_at_c[0x14]; 826 827 u8 reserved_at_20[0x20]; 828 829 u8 packet_pacing_max_rate[0x20]; 830 831 u8 packet_pacing_min_rate[0x20]; 832 833 u8 reserved_at_80[0x10]; 834 u8 packet_pacing_rate_table_size[0x10]; 835 836 u8 esw_element_type[0x10]; 837 u8 esw_tsar_type[0x10]; 838 839 u8 reserved_at_c0[0x10]; 840 u8 max_qos_para_vport[0x10]; 841 842 u8 max_tsar_bw_share[0x20]; 843 844 u8 reserved_at_100[0x700]; 845 }; 846 847 struct mlx5_ifc_debug_cap_bits { 848 u8 core_dump_general[0x1]; 849 u8 core_dump_qp[0x1]; 850 u8 reserved_at_2[0x7]; 851 u8 resource_dump[0x1]; 852 u8 reserved_at_a[0x16]; 853 854 u8 reserved_at_20[0x2]; 855 u8 stall_detect[0x1]; 856 u8 reserved_at_23[0x1d]; 857 858 u8 reserved_at_40[0x7c0]; 859 }; 860 861 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 862 u8 csum_cap[0x1]; 863 u8 vlan_cap[0x1]; 864 u8 lro_cap[0x1]; 865 u8 lro_psh_flag[0x1]; 866 u8 lro_time_stamp[0x1]; 867 u8 reserved_at_5[0x2]; 868 u8 wqe_vlan_insert[0x1]; 869 u8 self_lb_en_modifiable[0x1]; 870 u8 reserved_at_9[0x2]; 871 u8 max_lso_cap[0x5]; 872 u8 multi_pkt_send_wqe[0x2]; 873 u8 wqe_inline_mode[0x2]; 874 u8 rss_ind_tbl_cap[0x4]; 875 u8 reg_umr_sq[0x1]; 876 u8 scatter_fcs[0x1]; 877 u8 enhanced_multi_pkt_send_wqe[0x1]; 878 u8 tunnel_lso_const_out_ip_id[0x1]; 879 u8 tunnel_lro_gre[0x1]; 880 u8 tunnel_lro_vxlan[0x1]; 881 u8 tunnel_stateless_gre[0x1]; 882 u8 tunnel_stateless_vxlan[0x1]; 883 884 u8 swp[0x1]; 885 u8 swp_csum[0x1]; 886 u8 swp_lso[0x1]; 887 u8 cqe_checksum_full[0x1]; 888 u8 tunnel_stateless_geneve_tx[0x1]; 889 u8 tunnel_stateless_mpls_over_udp[0x1]; 890 u8 tunnel_stateless_mpls_over_gre[0x1]; 891 u8 tunnel_stateless_vxlan_gpe[0x1]; 892 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 893 u8 tunnel_stateless_ip_over_ip[0x1]; 894 u8 insert_trailer[0x1]; 895 u8 reserved_at_2b[0x5]; 896 u8 max_vxlan_udp_ports[0x8]; 897 u8 reserved_at_38[0x6]; 898 u8 max_geneve_opt_len[0x1]; 899 u8 tunnel_stateless_geneve_rx[0x1]; 900 901 u8 reserved_at_40[0x10]; 902 u8 lro_min_mss_size[0x10]; 903 904 u8 reserved_at_60[0x120]; 905 906 u8 lro_timer_supported_periods[4][0x20]; 907 908 u8 reserved_at_200[0x600]; 909 }; 910 911 struct mlx5_ifc_roce_cap_bits { 912 u8 roce_apm[0x1]; 913 u8 reserved_at_1[0x3]; 914 u8 sw_r_roce_src_udp_port[0x1]; 915 u8 reserved_at_5[0x1b]; 916 917 u8 reserved_at_20[0x60]; 918 919 u8 reserved_at_80[0xc]; 920 u8 l3_type[0x4]; 921 u8 reserved_at_90[0x8]; 922 u8 roce_version[0x8]; 923 924 u8 reserved_at_a0[0x10]; 925 u8 r_roce_dest_udp_port[0x10]; 926 927 u8 r_roce_max_src_udp_port[0x10]; 928 u8 r_roce_min_src_udp_port[0x10]; 929 930 u8 reserved_at_e0[0x10]; 931 u8 roce_address_table_size[0x10]; 932 933 u8 reserved_at_100[0x700]; 934 }; 935 936 struct mlx5_ifc_sync_steering_in_bits { 937 u8 opcode[0x10]; 938 u8 uid[0x10]; 939 940 u8 reserved_at_20[0x10]; 941 u8 op_mod[0x10]; 942 943 u8 reserved_at_40[0xc0]; 944 }; 945 946 struct mlx5_ifc_sync_steering_out_bits { 947 u8 status[0x8]; 948 u8 reserved_at_8[0x18]; 949 950 u8 syndrome[0x20]; 951 952 u8 reserved_at_40[0x40]; 953 }; 954 955 struct mlx5_ifc_device_mem_cap_bits { 956 u8 memic[0x1]; 957 u8 reserved_at_1[0x1f]; 958 959 u8 reserved_at_20[0xb]; 960 u8 log_min_memic_alloc_size[0x5]; 961 u8 reserved_at_30[0x8]; 962 u8 log_max_memic_addr_alignment[0x8]; 963 964 u8 memic_bar_start_addr[0x40]; 965 966 u8 memic_bar_size[0x20]; 967 968 u8 max_memic_size[0x20]; 969 970 u8 steering_sw_icm_start_address[0x40]; 971 972 u8 reserved_at_100[0x8]; 973 u8 log_header_modify_sw_icm_size[0x8]; 974 u8 reserved_at_110[0x2]; 975 u8 log_sw_icm_alloc_granularity[0x6]; 976 u8 log_steering_sw_icm_size[0x8]; 977 978 u8 reserved_at_120[0x20]; 979 980 u8 header_modify_sw_icm_start_address[0x40]; 981 982 u8 reserved_at_180[0x680]; 983 }; 984 985 struct mlx5_ifc_device_event_cap_bits { 986 u8 user_affiliated_events[4][0x40]; 987 988 u8 user_unaffiliated_events[4][0x40]; 989 }; 990 991 struct mlx5_ifc_virtio_emulation_cap_bits { 992 u8 desc_tunnel_offload_type[0x1]; 993 u8 eth_frame_offload_type[0x1]; 994 u8 virtio_version_1_0[0x1]; 995 u8 device_features_bits_mask[0xd]; 996 u8 event_mode[0x8]; 997 u8 virtio_queue_type[0x8]; 998 999 u8 max_tunnel_desc[0x10]; 1000 u8 reserved_at_30[0x3]; 1001 u8 log_doorbell_stride[0x5]; 1002 u8 reserved_at_38[0x3]; 1003 u8 log_doorbell_bar_size[0x5]; 1004 1005 u8 doorbell_bar_offset[0x40]; 1006 1007 u8 max_emulated_devices[0x8]; 1008 u8 max_num_virtio_queues[0x18]; 1009 1010 u8 reserved_at_a0[0x60]; 1011 1012 u8 umem_1_buffer_param_a[0x20]; 1013 1014 u8 umem_1_buffer_param_b[0x20]; 1015 1016 u8 umem_2_buffer_param_a[0x20]; 1017 1018 u8 umem_2_buffer_param_b[0x20]; 1019 1020 u8 umem_3_buffer_param_a[0x20]; 1021 1022 u8 umem_3_buffer_param_b[0x20]; 1023 1024 u8 reserved_at_1c0[0x640]; 1025 }; 1026 1027 enum { 1028 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1029 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1030 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1031 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1032 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1033 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1034 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1035 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1036 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1037 }; 1038 1039 enum { 1040 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1047 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1048 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1049 }; 1050 1051 struct mlx5_ifc_atomic_caps_bits { 1052 u8 reserved_at_0[0x40]; 1053 1054 u8 atomic_req_8B_endianness_mode[0x2]; 1055 u8 reserved_at_42[0x4]; 1056 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1057 1058 u8 reserved_at_47[0x19]; 1059 1060 u8 reserved_at_60[0x20]; 1061 1062 u8 reserved_at_80[0x10]; 1063 u8 atomic_operations[0x10]; 1064 1065 u8 reserved_at_a0[0x10]; 1066 u8 atomic_size_qp[0x10]; 1067 1068 u8 reserved_at_c0[0x10]; 1069 u8 atomic_size_dc[0x10]; 1070 1071 u8 reserved_at_e0[0x720]; 1072 }; 1073 1074 struct mlx5_ifc_odp_cap_bits { 1075 u8 reserved_at_0[0x40]; 1076 1077 u8 sig[0x1]; 1078 u8 reserved_at_41[0x1f]; 1079 1080 u8 reserved_at_60[0x20]; 1081 1082 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1083 1084 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1085 1086 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1087 1088 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1089 1090 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1091 1092 u8 reserved_at_120[0x6E0]; 1093 }; 1094 1095 struct mlx5_ifc_calc_op { 1096 u8 reserved_at_0[0x10]; 1097 u8 reserved_at_10[0x9]; 1098 u8 op_swap_endianness[0x1]; 1099 u8 op_min[0x1]; 1100 u8 op_xor[0x1]; 1101 u8 op_or[0x1]; 1102 u8 op_and[0x1]; 1103 u8 op_max[0x1]; 1104 u8 op_add[0x1]; 1105 }; 1106 1107 struct mlx5_ifc_vector_calc_cap_bits { 1108 u8 calc_matrix[0x1]; 1109 u8 reserved_at_1[0x1f]; 1110 u8 reserved_at_20[0x8]; 1111 u8 max_vec_count[0x8]; 1112 u8 reserved_at_30[0xd]; 1113 u8 max_chunk_size[0x3]; 1114 struct mlx5_ifc_calc_op calc0; 1115 struct mlx5_ifc_calc_op calc1; 1116 struct mlx5_ifc_calc_op calc2; 1117 struct mlx5_ifc_calc_op calc3; 1118 1119 u8 reserved_at_c0[0x720]; 1120 }; 1121 1122 struct mlx5_ifc_tls_cap_bits { 1123 u8 tls_1_2_aes_gcm_128[0x1]; 1124 u8 tls_1_3_aes_gcm_128[0x1]; 1125 u8 tls_1_2_aes_gcm_256[0x1]; 1126 u8 tls_1_3_aes_gcm_256[0x1]; 1127 u8 reserved_at_4[0x1c]; 1128 1129 u8 reserved_at_20[0x7e0]; 1130 }; 1131 1132 struct mlx5_ifc_ipsec_cap_bits { 1133 u8 ipsec_full_offload[0x1]; 1134 u8 ipsec_crypto_offload[0x1]; 1135 u8 ipsec_esn[0x1]; 1136 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1137 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1138 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1139 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1140 u8 reserved_at_7[0x4]; 1141 u8 log_max_ipsec_offload[0x5]; 1142 u8 reserved_at_10[0x10]; 1143 1144 u8 min_log_ipsec_full_replay_window[0x8]; 1145 u8 max_log_ipsec_full_replay_window[0x8]; 1146 u8 reserved_at_30[0x7d0]; 1147 }; 1148 1149 enum { 1150 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1151 MLX5_WQ_TYPE_CYCLIC = 0x1, 1152 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1153 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1154 }; 1155 1156 enum { 1157 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1158 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1159 }; 1160 1161 enum { 1162 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1163 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1164 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1165 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1166 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1167 }; 1168 1169 enum { 1170 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1171 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1172 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1173 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1174 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1175 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1176 }; 1177 1178 enum { 1179 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1180 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1181 }; 1182 1183 enum { 1184 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1185 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1186 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1187 }; 1188 1189 enum { 1190 MLX5_CAP_PORT_TYPE_IB = 0x0, 1191 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1192 }; 1193 1194 enum { 1195 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1196 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1197 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1198 }; 1199 1200 enum { 1201 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1202 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1203 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1204 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1205 }; 1206 1207 enum { 1208 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1209 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1210 }; 1211 1212 #define MLX5_FC_BULK_SIZE_FACTOR 128 1213 1214 enum mlx5_fc_bulk_alloc_bitmask { 1215 MLX5_FC_BULK_128 = (1 << 0), 1216 MLX5_FC_BULK_256 = (1 << 1), 1217 MLX5_FC_BULK_512 = (1 << 2), 1218 MLX5_FC_BULK_1024 = (1 << 3), 1219 MLX5_FC_BULK_2048 = (1 << 4), 1220 MLX5_FC_BULK_4096 = (1 << 5), 1221 MLX5_FC_BULK_8192 = (1 << 6), 1222 MLX5_FC_BULK_16384 = (1 << 7), 1223 }; 1224 1225 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1226 1227 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1228 1229 enum { 1230 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1231 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1232 }; 1233 1234 struct mlx5_ifc_cmd_hca_cap_bits { 1235 u8 reserved_at_0[0x30]; 1236 u8 vhca_id[0x10]; 1237 1238 u8 reserved_at_40[0x40]; 1239 1240 u8 log_max_srq_sz[0x8]; 1241 u8 log_max_qp_sz[0x8]; 1242 u8 event_cap[0x1]; 1243 u8 reserved_at_91[0x7]; 1244 u8 prio_tag_required[0x1]; 1245 u8 reserved_at_99[0x2]; 1246 u8 log_max_qp[0x5]; 1247 1248 u8 reserved_at_a0[0x3]; 1249 u8 ece_support[0x1]; 1250 u8 reserved_at_a4[0x7]; 1251 u8 log_max_srq[0x5]; 1252 u8 reserved_at_b0[0x10]; 1253 1254 u8 max_sgl_for_optimized_performance[0x8]; 1255 u8 log_max_cq_sz[0x8]; 1256 u8 relaxed_ordering_write_umr[0x1]; 1257 u8 relaxed_ordering_read_umr[0x1]; 1258 u8 reserved_at_d2[0x7]; 1259 u8 virtio_net_device_emualtion_manager[0x1]; 1260 u8 virtio_blk_device_emualtion_manager[0x1]; 1261 u8 log_max_cq[0x5]; 1262 1263 u8 log_max_eq_sz[0x8]; 1264 u8 relaxed_ordering_write[0x1]; 1265 u8 relaxed_ordering_read[0x1]; 1266 u8 log_max_mkey[0x6]; 1267 u8 reserved_at_f0[0x8]; 1268 u8 dump_fill_mkey[0x1]; 1269 u8 reserved_at_f9[0x2]; 1270 u8 fast_teardown[0x1]; 1271 u8 log_max_eq[0x4]; 1272 1273 u8 max_indirection[0x8]; 1274 u8 fixed_buffer_size[0x1]; 1275 u8 log_max_mrw_sz[0x7]; 1276 u8 force_teardown[0x1]; 1277 u8 reserved_at_111[0x1]; 1278 u8 log_max_bsf_list_size[0x6]; 1279 u8 umr_extended_translation_offset[0x1]; 1280 u8 null_mkey[0x1]; 1281 u8 log_max_klm_list_size[0x6]; 1282 1283 u8 reserved_at_120[0xa]; 1284 u8 log_max_ra_req_dc[0x6]; 1285 u8 reserved_at_130[0xa]; 1286 u8 log_max_ra_res_dc[0x6]; 1287 1288 u8 reserved_at_140[0x6]; 1289 u8 release_all_pages[0x1]; 1290 u8 reserved_at_147[0x2]; 1291 u8 roce_accl[0x1]; 1292 u8 log_max_ra_req_qp[0x6]; 1293 u8 reserved_at_150[0xa]; 1294 u8 log_max_ra_res_qp[0x6]; 1295 1296 u8 end_pad[0x1]; 1297 u8 cc_query_allowed[0x1]; 1298 u8 cc_modify_allowed[0x1]; 1299 u8 start_pad[0x1]; 1300 u8 cache_line_128byte[0x1]; 1301 u8 reserved_at_165[0x4]; 1302 u8 rts2rts_qp_counters_set_id[0x1]; 1303 u8 reserved_at_16a[0x2]; 1304 u8 vnic_env_int_rq_oob[0x1]; 1305 u8 sbcam_reg[0x1]; 1306 u8 reserved_at_16e[0x1]; 1307 u8 qcam_reg[0x1]; 1308 u8 gid_table_size[0x10]; 1309 1310 u8 out_of_seq_cnt[0x1]; 1311 u8 vport_counters[0x1]; 1312 u8 retransmission_q_counters[0x1]; 1313 u8 debug[0x1]; 1314 u8 modify_rq_counter_set_id[0x1]; 1315 u8 rq_delay_drop[0x1]; 1316 u8 max_qp_cnt[0xa]; 1317 u8 pkey_table_size[0x10]; 1318 1319 u8 vport_group_manager[0x1]; 1320 u8 vhca_group_manager[0x1]; 1321 u8 ib_virt[0x1]; 1322 u8 eth_virt[0x1]; 1323 u8 vnic_env_queue_counters[0x1]; 1324 u8 ets[0x1]; 1325 u8 nic_flow_table[0x1]; 1326 u8 eswitch_manager[0x1]; 1327 u8 device_memory[0x1]; 1328 u8 mcam_reg[0x1]; 1329 u8 pcam_reg[0x1]; 1330 u8 local_ca_ack_delay[0x5]; 1331 u8 port_module_event[0x1]; 1332 u8 enhanced_error_q_counters[0x1]; 1333 u8 ports_check[0x1]; 1334 u8 reserved_at_1b3[0x1]; 1335 u8 disable_link_up[0x1]; 1336 u8 beacon_led[0x1]; 1337 u8 port_type[0x2]; 1338 u8 num_ports[0x8]; 1339 1340 u8 reserved_at_1c0[0x1]; 1341 u8 pps[0x1]; 1342 u8 pps_modify[0x1]; 1343 u8 log_max_msg[0x5]; 1344 u8 reserved_at_1c8[0x4]; 1345 u8 max_tc[0x4]; 1346 u8 temp_warn_event[0x1]; 1347 u8 dcbx[0x1]; 1348 u8 general_notification_event[0x1]; 1349 u8 reserved_at_1d3[0x2]; 1350 u8 fpga[0x1]; 1351 u8 rol_s[0x1]; 1352 u8 rol_g[0x1]; 1353 u8 reserved_at_1d8[0x1]; 1354 u8 wol_s[0x1]; 1355 u8 wol_g[0x1]; 1356 u8 wol_a[0x1]; 1357 u8 wol_b[0x1]; 1358 u8 wol_m[0x1]; 1359 u8 wol_u[0x1]; 1360 u8 wol_p[0x1]; 1361 1362 u8 stat_rate_support[0x10]; 1363 u8 reserved_at_1f0[0x1]; 1364 u8 pci_sync_for_fw_update_event[0x1]; 1365 u8 reserved_at_1f2[0x6]; 1366 u8 init2_lag_tx_port_affinity[0x1]; 1367 u8 reserved_at_1fa[0x3]; 1368 u8 cqe_version[0x4]; 1369 1370 u8 compact_address_vector[0x1]; 1371 u8 striding_rq[0x1]; 1372 u8 reserved_at_202[0x1]; 1373 u8 ipoib_enhanced_offloads[0x1]; 1374 u8 ipoib_basic_offloads[0x1]; 1375 u8 reserved_at_205[0x1]; 1376 u8 repeated_block_disabled[0x1]; 1377 u8 umr_modify_entity_size_disabled[0x1]; 1378 u8 umr_modify_atomic_disabled[0x1]; 1379 u8 umr_indirect_mkey_disabled[0x1]; 1380 u8 umr_fence[0x2]; 1381 u8 dc_req_scat_data_cqe[0x1]; 1382 u8 reserved_at_20d[0x2]; 1383 u8 drain_sigerr[0x1]; 1384 u8 cmdif_checksum[0x2]; 1385 u8 sigerr_cqe[0x1]; 1386 u8 reserved_at_213[0x1]; 1387 u8 wq_signature[0x1]; 1388 u8 sctr_data_cqe[0x1]; 1389 u8 reserved_at_216[0x1]; 1390 u8 sho[0x1]; 1391 u8 tph[0x1]; 1392 u8 rf[0x1]; 1393 u8 dct[0x1]; 1394 u8 qos[0x1]; 1395 u8 eth_net_offloads[0x1]; 1396 u8 roce[0x1]; 1397 u8 atomic[0x1]; 1398 u8 reserved_at_21f[0x1]; 1399 1400 u8 cq_oi[0x1]; 1401 u8 cq_resize[0x1]; 1402 u8 cq_moderation[0x1]; 1403 u8 reserved_at_223[0x3]; 1404 u8 cq_eq_remap[0x1]; 1405 u8 pg[0x1]; 1406 u8 block_lb_mc[0x1]; 1407 u8 reserved_at_229[0x1]; 1408 u8 scqe_break_moderation[0x1]; 1409 u8 cq_period_start_from_cqe[0x1]; 1410 u8 cd[0x1]; 1411 u8 reserved_at_22d[0x1]; 1412 u8 apm[0x1]; 1413 u8 vector_calc[0x1]; 1414 u8 umr_ptr_rlky[0x1]; 1415 u8 imaicl[0x1]; 1416 u8 qp_packet_based[0x1]; 1417 u8 reserved_at_233[0x3]; 1418 u8 qkv[0x1]; 1419 u8 pkv[0x1]; 1420 u8 set_deth_sqpn[0x1]; 1421 u8 reserved_at_239[0x3]; 1422 u8 xrc[0x1]; 1423 u8 ud[0x1]; 1424 u8 uc[0x1]; 1425 u8 rc[0x1]; 1426 1427 u8 uar_4k[0x1]; 1428 u8 reserved_at_241[0x9]; 1429 u8 uar_sz[0x6]; 1430 u8 reserved_at_250[0x8]; 1431 u8 log_pg_sz[0x8]; 1432 1433 u8 bf[0x1]; 1434 u8 driver_version[0x1]; 1435 u8 pad_tx_eth_packet[0x1]; 1436 u8 reserved_at_263[0x3]; 1437 u8 mkey_by_name[0x1]; 1438 u8 reserved_at_267[0x4]; 1439 1440 u8 log_bf_reg_size[0x5]; 1441 1442 u8 reserved_at_270[0x6]; 1443 u8 lag_dct[0x2]; 1444 u8 lag_tx_port_affinity[0x1]; 1445 u8 reserved_at_279[0x2]; 1446 u8 lag_master[0x1]; 1447 u8 num_lag_ports[0x4]; 1448 1449 u8 reserved_at_280[0x10]; 1450 u8 max_wqe_sz_sq[0x10]; 1451 1452 u8 reserved_at_2a0[0x10]; 1453 u8 max_wqe_sz_rq[0x10]; 1454 1455 u8 max_flow_counter_31_16[0x10]; 1456 u8 max_wqe_sz_sq_dc[0x10]; 1457 1458 u8 reserved_at_2e0[0x7]; 1459 u8 max_qp_mcg[0x19]; 1460 1461 u8 reserved_at_300[0x10]; 1462 u8 flow_counter_bulk_alloc[0x8]; 1463 u8 log_max_mcg[0x8]; 1464 1465 u8 reserved_at_320[0x3]; 1466 u8 log_max_transport_domain[0x5]; 1467 u8 reserved_at_328[0x3]; 1468 u8 log_max_pd[0x5]; 1469 u8 reserved_at_330[0xb]; 1470 u8 log_max_xrcd[0x5]; 1471 1472 u8 nic_receive_steering_discard[0x1]; 1473 u8 receive_discard_vport_down[0x1]; 1474 u8 transmit_discard_vport_down[0x1]; 1475 u8 reserved_at_343[0x5]; 1476 u8 log_max_flow_counter_bulk[0x8]; 1477 u8 max_flow_counter_15_0[0x10]; 1478 1479 1480 u8 reserved_at_360[0x3]; 1481 u8 log_max_rq[0x5]; 1482 u8 reserved_at_368[0x3]; 1483 u8 log_max_sq[0x5]; 1484 u8 reserved_at_370[0x3]; 1485 u8 log_max_tir[0x5]; 1486 u8 reserved_at_378[0x3]; 1487 u8 log_max_tis[0x5]; 1488 1489 u8 basic_cyclic_rcv_wqe[0x1]; 1490 u8 reserved_at_381[0x2]; 1491 u8 log_max_rmp[0x5]; 1492 u8 reserved_at_388[0x3]; 1493 u8 log_max_rqt[0x5]; 1494 u8 reserved_at_390[0x3]; 1495 u8 log_max_rqt_size[0x5]; 1496 u8 reserved_at_398[0x3]; 1497 u8 log_max_tis_per_sq[0x5]; 1498 1499 u8 ext_stride_num_range[0x1]; 1500 u8 reserved_at_3a1[0x2]; 1501 u8 log_max_stride_sz_rq[0x5]; 1502 u8 reserved_at_3a8[0x3]; 1503 u8 log_min_stride_sz_rq[0x5]; 1504 u8 reserved_at_3b0[0x3]; 1505 u8 log_max_stride_sz_sq[0x5]; 1506 u8 reserved_at_3b8[0x3]; 1507 u8 log_min_stride_sz_sq[0x5]; 1508 1509 u8 hairpin[0x1]; 1510 u8 reserved_at_3c1[0x2]; 1511 u8 log_max_hairpin_queues[0x5]; 1512 u8 reserved_at_3c8[0x3]; 1513 u8 log_max_hairpin_wq_data_sz[0x5]; 1514 u8 reserved_at_3d0[0x3]; 1515 u8 log_max_hairpin_num_packets[0x5]; 1516 u8 reserved_at_3d8[0x3]; 1517 u8 log_max_wq_sz[0x5]; 1518 1519 u8 nic_vport_change_event[0x1]; 1520 u8 disable_local_lb_uc[0x1]; 1521 u8 disable_local_lb_mc[0x1]; 1522 u8 log_min_hairpin_wq_data_sz[0x5]; 1523 u8 reserved_at_3e8[0x3]; 1524 u8 log_max_vlan_list[0x5]; 1525 u8 reserved_at_3f0[0x3]; 1526 u8 log_max_current_mc_list[0x5]; 1527 u8 reserved_at_3f8[0x3]; 1528 u8 log_max_current_uc_list[0x5]; 1529 1530 u8 general_obj_types[0x40]; 1531 1532 u8 reserved_at_440[0x4]; 1533 u8 steering_format_version[0x4]; 1534 u8 create_qp_start_hint[0x18]; 1535 1536 u8 reserved_at_460[0x3]; 1537 u8 log_max_uctx[0x5]; 1538 u8 reserved_at_468[0x2]; 1539 u8 ipsec_offload[0x1]; 1540 u8 log_max_umem[0x5]; 1541 u8 max_num_eqs[0x10]; 1542 1543 u8 reserved_at_480[0x1]; 1544 u8 tls_tx[0x1]; 1545 u8 tls_rx[0x1]; 1546 u8 log_max_l2_table[0x5]; 1547 u8 reserved_at_488[0x8]; 1548 u8 log_uar_page_sz[0x10]; 1549 1550 u8 reserved_at_4a0[0x20]; 1551 u8 device_frequency_mhz[0x20]; 1552 u8 device_frequency_khz[0x20]; 1553 1554 u8 reserved_at_500[0x20]; 1555 u8 num_of_uars_per_page[0x20]; 1556 1557 u8 flex_parser_protocols[0x20]; 1558 1559 u8 max_geneve_tlv_options[0x8]; 1560 u8 reserved_at_568[0x3]; 1561 u8 max_geneve_tlv_option_data_len[0x5]; 1562 u8 reserved_at_570[0x10]; 1563 1564 u8 reserved_at_580[0x33]; 1565 u8 log_max_dek[0x5]; 1566 u8 reserved_at_5b8[0x4]; 1567 u8 mini_cqe_resp_stride_index[0x1]; 1568 u8 cqe_128_always[0x1]; 1569 u8 cqe_compression_128[0x1]; 1570 u8 cqe_compression[0x1]; 1571 1572 u8 cqe_compression_timeout[0x10]; 1573 u8 cqe_compression_max_num[0x10]; 1574 1575 u8 reserved_at_5e0[0x10]; 1576 u8 tag_matching[0x1]; 1577 u8 rndv_offload_rc[0x1]; 1578 u8 rndv_offload_dc[0x1]; 1579 u8 log_tag_matching_list_sz[0x5]; 1580 u8 reserved_at_5f8[0x3]; 1581 u8 log_max_xrq[0x5]; 1582 1583 u8 affiliate_nic_vport_criteria[0x8]; 1584 u8 native_port_num[0x8]; 1585 u8 num_vhca_ports[0x8]; 1586 u8 reserved_at_618[0x6]; 1587 u8 sw_owner_id[0x1]; 1588 u8 reserved_at_61f[0x1]; 1589 1590 u8 max_num_of_monitor_counters[0x10]; 1591 u8 num_ppcnt_monitor_counters[0x10]; 1592 1593 u8 reserved_at_640[0x10]; 1594 u8 num_q_monitor_counters[0x10]; 1595 1596 u8 reserved_at_660[0x20]; 1597 1598 u8 sf[0x1]; 1599 u8 sf_set_partition[0x1]; 1600 u8 reserved_at_682[0x1]; 1601 u8 log_max_sf[0x5]; 1602 u8 reserved_at_688[0x8]; 1603 u8 log_min_sf_size[0x8]; 1604 u8 max_num_sf_partitions[0x8]; 1605 1606 u8 uctx_cap[0x20]; 1607 1608 u8 reserved_at_6c0[0x4]; 1609 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1610 u8 flex_parser_id_icmp_dw1[0x4]; 1611 u8 flex_parser_id_icmp_dw0[0x4]; 1612 u8 flex_parser_id_icmpv6_dw1[0x4]; 1613 u8 flex_parser_id_icmpv6_dw0[0x4]; 1614 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1615 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1616 1617 u8 reserved_at_6e0[0x10]; 1618 u8 sf_base_id[0x10]; 1619 1620 u8 reserved_at_700[0x80]; 1621 u8 vhca_tunnel_commands[0x40]; 1622 u8 reserved_at_7c0[0x40]; 1623 }; 1624 1625 enum mlx5_flow_destination_type { 1626 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1627 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1628 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1629 1630 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1631 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1632 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1633 }; 1634 1635 enum mlx5_flow_table_miss_action { 1636 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1637 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1638 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1639 }; 1640 1641 struct mlx5_ifc_dest_format_struct_bits { 1642 u8 destination_type[0x8]; 1643 u8 destination_id[0x18]; 1644 1645 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1646 u8 packet_reformat[0x1]; 1647 u8 reserved_at_22[0xe]; 1648 u8 destination_eswitch_owner_vhca_id[0x10]; 1649 }; 1650 1651 struct mlx5_ifc_flow_counter_list_bits { 1652 u8 flow_counter_id[0x20]; 1653 1654 u8 reserved_at_20[0x20]; 1655 }; 1656 1657 struct mlx5_ifc_extended_dest_format_bits { 1658 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1659 1660 u8 packet_reformat_id[0x20]; 1661 1662 u8 reserved_at_60[0x20]; 1663 }; 1664 1665 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1666 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1667 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1668 }; 1669 1670 struct mlx5_ifc_fte_match_param_bits { 1671 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1672 1673 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1674 1675 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1676 1677 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1678 1679 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1680 1681 u8 reserved_at_a00[0x600]; 1682 }; 1683 1684 enum { 1685 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1686 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1687 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1688 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1689 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1690 }; 1691 1692 struct mlx5_ifc_rx_hash_field_select_bits { 1693 u8 l3_prot_type[0x1]; 1694 u8 l4_prot_type[0x1]; 1695 u8 selected_fields[0x1e]; 1696 }; 1697 1698 enum { 1699 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1700 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1701 }; 1702 1703 enum { 1704 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1705 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1706 }; 1707 1708 struct mlx5_ifc_wq_bits { 1709 u8 wq_type[0x4]; 1710 u8 wq_signature[0x1]; 1711 u8 end_padding_mode[0x2]; 1712 u8 cd_slave[0x1]; 1713 u8 reserved_at_8[0x18]; 1714 1715 u8 hds_skip_first_sge[0x1]; 1716 u8 log2_hds_buf_size[0x3]; 1717 u8 reserved_at_24[0x7]; 1718 u8 page_offset[0x5]; 1719 u8 lwm[0x10]; 1720 1721 u8 reserved_at_40[0x8]; 1722 u8 pd[0x18]; 1723 1724 u8 reserved_at_60[0x8]; 1725 u8 uar_page[0x18]; 1726 1727 u8 dbr_addr[0x40]; 1728 1729 u8 hw_counter[0x20]; 1730 1731 u8 sw_counter[0x20]; 1732 1733 u8 reserved_at_100[0xc]; 1734 u8 log_wq_stride[0x4]; 1735 u8 reserved_at_110[0x3]; 1736 u8 log_wq_pg_sz[0x5]; 1737 u8 reserved_at_118[0x3]; 1738 u8 log_wq_sz[0x5]; 1739 1740 u8 dbr_umem_valid[0x1]; 1741 u8 wq_umem_valid[0x1]; 1742 u8 reserved_at_122[0x1]; 1743 u8 log_hairpin_num_packets[0x5]; 1744 u8 reserved_at_128[0x3]; 1745 u8 log_hairpin_data_sz[0x5]; 1746 1747 u8 reserved_at_130[0x4]; 1748 u8 log_wqe_num_of_strides[0x4]; 1749 u8 two_byte_shift_en[0x1]; 1750 u8 reserved_at_139[0x4]; 1751 u8 log_wqe_stride_size[0x3]; 1752 1753 u8 reserved_at_140[0x4c0]; 1754 1755 struct mlx5_ifc_cmd_pas_bits pas[]; 1756 }; 1757 1758 struct mlx5_ifc_rq_num_bits { 1759 u8 reserved_at_0[0x8]; 1760 u8 rq_num[0x18]; 1761 }; 1762 1763 struct mlx5_ifc_mac_address_layout_bits { 1764 u8 reserved_at_0[0x10]; 1765 u8 mac_addr_47_32[0x10]; 1766 1767 u8 mac_addr_31_0[0x20]; 1768 }; 1769 1770 struct mlx5_ifc_vlan_layout_bits { 1771 u8 reserved_at_0[0x14]; 1772 u8 vlan[0x0c]; 1773 1774 u8 reserved_at_20[0x20]; 1775 }; 1776 1777 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1778 u8 reserved_at_0[0xa0]; 1779 1780 u8 min_time_between_cnps[0x20]; 1781 1782 u8 reserved_at_c0[0x12]; 1783 u8 cnp_dscp[0x6]; 1784 u8 reserved_at_d8[0x4]; 1785 u8 cnp_prio_mode[0x1]; 1786 u8 cnp_802p_prio[0x3]; 1787 1788 u8 reserved_at_e0[0x720]; 1789 }; 1790 1791 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1792 u8 reserved_at_0[0x60]; 1793 1794 u8 reserved_at_60[0x4]; 1795 u8 clamp_tgt_rate[0x1]; 1796 u8 reserved_at_65[0x3]; 1797 u8 clamp_tgt_rate_after_time_inc[0x1]; 1798 u8 reserved_at_69[0x17]; 1799 1800 u8 reserved_at_80[0x20]; 1801 1802 u8 rpg_time_reset[0x20]; 1803 1804 u8 rpg_byte_reset[0x20]; 1805 1806 u8 rpg_threshold[0x20]; 1807 1808 u8 rpg_max_rate[0x20]; 1809 1810 u8 rpg_ai_rate[0x20]; 1811 1812 u8 rpg_hai_rate[0x20]; 1813 1814 u8 rpg_gd[0x20]; 1815 1816 u8 rpg_min_dec_fac[0x20]; 1817 1818 u8 rpg_min_rate[0x20]; 1819 1820 u8 reserved_at_1c0[0xe0]; 1821 1822 u8 rate_to_set_on_first_cnp[0x20]; 1823 1824 u8 dce_tcp_g[0x20]; 1825 1826 u8 dce_tcp_rtt[0x20]; 1827 1828 u8 rate_reduce_monitor_period[0x20]; 1829 1830 u8 reserved_at_320[0x20]; 1831 1832 u8 initial_alpha_value[0x20]; 1833 1834 u8 reserved_at_360[0x4a0]; 1835 }; 1836 1837 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1838 u8 reserved_at_0[0x80]; 1839 1840 u8 rppp_max_rps[0x20]; 1841 1842 u8 rpg_time_reset[0x20]; 1843 1844 u8 rpg_byte_reset[0x20]; 1845 1846 u8 rpg_threshold[0x20]; 1847 1848 u8 rpg_max_rate[0x20]; 1849 1850 u8 rpg_ai_rate[0x20]; 1851 1852 u8 rpg_hai_rate[0x20]; 1853 1854 u8 rpg_gd[0x20]; 1855 1856 u8 rpg_min_dec_fac[0x20]; 1857 1858 u8 rpg_min_rate[0x20]; 1859 1860 u8 reserved_at_1c0[0x640]; 1861 }; 1862 1863 enum { 1864 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1865 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1866 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1867 }; 1868 1869 struct mlx5_ifc_resize_field_select_bits { 1870 u8 resize_field_select[0x20]; 1871 }; 1872 1873 struct mlx5_ifc_resource_dump_bits { 1874 u8 more_dump[0x1]; 1875 u8 inline_dump[0x1]; 1876 u8 reserved_at_2[0xa]; 1877 u8 seq_num[0x4]; 1878 u8 segment_type[0x10]; 1879 1880 u8 reserved_at_20[0x10]; 1881 u8 vhca_id[0x10]; 1882 1883 u8 index1[0x20]; 1884 1885 u8 index2[0x20]; 1886 1887 u8 num_of_obj1[0x10]; 1888 u8 num_of_obj2[0x10]; 1889 1890 u8 reserved_at_a0[0x20]; 1891 1892 u8 device_opaque[0x40]; 1893 1894 u8 mkey[0x20]; 1895 1896 u8 size[0x20]; 1897 1898 u8 address[0x40]; 1899 1900 u8 inline_data[52][0x20]; 1901 }; 1902 1903 struct mlx5_ifc_resource_dump_menu_record_bits { 1904 u8 reserved_at_0[0x4]; 1905 u8 num_of_obj2_supports_active[0x1]; 1906 u8 num_of_obj2_supports_all[0x1]; 1907 u8 must_have_num_of_obj2[0x1]; 1908 u8 support_num_of_obj2[0x1]; 1909 u8 num_of_obj1_supports_active[0x1]; 1910 u8 num_of_obj1_supports_all[0x1]; 1911 u8 must_have_num_of_obj1[0x1]; 1912 u8 support_num_of_obj1[0x1]; 1913 u8 must_have_index2[0x1]; 1914 u8 support_index2[0x1]; 1915 u8 must_have_index1[0x1]; 1916 u8 support_index1[0x1]; 1917 u8 segment_type[0x10]; 1918 1919 u8 segment_name[4][0x20]; 1920 1921 u8 index1_name[4][0x20]; 1922 1923 u8 index2_name[4][0x20]; 1924 }; 1925 1926 struct mlx5_ifc_resource_dump_segment_header_bits { 1927 u8 length_dw[0x10]; 1928 u8 segment_type[0x10]; 1929 }; 1930 1931 struct mlx5_ifc_resource_dump_command_segment_bits { 1932 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1933 1934 u8 segment_called[0x10]; 1935 u8 vhca_id[0x10]; 1936 1937 u8 index1[0x20]; 1938 1939 u8 index2[0x20]; 1940 1941 u8 num_of_obj1[0x10]; 1942 u8 num_of_obj2[0x10]; 1943 }; 1944 1945 struct mlx5_ifc_resource_dump_error_segment_bits { 1946 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1947 1948 u8 reserved_at_20[0x10]; 1949 u8 syndrome_id[0x10]; 1950 1951 u8 reserved_at_40[0x40]; 1952 1953 u8 error[8][0x20]; 1954 }; 1955 1956 struct mlx5_ifc_resource_dump_info_segment_bits { 1957 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1958 1959 u8 reserved_at_20[0x18]; 1960 u8 dump_version[0x8]; 1961 1962 u8 hw_version[0x20]; 1963 1964 u8 fw_version[0x20]; 1965 }; 1966 1967 struct mlx5_ifc_resource_dump_menu_segment_bits { 1968 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1969 1970 u8 reserved_at_20[0x10]; 1971 u8 num_of_records[0x10]; 1972 1973 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 1974 }; 1975 1976 struct mlx5_ifc_resource_dump_resource_segment_bits { 1977 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1978 1979 u8 reserved_at_20[0x20]; 1980 1981 u8 index1[0x20]; 1982 1983 u8 index2[0x20]; 1984 1985 u8 payload[][0x20]; 1986 }; 1987 1988 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1989 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1990 }; 1991 1992 struct mlx5_ifc_menu_resource_dump_response_bits { 1993 struct mlx5_ifc_resource_dump_info_segment_bits info; 1994 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1995 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1996 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1997 }; 1998 1999 enum { 2000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2001 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2003 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2004 }; 2005 2006 struct mlx5_ifc_modify_field_select_bits { 2007 u8 modify_field_select[0x20]; 2008 }; 2009 2010 struct mlx5_ifc_field_select_r_roce_np_bits { 2011 u8 field_select_r_roce_np[0x20]; 2012 }; 2013 2014 struct mlx5_ifc_field_select_r_roce_rp_bits { 2015 u8 field_select_r_roce_rp[0x20]; 2016 }; 2017 2018 enum { 2019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2028 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2029 }; 2030 2031 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2032 u8 field_select_8021qaurp[0x20]; 2033 }; 2034 2035 struct mlx5_ifc_phys_layer_cntrs_bits { 2036 u8 time_since_last_clear_high[0x20]; 2037 2038 u8 time_since_last_clear_low[0x20]; 2039 2040 u8 symbol_errors_high[0x20]; 2041 2042 u8 symbol_errors_low[0x20]; 2043 2044 u8 sync_headers_errors_high[0x20]; 2045 2046 u8 sync_headers_errors_low[0x20]; 2047 2048 u8 edpl_bip_errors_lane0_high[0x20]; 2049 2050 u8 edpl_bip_errors_lane0_low[0x20]; 2051 2052 u8 edpl_bip_errors_lane1_high[0x20]; 2053 2054 u8 edpl_bip_errors_lane1_low[0x20]; 2055 2056 u8 edpl_bip_errors_lane2_high[0x20]; 2057 2058 u8 edpl_bip_errors_lane2_low[0x20]; 2059 2060 u8 edpl_bip_errors_lane3_high[0x20]; 2061 2062 u8 edpl_bip_errors_lane3_low[0x20]; 2063 2064 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2065 2066 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2067 2068 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2069 2070 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2071 2072 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2073 2074 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2075 2076 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2077 2078 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2079 2080 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2081 2082 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2083 2084 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2085 2086 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2087 2088 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2089 2090 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2091 2092 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2093 2094 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2095 2096 u8 rs_fec_corrected_blocks_high[0x20]; 2097 2098 u8 rs_fec_corrected_blocks_low[0x20]; 2099 2100 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2101 2102 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2103 2104 u8 rs_fec_no_errors_blocks_high[0x20]; 2105 2106 u8 rs_fec_no_errors_blocks_low[0x20]; 2107 2108 u8 rs_fec_single_error_blocks_high[0x20]; 2109 2110 u8 rs_fec_single_error_blocks_low[0x20]; 2111 2112 u8 rs_fec_corrected_symbols_total_high[0x20]; 2113 2114 u8 rs_fec_corrected_symbols_total_low[0x20]; 2115 2116 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2117 2118 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2119 2120 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2121 2122 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2123 2124 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2125 2126 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2127 2128 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2129 2130 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2131 2132 u8 link_down_events[0x20]; 2133 2134 u8 successful_recovery_events[0x20]; 2135 2136 u8 reserved_at_640[0x180]; 2137 }; 2138 2139 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2140 u8 time_since_last_clear_high[0x20]; 2141 2142 u8 time_since_last_clear_low[0x20]; 2143 2144 u8 phy_received_bits_high[0x20]; 2145 2146 u8 phy_received_bits_low[0x20]; 2147 2148 u8 phy_symbol_errors_high[0x20]; 2149 2150 u8 phy_symbol_errors_low[0x20]; 2151 2152 u8 phy_corrected_bits_high[0x20]; 2153 2154 u8 phy_corrected_bits_low[0x20]; 2155 2156 u8 phy_corrected_bits_lane0_high[0x20]; 2157 2158 u8 phy_corrected_bits_lane0_low[0x20]; 2159 2160 u8 phy_corrected_bits_lane1_high[0x20]; 2161 2162 u8 phy_corrected_bits_lane1_low[0x20]; 2163 2164 u8 phy_corrected_bits_lane2_high[0x20]; 2165 2166 u8 phy_corrected_bits_lane2_low[0x20]; 2167 2168 u8 phy_corrected_bits_lane3_high[0x20]; 2169 2170 u8 phy_corrected_bits_lane3_low[0x20]; 2171 2172 u8 reserved_at_200[0x5c0]; 2173 }; 2174 2175 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2176 u8 symbol_error_counter[0x10]; 2177 2178 u8 link_error_recovery_counter[0x8]; 2179 2180 u8 link_downed_counter[0x8]; 2181 2182 u8 port_rcv_errors[0x10]; 2183 2184 u8 port_rcv_remote_physical_errors[0x10]; 2185 2186 u8 port_rcv_switch_relay_errors[0x10]; 2187 2188 u8 port_xmit_discards[0x10]; 2189 2190 u8 port_xmit_constraint_errors[0x8]; 2191 2192 u8 port_rcv_constraint_errors[0x8]; 2193 2194 u8 reserved_at_70[0x8]; 2195 2196 u8 link_overrun_errors[0x8]; 2197 2198 u8 reserved_at_80[0x10]; 2199 2200 u8 vl_15_dropped[0x10]; 2201 2202 u8 reserved_at_a0[0x80]; 2203 2204 u8 port_xmit_wait[0x20]; 2205 }; 2206 2207 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2208 u8 transmit_queue_high[0x20]; 2209 2210 u8 transmit_queue_low[0x20]; 2211 2212 u8 no_buffer_discard_uc_high[0x20]; 2213 2214 u8 no_buffer_discard_uc_low[0x20]; 2215 2216 u8 reserved_at_80[0x740]; 2217 }; 2218 2219 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2220 u8 wred_discard_high[0x20]; 2221 2222 u8 wred_discard_low[0x20]; 2223 2224 u8 ecn_marked_tc_high[0x20]; 2225 2226 u8 ecn_marked_tc_low[0x20]; 2227 2228 u8 reserved_at_80[0x740]; 2229 }; 2230 2231 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2232 u8 rx_octets_high[0x20]; 2233 2234 u8 rx_octets_low[0x20]; 2235 2236 u8 reserved_at_40[0xc0]; 2237 2238 u8 rx_frames_high[0x20]; 2239 2240 u8 rx_frames_low[0x20]; 2241 2242 u8 tx_octets_high[0x20]; 2243 2244 u8 tx_octets_low[0x20]; 2245 2246 u8 reserved_at_180[0xc0]; 2247 2248 u8 tx_frames_high[0x20]; 2249 2250 u8 tx_frames_low[0x20]; 2251 2252 u8 rx_pause_high[0x20]; 2253 2254 u8 rx_pause_low[0x20]; 2255 2256 u8 rx_pause_duration_high[0x20]; 2257 2258 u8 rx_pause_duration_low[0x20]; 2259 2260 u8 tx_pause_high[0x20]; 2261 2262 u8 tx_pause_low[0x20]; 2263 2264 u8 tx_pause_duration_high[0x20]; 2265 2266 u8 tx_pause_duration_low[0x20]; 2267 2268 u8 rx_pause_transition_high[0x20]; 2269 2270 u8 rx_pause_transition_low[0x20]; 2271 2272 u8 rx_discards_high[0x20]; 2273 2274 u8 rx_discards_low[0x20]; 2275 2276 u8 device_stall_minor_watermark_cnt_high[0x20]; 2277 2278 u8 device_stall_minor_watermark_cnt_low[0x20]; 2279 2280 u8 device_stall_critical_watermark_cnt_high[0x20]; 2281 2282 u8 device_stall_critical_watermark_cnt_low[0x20]; 2283 2284 u8 reserved_at_480[0x340]; 2285 }; 2286 2287 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2288 u8 port_transmit_wait_high[0x20]; 2289 2290 u8 port_transmit_wait_low[0x20]; 2291 2292 u8 reserved_at_40[0x100]; 2293 2294 u8 rx_buffer_almost_full_high[0x20]; 2295 2296 u8 rx_buffer_almost_full_low[0x20]; 2297 2298 u8 rx_buffer_full_high[0x20]; 2299 2300 u8 rx_buffer_full_low[0x20]; 2301 2302 u8 rx_icrc_encapsulated_high[0x20]; 2303 2304 u8 rx_icrc_encapsulated_low[0x20]; 2305 2306 u8 reserved_at_200[0x5c0]; 2307 }; 2308 2309 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2310 u8 dot3stats_alignment_errors_high[0x20]; 2311 2312 u8 dot3stats_alignment_errors_low[0x20]; 2313 2314 u8 dot3stats_fcs_errors_high[0x20]; 2315 2316 u8 dot3stats_fcs_errors_low[0x20]; 2317 2318 u8 dot3stats_single_collision_frames_high[0x20]; 2319 2320 u8 dot3stats_single_collision_frames_low[0x20]; 2321 2322 u8 dot3stats_multiple_collision_frames_high[0x20]; 2323 2324 u8 dot3stats_multiple_collision_frames_low[0x20]; 2325 2326 u8 dot3stats_sqe_test_errors_high[0x20]; 2327 2328 u8 dot3stats_sqe_test_errors_low[0x20]; 2329 2330 u8 dot3stats_deferred_transmissions_high[0x20]; 2331 2332 u8 dot3stats_deferred_transmissions_low[0x20]; 2333 2334 u8 dot3stats_late_collisions_high[0x20]; 2335 2336 u8 dot3stats_late_collisions_low[0x20]; 2337 2338 u8 dot3stats_excessive_collisions_high[0x20]; 2339 2340 u8 dot3stats_excessive_collisions_low[0x20]; 2341 2342 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2343 2344 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2345 2346 u8 dot3stats_carrier_sense_errors_high[0x20]; 2347 2348 u8 dot3stats_carrier_sense_errors_low[0x20]; 2349 2350 u8 dot3stats_frame_too_longs_high[0x20]; 2351 2352 u8 dot3stats_frame_too_longs_low[0x20]; 2353 2354 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2355 2356 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2357 2358 u8 dot3stats_symbol_errors_high[0x20]; 2359 2360 u8 dot3stats_symbol_errors_low[0x20]; 2361 2362 u8 dot3control_in_unknown_opcodes_high[0x20]; 2363 2364 u8 dot3control_in_unknown_opcodes_low[0x20]; 2365 2366 u8 dot3in_pause_frames_high[0x20]; 2367 2368 u8 dot3in_pause_frames_low[0x20]; 2369 2370 u8 dot3out_pause_frames_high[0x20]; 2371 2372 u8 dot3out_pause_frames_low[0x20]; 2373 2374 u8 reserved_at_400[0x3c0]; 2375 }; 2376 2377 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2378 u8 ether_stats_drop_events_high[0x20]; 2379 2380 u8 ether_stats_drop_events_low[0x20]; 2381 2382 u8 ether_stats_octets_high[0x20]; 2383 2384 u8 ether_stats_octets_low[0x20]; 2385 2386 u8 ether_stats_pkts_high[0x20]; 2387 2388 u8 ether_stats_pkts_low[0x20]; 2389 2390 u8 ether_stats_broadcast_pkts_high[0x20]; 2391 2392 u8 ether_stats_broadcast_pkts_low[0x20]; 2393 2394 u8 ether_stats_multicast_pkts_high[0x20]; 2395 2396 u8 ether_stats_multicast_pkts_low[0x20]; 2397 2398 u8 ether_stats_crc_align_errors_high[0x20]; 2399 2400 u8 ether_stats_crc_align_errors_low[0x20]; 2401 2402 u8 ether_stats_undersize_pkts_high[0x20]; 2403 2404 u8 ether_stats_undersize_pkts_low[0x20]; 2405 2406 u8 ether_stats_oversize_pkts_high[0x20]; 2407 2408 u8 ether_stats_oversize_pkts_low[0x20]; 2409 2410 u8 ether_stats_fragments_high[0x20]; 2411 2412 u8 ether_stats_fragments_low[0x20]; 2413 2414 u8 ether_stats_jabbers_high[0x20]; 2415 2416 u8 ether_stats_jabbers_low[0x20]; 2417 2418 u8 ether_stats_collisions_high[0x20]; 2419 2420 u8 ether_stats_collisions_low[0x20]; 2421 2422 u8 ether_stats_pkts64octets_high[0x20]; 2423 2424 u8 ether_stats_pkts64octets_low[0x20]; 2425 2426 u8 ether_stats_pkts65to127octets_high[0x20]; 2427 2428 u8 ether_stats_pkts65to127octets_low[0x20]; 2429 2430 u8 ether_stats_pkts128to255octets_high[0x20]; 2431 2432 u8 ether_stats_pkts128to255octets_low[0x20]; 2433 2434 u8 ether_stats_pkts256to511octets_high[0x20]; 2435 2436 u8 ether_stats_pkts256to511octets_low[0x20]; 2437 2438 u8 ether_stats_pkts512to1023octets_high[0x20]; 2439 2440 u8 ether_stats_pkts512to1023octets_low[0x20]; 2441 2442 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2443 2444 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2445 2446 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2447 2448 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2449 2450 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2451 2452 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2453 2454 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2455 2456 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2457 2458 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2459 2460 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2461 2462 u8 reserved_at_540[0x280]; 2463 }; 2464 2465 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2466 u8 if_in_octets_high[0x20]; 2467 2468 u8 if_in_octets_low[0x20]; 2469 2470 u8 if_in_ucast_pkts_high[0x20]; 2471 2472 u8 if_in_ucast_pkts_low[0x20]; 2473 2474 u8 if_in_discards_high[0x20]; 2475 2476 u8 if_in_discards_low[0x20]; 2477 2478 u8 if_in_errors_high[0x20]; 2479 2480 u8 if_in_errors_low[0x20]; 2481 2482 u8 if_in_unknown_protos_high[0x20]; 2483 2484 u8 if_in_unknown_protos_low[0x20]; 2485 2486 u8 if_out_octets_high[0x20]; 2487 2488 u8 if_out_octets_low[0x20]; 2489 2490 u8 if_out_ucast_pkts_high[0x20]; 2491 2492 u8 if_out_ucast_pkts_low[0x20]; 2493 2494 u8 if_out_discards_high[0x20]; 2495 2496 u8 if_out_discards_low[0x20]; 2497 2498 u8 if_out_errors_high[0x20]; 2499 2500 u8 if_out_errors_low[0x20]; 2501 2502 u8 if_in_multicast_pkts_high[0x20]; 2503 2504 u8 if_in_multicast_pkts_low[0x20]; 2505 2506 u8 if_in_broadcast_pkts_high[0x20]; 2507 2508 u8 if_in_broadcast_pkts_low[0x20]; 2509 2510 u8 if_out_multicast_pkts_high[0x20]; 2511 2512 u8 if_out_multicast_pkts_low[0x20]; 2513 2514 u8 if_out_broadcast_pkts_high[0x20]; 2515 2516 u8 if_out_broadcast_pkts_low[0x20]; 2517 2518 u8 reserved_at_340[0x480]; 2519 }; 2520 2521 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2522 u8 a_frames_transmitted_ok_high[0x20]; 2523 2524 u8 a_frames_transmitted_ok_low[0x20]; 2525 2526 u8 a_frames_received_ok_high[0x20]; 2527 2528 u8 a_frames_received_ok_low[0x20]; 2529 2530 u8 a_frame_check_sequence_errors_high[0x20]; 2531 2532 u8 a_frame_check_sequence_errors_low[0x20]; 2533 2534 u8 a_alignment_errors_high[0x20]; 2535 2536 u8 a_alignment_errors_low[0x20]; 2537 2538 u8 a_octets_transmitted_ok_high[0x20]; 2539 2540 u8 a_octets_transmitted_ok_low[0x20]; 2541 2542 u8 a_octets_received_ok_high[0x20]; 2543 2544 u8 a_octets_received_ok_low[0x20]; 2545 2546 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2547 2548 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2549 2550 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2551 2552 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2553 2554 u8 a_multicast_frames_received_ok_high[0x20]; 2555 2556 u8 a_multicast_frames_received_ok_low[0x20]; 2557 2558 u8 a_broadcast_frames_received_ok_high[0x20]; 2559 2560 u8 a_broadcast_frames_received_ok_low[0x20]; 2561 2562 u8 a_in_range_length_errors_high[0x20]; 2563 2564 u8 a_in_range_length_errors_low[0x20]; 2565 2566 u8 a_out_of_range_length_field_high[0x20]; 2567 2568 u8 a_out_of_range_length_field_low[0x20]; 2569 2570 u8 a_frame_too_long_errors_high[0x20]; 2571 2572 u8 a_frame_too_long_errors_low[0x20]; 2573 2574 u8 a_symbol_error_during_carrier_high[0x20]; 2575 2576 u8 a_symbol_error_during_carrier_low[0x20]; 2577 2578 u8 a_mac_control_frames_transmitted_high[0x20]; 2579 2580 u8 a_mac_control_frames_transmitted_low[0x20]; 2581 2582 u8 a_mac_control_frames_received_high[0x20]; 2583 2584 u8 a_mac_control_frames_received_low[0x20]; 2585 2586 u8 a_unsupported_opcodes_received_high[0x20]; 2587 2588 u8 a_unsupported_opcodes_received_low[0x20]; 2589 2590 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2591 2592 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2593 2594 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2595 2596 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2597 2598 u8 reserved_at_4c0[0x300]; 2599 }; 2600 2601 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2602 u8 life_time_counter_high[0x20]; 2603 2604 u8 life_time_counter_low[0x20]; 2605 2606 u8 rx_errors[0x20]; 2607 2608 u8 tx_errors[0x20]; 2609 2610 u8 l0_to_recovery_eieos[0x20]; 2611 2612 u8 l0_to_recovery_ts[0x20]; 2613 2614 u8 l0_to_recovery_framing[0x20]; 2615 2616 u8 l0_to_recovery_retrain[0x20]; 2617 2618 u8 crc_error_dllp[0x20]; 2619 2620 u8 crc_error_tlp[0x20]; 2621 2622 u8 tx_overflow_buffer_pkt_high[0x20]; 2623 2624 u8 tx_overflow_buffer_pkt_low[0x20]; 2625 2626 u8 outbound_stalled_reads[0x20]; 2627 2628 u8 outbound_stalled_writes[0x20]; 2629 2630 u8 outbound_stalled_reads_events[0x20]; 2631 2632 u8 outbound_stalled_writes_events[0x20]; 2633 2634 u8 reserved_at_200[0x5c0]; 2635 }; 2636 2637 struct mlx5_ifc_cmd_inter_comp_event_bits { 2638 u8 command_completion_vector[0x20]; 2639 2640 u8 reserved_at_20[0xc0]; 2641 }; 2642 2643 struct mlx5_ifc_stall_vl_event_bits { 2644 u8 reserved_at_0[0x18]; 2645 u8 port_num[0x1]; 2646 u8 reserved_at_19[0x3]; 2647 u8 vl[0x4]; 2648 2649 u8 reserved_at_20[0xa0]; 2650 }; 2651 2652 struct mlx5_ifc_db_bf_congestion_event_bits { 2653 u8 event_subtype[0x8]; 2654 u8 reserved_at_8[0x8]; 2655 u8 congestion_level[0x8]; 2656 u8 reserved_at_18[0x8]; 2657 2658 u8 reserved_at_20[0xa0]; 2659 }; 2660 2661 struct mlx5_ifc_gpio_event_bits { 2662 u8 reserved_at_0[0x60]; 2663 2664 u8 gpio_event_hi[0x20]; 2665 2666 u8 gpio_event_lo[0x20]; 2667 2668 u8 reserved_at_a0[0x40]; 2669 }; 2670 2671 struct mlx5_ifc_port_state_change_event_bits { 2672 u8 reserved_at_0[0x40]; 2673 2674 u8 port_num[0x4]; 2675 u8 reserved_at_44[0x1c]; 2676 2677 u8 reserved_at_60[0x80]; 2678 }; 2679 2680 struct mlx5_ifc_dropped_packet_logged_bits { 2681 u8 reserved_at_0[0xe0]; 2682 }; 2683 2684 enum { 2685 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2686 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2687 }; 2688 2689 struct mlx5_ifc_cq_error_bits { 2690 u8 reserved_at_0[0x8]; 2691 u8 cqn[0x18]; 2692 2693 u8 reserved_at_20[0x20]; 2694 2695 u8 reserved_at_40[0x18]; 2696 u8 syndrome[0x8]; 2697 2698 u8 reserved_at_60[0x80]; 2699 }; 2700 2701 struct mlx5_ifc_rdma_page_fault_event_bits { 2702 u8 bytes_committed[0x20]; 2703 2704 u8 r_key[0x20]; 2705 2706 u8 reserved_at_40[0x10]; 2707 u8 packet_len[0x10]; 2708 2709 u8 rdma_op_len[0x20]; 2710 2711 u8 rdma_va[0x40]; 2712 2713 u8 reserved_at_c0[0x5]; 2714 u8 rdma[0x1]; 2715 u8 write[0x1]; 2716 u8 requestor[0x1]; 2717 u8 qp_number[0x18]; 2718 }; 2719 2720 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2721 u8 bytes_committed[0x20]; 2722 2723 u8 reserved_at_20[0x10]; 2724 u8 wqe_index[0x10]; 2725 2726 u8 reserved_at_40[0x10]; 2727 u8 len[0x10]; 2728 2729 u8 reserved_at_60[0x60]; 2730 2731 u8 reserved_at_c0[0x5]; 2732 u8 rdma[0x1]; 2733 u8 write_read[0x1]; 2734 u8 requestor[0x1]; 2735 u8 qpn[0x18]; 2736 }; 2737 2738 struct mlx5_ifc_qp_events_bits { 2739 u8 reserved_at_0[0xa0]; 2740 2741 u8 type[0x8]; 2742 u8 reserved_at_a8[0x18]; 2743 2744 u8 reserved_at_c0[0x8]; 2745 u8 qpn_rqn_sqn[0x18]; 2746 }; 2747 2748 struct mlx5_ifc_dct_events_bits { 2749 u8 reserved_at_0[0xc0]; 2750 2751 u8 reserved_at_c0[0x8]; 2752 u8 dct_number[0x18]; 2753 }; 2754 2755 struct mlx5_ifc_comp_event_bits { 2756 u8 reserved_at_0[0xc0]; 2757 2758 u8 reserved_at_c0[0x8]; 2759 u8 cq_number[0x18]; 2760 }; 2761 2762 enum { 2763 MLX5_QPC_STATE_RST = 0x0, 2764 MLX5_QPC_STATE_INIT = 0x1, 2765 MLX5_QPC_STATE_RTR = 0x2, 2766 MLX5_QPC_STATE_RTS = 0x3, 2767 MLX5_QPC_STATE_SQER = 0x4, 2768 MLX5_QPC_STATE_ERR = 0x6, 2769 MLX5_QPC_STATE_SQD = 0x7, 2770 MLX5_QPC_STATE_SUSPENDED = 0x9, 2771 }; 2772 2773 enum { 2774 MLX5_QPC_ST_RC = 0x0, 2775 MLX5_QPC_ST_UC = 0x1, 2776 MLX5_QPC_ST_UD = 0x2, 2777 MLX5_QPC_ST_XRC = 0x3, 2778 MLX5_QPC_ST_DCI = 0x5, 2779 MLX5_QPC_ST_QP0 = 0x7, 2780 MLX5_QPC_ST_QP1 = 0x8, 2781 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2782 MLX5_QPC_ST_REG_UMR = 0xc, 2783 }; 2784 2785 enum { 2786 MLX5_QPC_PM_STATE_ARMED = 0x0, 2787 MLX5_QPC_PM_STATE_REARM = 0x1, 2788 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2789 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2790 }; 2791 2792 enum { 2793 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2794 }; 2795 2796 enum { 2797 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2798 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2799 }; 2800 2801 enum { 2802 MLX5_QPC_MTU_256_BYTES = 0x1, 2803 MLX5_QPC_MTU_512_BYTES = 0x2, 2804 MLX5_QPC_MTU_1K_BYTES = 0x3, 2805 MLX5_QPC_MTU_2K_BYTES = 0x4, 2806 MLX5_QPC_MTU_4K_BYTES = 0x5, 2807 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2808 }; 2809 2810 enum { 2811 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2812 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2813 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2814 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2815 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2816 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2817 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2818 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2819 }; 2820 2821 enum { 2822 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2823 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2824 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2825 }; 2826 2827 enum { 2828 MLX5_QPC_CS_RES_DISABLE = 0x0, 2829 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2830 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2831 }; 2832 2833 struct mlx5_ifc_qpc_bits { 2834 u8 state[0x4]; 2835 u8 lag_tx_port_affinity[0x4]; 2836 u8 st[0x8]; 2837 u8 reserved_at_10[0x3]; 2838 u8 pm_state[0x2]; 2839 u8 reserved_at_15[0x1]; 2840 u8 req_e2e_credit_mode[0x2]; 2841 u8 offload_type[0x4]; 2842 u8 end_padding_mode[0x2]; 2843 u8 reserved_at_1e[0x2]; 2844 2845 u8 wq_signature[0x1]; 2846 u8 block_lb_mc[0x1]; 2847 u8 atomic_like_write_en[0x1]; 2848 u8 latency_sensitive[0x1]; 2849 u8 reserved_at_24[0x1]; 2850 u8 drain_sigerr[0x1]; 2851 u8 reserved_at_26[0x2]; 2852 u8 pd[0x18]; 2853 2854 u8 mtu[0x3]; 2855 u8 log_msg_max[0x5]; 2856 u8 reserved_at_48[0x1]; 2857 u8 log_rq_size[0x4]; 2858 u8 log_rq_stride[0x3]; 2859 u8 no_sq[0x1]; 2860 u8 log_sq_size[0x4]; 2861 u8 reserved_at_55[0x6]; 2862 u8 rlky[0x1]; 2863 u8 ulp_stateless_offload_mode[0x4]; 2864 2865 u8 counter_set_id[0x8]; 2866 u8 uar_page[0x18]; 2867 2868 u8 reserved_at_80[0x8]; 2869 u8 user_index[0x18]; 2870 2871 u8 reserved_at_a0[0x3]; 2872 u8 log_page_size[0x5]; 2873 u8 remote_qpn[0x18]; 2874 2875 struct mlx5_ifc_ads_bits primary_address_path; 2876 2877 struct mlx5_ifc_ads_bits secondary_address_path; 2878 2879 u8 log_ack_req_freq[0x4]; 2880 u8 reserved_at_384[0x4]; 2881 u8 log_sra_max[0x3]; 2882 u8 reserved_at_38b[0x2]; 2883 u8 retry_count[0x3]; 2884 u8 rnr_retry[0x3]; 2885 u8 reserved_at_393[0x1]; 2886 u8 fre[0x1]; 2887 u8 cur_rnr_retry[0x3]; 2888 u8 cur_retry_count[0x3]; 2889 u8 reserved_at_39b[0x5]; 2890 2891 u8 reserved_at_3a0[0x20]; 2892 2893 u8 reserved_at_3c0[0x8]; 2894 u8 next_send_psn[0x18]; 2895 2896 u8 reserved_at_3e0[0x8]; 2897 u8 cqn_snd[0x18]; 2898 2899 u8 reserved_at_400[0x8]; 2900 u8 deth_sqpn[0x18]; 2901 2902 u8 reserved_at_420[0x20]; 2903 2904 u8 reserved_at_440[0x8]; 2905 u8 last_acked_psn[0x18]; 2906 2907 u8 reserved_at_460[0x8]; 2908 u8 ssn[0x18]; 2909 2910 u8 reserved_at_480[0x8]; 2911 u8 log_rra_max[0x3]; 2912 u8 reserved_at_48b[0x1]; 2913 u8 atomic_mode[0x4]; 2914 u8 rre[0x1]; 2915 u8 rwe[0x1]; 2916 u8 rae[0x1]; 2917 u8 reserved_at_493[0x1]; 2918 u8 page_offset[0x6]; 2919 u8 reserved_at_49a[0x3]; 2920 u8 cd_slave_receive[0x1]; 2921 u8 cd_slave_send[0x1]; 2922 u8 cd_master[0x1]; 2923 2924 u8 reserved_at_4a0[0x3]; 2925 u8 min_rnr_nak[0x5]; 2926 u8 next_rcv_psn[0x18]; 2927 2928 u8 reserved_at_4c0[0x8]; 2929 u8 xrcd[0x18]; 2930 2931 u8 reserved_at_4e0[0x8]; 2932 u8 cqn_rcv[0x18]; 2933 2934 u8 dbr_addr[0x40]; 2935 2936 u8 q_key[0x20]; 2937 2938 u8 reserved_at_560[0x5]; 2939 u8 rq_type[0x3]; 2940 u8 srqn_rmpn_xrqn[0x18]; 2941 2942 u8 reserved_at_580[0x8]; 2943 u8 rmsn[0x18]; 2944 2945 u8 hw_sq_wqebb_counter[0x10]; 2946 u8 sw_sq_wqebb_counter[0x10]; 2947 2948 u8 hw_rq_counter[0x20]; 2949 2950 u8 sw_rq_counter[0x20]; 2951 2952 u8 reserved_at_600[0x20]; 2953 2954 u8 reserved_at_620[0xf]; 2955 u8 cgs[0x1]; 2956 u8 cs_req[0x8]; 2957 u8 cs_res[0x8]; 2958 2959 u8 dc_access_key[0x40]; 2960 2961 u8 reserved_at_680[0x3]; 2962 u8 dbr_umem_valid[0x1]; 2963 2964 u8 reserved_at_684[0xbc]; 2965 }; 2966 2967 struct mlx5_ifc_roce_addr_layout_bits { 2968 u8 source_l3_address[16][0x8]; 2969 2970 u8 reserved_at_80[0x3]; 2971 u8 vlan_valid[0x1]; 2972 u8 vlan_id[0xc]; 2973 u8 source_mac_47_32[0x10]; 2974 2975 u8 source_mac_31_0[0x20]; 2976 2977 u8 reserved_at_c0[0x14]; 2978 u8 roce_l3_type[0x4]; 2979 u8 roce_version[0x8]; 2980 2981 u8 reserved_at_e0[0x20]; 2982 }; 2983 2984 union mlx5_ifc_hca_cap_union_bits { 2985 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2986 struct mlx5_ifc_odp_cap_bits odp_cap; 2987 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2988 struct mlx5_ifc_roce_cap_bits roce_cap; 2989 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2990 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2991 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2992 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2993 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2994 struct mlx5_ifc_qos_cap_bits qos_cap; 2995 struct mlx5_ifc_debug_cap_bits debug_cap; 2996 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2997 struct mlx5_ifc_tls_cap_bits tls_cap; 2998 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2999 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3000 u8 reserved_at_0[0x8000]; 3001 }; 3002 3003 enum { 3004 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3005 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3006 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3007 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3008 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3009 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3010 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3011 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3012 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3013 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3014 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3015 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3016 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3017 }; 3018 3019 enum { 3020 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3021 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3022 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3023 }; 3024 3025 struct mlx5_ifc_vlan_bits { 3026 u8 ethtype[0x10]; 3027 u8 prio[0x3]; 3028 u8 cfi[0x1]; 3029 u8 vid[0xc]; 3030 }; 3031 3032 struct mlx5_ifc_flow_context_bits { 3033 struct mlx5_ifc_vlan_bits push_vlan; 3034 3035 u8 group_id[0x20]; 3036 3037 u8 reserved_at_40[0x8]; 3038 u8 flow_tag[0x18]; 3039 3040 u8 reserved_at_60[0x10]; 3041 u8 action[0x10]; 3042 3043 u8 extended_destination[0x1]; 3044 u8 reserved_at_81[0x1]; 3045 u8 flow_source[0x2]; 3046 u8 reserved_at_84[0x4]; 3047 u8 destination_list_size[0x18]; 3048 3049 u8 reserved_at_a0[0x8]; 3050 u8 flow_counter_list_size[0x18]; 3051 3052 u8 packet_reformat_id[0x20]; 3053 3054 u8 modify_header_id[0x20]; 3055 3056 struct mlx5_ifc_vlan_bits push_vlan_2; 3057 3058 u8 ipsec_obj_id[0x20]; 3059 u8 reserved_at_140[0xc0]; 3060 3061 struct mlx5_ifc_fte_match_param_bits match_value; 3062 3063 u8 reserved_at_1200[0x600]; 3064 3065 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3066 }; 3067 3068 enum { 3069 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3070 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3071 }; 3072 3073 struct mlx5_ifc_xrc_srqc_bits { 3074 u8 state[0x4]; 3075 u8 log_xrc_srq_size[0x4]; 3076 u8 reserved_at_8[0x18]; 3077 3078 u8 wq_signature[0x1]; 3079 u8 cont_srq[0x1]; 3080 u8 reserved_at_22[0x1]; 3081 u8 rlky[0x1]; 3082 u8 basic_cyclic_rcv_wqe[0x1]; 3083 u8 log_rq_stride[0x3]; 3084 u8 xrcd[0x18]; 3085 3086 u8 page_offset[0x6]; 3087 u8 reserved_at_46[0x1]; 3088 u8 dbr_umem_valid[0x1]; 3089 u8 cqn[0x18]; 3090 3091 u8 reserved_at_60[0x20]; 3092 3093 u8 user_index_equal_xrc_srqn[0x1]; 3094 u8 reserved_at_81[0x1]; 3095 u8 log_page_size[0x6]; 3096 u8 user_index[0x18]; 3097 3098 u8 reserved_at_a0[0x20]; 3099 3100 u8 reserved_at_c0[0x8]; 3101 u8 pd[0x18]; 3102 3103 u8 lwm[0x10]; 3104 u8 wqe_cnt[0x10]; 3105 3106 u8 reserved_at_100[0x40]; 3107 3108 u8 db_record_addr_h[0x20]; 3109 3110 u8 db_record_addr_l[0x1e]; 3111 u8 reserved_at_17e[0x2]; 3112 3113 u8 reserved_at_180[0x80]; 3114 }; 3115 3116 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3117 u8 counter_error_queues[0x20]; 3118 3119 u8 total_error_queues[0x20]; 3120 3121 u8 send_queue_priority_update_flow[0x20]; 3122 3123 u8 reserved_at_60[0x20]; 3124 3125 u8 nic_receive_steering_discard[0x40]; 3126 3127 u8 receive_discard_vport_down[0x40]; 3128 3129 u8 transmit_discard_vport_down[0x40]; 3130 3131 u8 reserved_at_140[0xa0]; 3132 3133 u8 internal_rq_out_of_buffer[0x20]; 3134 3135 u8 reserved_at_200[0xe00]; 3136 }; 3137 3138 struct mlx5_ifc_traffic_counter_bits { 3139 u8 packets[0x40]; 3140 3141 u8 octets[0x40]; 3142 }; 3143 3144 struct mlx5_ifc_tisc_bits { 3145 u8 strict_lag_tx_port_affinity[0x1]; 3146 u8 tls_en[0x1]; 3147 u8 reserved_at_2[0x2]; 3148 u8 lag_tx_port_affinity[0x04]; 3149 3150 u8 reserved_at_8[0x4]; 3151 u8 prio[0x4]; 3152 u8 reserved_at_10[0x10]; 3153 3154 u8 reserved_at_20[0x100]; 3155 3156 u8 reserved_at_120[0x8]; 3157 u8 transport_domain[0x18]; 3158 3159 u8 reserved_at_140[0x8]; 3160 u8 underlay_qpn[0x18]; 3161 3162 u8 reserved_at_160[0x8]; 3163 u8 pd[0x18]; 3164 3165 u8 reserved_at_180[0x380]; 3166 }; 3167 3168 enum { 3169 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3170 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3171 }; 3172 3173 enum { 3174 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3175 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3176 }; 3177 3178 enum { 3179 MLX5_RX_HASH_FN_NONE = 0x0, 3180 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3181 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3182 }; 3183 3184 enum { 3185 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3186 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3187 }; 3188 3189 struct mlx5_ifc_tirc_bits { 3190 u8 reserved_at_0[0x20]; 3191 3192 u8 disp_type[0x4]; 3193 u8 tls_en[0x1]; 3194 u8 reserved_at_25[0x1b]; 3195 3196 u8 reserved_at_40[0x40]; 3197 3198 u8 reserved_at_80[0x4]; 3199 u8 lro_timeout_period_usecs[0x10]; 3200 u8 lro_enable_mask[0x4]; 3201 u8 lro_max_ip_payload_size[0x8]; 3202 3203 u8 reserved_at_a0[0x40]; 3204 3205 u8 reserved_at_e0[0x8]; 3206 u8 inline_rqn[0x18]; 3207 3208 u8 rx_hash_symmetric[0x1]; 3209 u8 reserved_at_101[0x1]; 3210 u8 tunneled_offload_en[0x1]; 3211 u8 reserved_at_103[0x5]; 3212 u8 indirect_table[0x18]; 3213 3214 u8 rx_hash_fn[0x4]; 3215 u8 reserved_at_124[0x2]; 3216 u8 self_lb_block[0x2]; 3217 u8 transport_domain[0x18]; 3218 3219 u8 rx_hash_toeplitz_key[10][0x20]; 3220 3221 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3222 3223 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3224 3225 u8 reserved_at_2c0[0x4c0]; 3226 }; 3227 3228 enum { 3229 MLX5_SRQC_STATE_GOOD = 0x0, 3230 MLX5_SRQC_STATE_ERROR = 0x1, 3231 }; 3232 3233 struct mlx5_ifc_srqc_bits { 3234 u8 state[0x4]; 3235 u8 log_srq_size[0x4]; 3236 u8 reserved_at_8[0x18]; 3237 3238 u8 wq_signature[0x1]; 3239 u8 cont_srq[0x1]; 3240 u8 reserved_at_22[0x1]; 3241 u8 rlky[0x1]; 3242 u8 reserved_at_24[0x1]; 3243 u8 log_rq_stride[0x3]; 3244 u8 xrcd[0x18]; 3245 3246 u8 page_offset[0x6]; 3247 u8 reserved_at_46[0x2]; 3248 u8 cqn[0x18]; 3249 3250 u8 reserved_at_60[0x20]; 3251 3252 u8 reserved_at_80[0x2]; 3253 u8 log_page_size[0x6]; 3254 u8 reserved_at_88[0x18]; 3255 3256 u8 reserved_at_a0[0x20]; 3257 3258 u8 reserved_at_c0[0x8]; 3259 u8 pd[0x18]; 3260 3261 u8 lwm[0x10]; 3262 u8 wqe_cnt[0x10]; 3263 3264 u8 reserved_at_100[0x40]; 3265 3266 u8 dbr_addr[0x40]; 3267 3268 u8 reserved_at_180[0x80]; 3269 }; 3270 3271 enum { 3272 MLX5_SQC_STATE_RST = 0x0, 3273 MLX5_SQC_STATE_RDY = 0x1, 3274 MLX5_SQC_STATE_ERR = 0x3, 3275 }; 3276 3277 struct mlx5_ifc_sqc_bits { 3278 u8 rlky[0x1]; 3279 u8 cd_master[0x1]; 3280 u8 fre[0x1]; 3281 u8 flush_in_error_en[0x1]; 3282 u8 allow_multi_pkt_send_wqe[0x1]; 3283 u8 min_wqe_inline_mode[0x3]; 3284 u8 state[0x4]; 3285 u8 reg_umr[0x1]; 3286 u8 allow_swp[0x1]; 3287 u8 hairpin[0x1]; 3288 u8 reserved_at_f[0x11]; 3289 3290 u8 reserved_at_20[0x8]; 3291 u8 user_index[0x18]; 3292 3293 u8 reserved_at_40[0x8]; 3294 u8 cqn[0x18]; 3295 3296 u8 reserved_at_60[0x8]; 3297 u8 hairpin_peer_rq[0x18]; 3298 3299 u8 reserved_at_80[0x10]; 3300 u8 hairpin_peer_vhca[0x10]; 3301 3302 u8 reserved_at_a0[0x50]; 3303 3304 u8 packet_pacing_rate_limit_index[0x10]; 3305 u8 tis_lst_sz[0x10]; 3306 u8 reserved_at_110[0x10]; 3307 3308 u8 reserved_at_120[0x40]; 3309 3310 u8 reserved_at_160[0x8]; 3311 u8 tis_num_0[0x18]; 3312 3313 struct mlx5_ifc_wq_bits wq; 3314 }; 3315 3316 enum { 3317 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3318 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3319 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3320 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3321 }; 3322 3323 enum { 3324 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3325 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3326 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3327 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3328 }; 3329 3330 struct mlx5_ifc_scheduling_context_bits { 3331 u8 element_type[0x8]; 3332 u8 reserved_at_8[0x18]; 3333 3334 u8 element_attributes[0x20]; 3335 3336 u8 parent_element_id[0x20]; 3337 3338 u8 reserved_at_60[0x40]; 3339 3340 u8 bw_share[0x20]; 3341 3342 u8 max_average_bw[0x20]; 3343 3344 u8 reserved_at_e0[0x120]; 3345 }; 3346 3347 struct mlx5_ifc_rqtc_bits { 3348 u8 reserved_at_0[0xa0]; 3349 3350 u8 reserved_at_a0[0x5]; 3351 u8 list_q_type[0x3]; 3352 u8 reserved_at_a8[0x8]; 3353 u8 rqt_max_size[0x10]; 3354 3355 u8 rq_vhca_id_format[0x1]; 3356 u8 reserved_at_c1[0xf]; 3357 u8 rqt_actual_size[0x10]; 3358 3359 u8 reserved_at_e0[0x6a0]; 3360 3361 struct mlx5_ifc_rq_num_bits rq_num[]; 3362 }; 3363 3364 enum { 3365 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3366 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3367 }; 3368 3369 enum { 3370 MLX5_RQC_STATE_RST = 0x0, 3371 MLX5_RQC_STATE_RDY = 0x1, 3372 MLX5_RQC_STATE_ERR = 0x3, 3373 }; 3374 3375 struct mlx5_ifc_rqc_bits { 3376 u8 rlky[0x1]; 3377 u8 delay_drop_en[0x1]; 3378 u8 scatter_fcs[0x1]; 3379 u8 vsd[0x1]; 3380 u8 mem_rq_type[0x4]; 3381 u8 state[0x4]; 3382 u8 reserved_at_c[0x1]; 3383 u8 flush_in_error_en[0x1]; 3384 u8 hairpin[0x1]; 3385 u8 reserved_at_f[0x11]; 3386 3387 u8 reserved_at_20[0x8]; 3388 u8 user_index[0x18]; 3389 3390 u8 reserved_at_40[0x8]; 3391 u8 cqn[0x18]; 3392 3393 u8 counter_set_id[0x8]; 3394 u8 reserved_at_68[0x18]; 3395 3396 u8 reserved_at_80[0x8]; 3397 u8 rmpn[0x18]; 3398 3399 u8 reserved_at_a0[0x8]; 3400 u8 hairpin_peer_sq[0x18]; 3401 3402 u8 reserved_at_c0[0x10]; 3403 u8 hairpin_peer_vhca[0x10]; 3404 3405 u8 reserved_at_e0[0xa0]; 3406 3407 struct mlx5_ifc_wq_bits wq; 3408 }; 3409 3410 enum { 3411 MLX5_RMPC_STATE_RDY = 0x1, 3412 MLX5_RMPC_STATE_ERR = 0x3, 3413 }; 3414 3415 struct mlx5_ifc_rmpc_bits { 3416 u8 reserved_at_0[0x8]; 3417 u8 state[0x4]; 3418 u8 reserved_at_c[0x14]; 3419 3420 u8 basic_cyclic_rcv_wqe[0x1]; 3421 u8 reserved_at_21[0x1f]; 3422 3423 u8 reserved_at_40[0x140]; 3424 3425 struct mlx5_ifc_wq_bits wq; 3426 }; 3427 3428 struct mlx5_ifc_nic_vport_context_bits { 3429 u8 reserved_at_0[0x5]; 3430 u8 min_wqe_inline_mode[0x3]; 3431 u8 reserved_at_8[0x15]; 3432 u8 disable_mc_local_lb[0x1]; 3433 u8 disable_uc_local_lb[0x1]; 3434 u8 roce_en[0x1]; 3435 3436 u8 arm_change_event[0x1]; 3437 u8 reserved_at_21[0x1a]; 3438 u8 event_on_mtu[0x1]; 3439 u8 event_on_promisc_change[0x1]; 3440 u8 event_on_vlan_change[0x1]; 3441 u8 event_on_mc_address_change[0x1]; 3442 u8 event_on_uc_address_change[0x1]; 3443 3444 u8 reserved_at_40[0xc]; 3445 3446 u8 affiliation_criteria[0x4]; 3447 u8 affiliated_vhca_id[0x10]; 3448 3449 u8 reserved_at_60[0xd0]; 3450 3451 u8 mtu[0x10]; 3452 3453 u8 system_image_guid[0x40]; 3454 u8 port_guid[0x40]; 3455 u8 node_guid[0x40]; 3456 3457 u8 reserved_at_200[0x140]; 3458 u8 qkey_violation_counter[0x10]; 3459 u8 reserved_at_350[0x430]; 3460 3461 u8 promisc_uc[0x1]; 3462 u8 promisc_mc[0x1]; 3463 u8 promisc_all[0x1]; 3464 u8 reserved_at_783[0x2]; 3465 u8 allowed_list_type[0x3]; 3466 u8 reserved_at_788[0xc]; 3467 u8 allowed_list_size[0xc]; 3468 3469 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3470 3471 u8 reserved_at_7e0[0x20]; 3472 3473 u8 current_uc_mac_address[][0x40]; 3474 }; 3475 3476 enum { 3477 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3478 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3479 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3480 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3481 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3482 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3483 }; 3484 3485 struct mlx5_ifc_mkc_bits { 3486 u8 reserved_at_0[0x1]; 3487 u8 free[0x1]; 3488 u8 reserved_at_2[0x1]; 3489 u8 access_mode_4_2[0x3]; 3490 u8 reserved_at_6[0x7]; 3491 u8 relaxed_ordering_write[0x1]; 3492 u8 reserved_at_e[0x1]; 3493 u8 small_fence_on_rdma_read_response[0x1]; 3494 u8 umr_en[0x1]; 3495 u8 a[0x1]; 3496 u8 rw[0x1]; 3497 u8 rr[0x1]; 3498 u8 lw[0x1]; 3499 u8 lr[0x1]; 3500 u8 access_mode_1_0[0x2]; 3501 u8 reserved_at_18[0x8]; 3502 3503 u8 qpn[0x18]; 3504 u8 mkey_7_0[0x8]; 3505 3506 u8 reserved_at_40[0x20]; 3507 3508 u8 length64[0x1]; 3509 u8 bsf_en[0x1]; 3510 u8 sync_umr[0x1]; 3511 u8 reserved_at_63[0x2]; 3512 u8 expected_sigerr_count[0x1]; 3513 u8 reserved_at_66[0x1]; 3514 u8 en_rinval[0x1]; 3515 u8 pd[0x18]; 3516 3517 u8 start_addr[0x40]; 3518 3519 u8 len[0x40]; 3520 3521 u8 bsf_octword_size[0x20]; 3522 3523 u8 reserved_at_120[0x80]; 3524 3525 u8 translations_octword_size[0x20]; 3526 3527 u8 reserved_at_1c0[0x19]; 3528 u8 relaxed_ordering_read[0x1]; 3529 u8 reserved_at_1d9[0x1]; 3530 u8 log_page_size[0x5]; 3531 3532 u8 reserved_at_1e0[0x20]; 3533 }; 3534 3535 struct mlx5_ifc_pkey_bits { 3536 u8 reserved_at_0[0x10]; 3537 u8 pkey[0x10]; 3538 }; 3539 3540 struct mlx5_ifc_array128_auto_bits { 3541 u8 array128_auto[16][0x8]; 3542 }; 3543 3544 struct mlx5_ifc_hca_vport_context_bits { 3545 u8 field_select[0x20]; 3546 3547 u8 reserved_at_20[0xe0]; 3548 3549 u8 sm_virt_aware[0x1]; 3550 u8 has_smi[0x1]; 3551 u8 has_raw[0x1]; 3552 u8 grh_required[0x1]; 3553 u8 reserved_at_104[0xc]; 3554 u8 port_physical_state[0x4]; 3555 u8 vport_state_policy[0x4]; 3556 u8 port_state[0x4]; 3557 u8 vport_state[0x4]; 3558 3559 u8 reserved_at_120[0x20]; 3560 3561 u8 system_image_guid[0x40]; 3562 3563 u8 port_guid[0x40]; 3564 3565 u8 node_guid[0x40]; 3566 3567 u8 cap_mask1[0x20]; 3568 3569 u8 cap_mask1_field_select[0x20]; 3570 3571 u8 cap_mask2[0x20]; 3572 3573 u8 cap_mask2_field_select[0x20]; 3574 3575 u8 reserved_at_280[0x80]; 3576 3577 u8 lid[0x10]; 3578 u8 reserved_at_310[0x4]; 3579 u8 init_type_reply[0x4]; 3580 u8 lmc[0x3]; 3581 u8 subnet_timeout[0x5]; 3582 3583 u8 sm_lid[0x10]; 3584 u8 sm_sl[0x4]; 3585 u8 reserved_at_334[0xc]; 3586 3587 u8 qkey_violation_counter[0x10]; 3588 u8 pkey_violation_counter[0x10]; 3589 3590 u8 reserved_at_360[0xca0]; 3591 }; 3592 3593 struct mlx5_ifc_esw_vport_context_bits { 3594 u8 fdb_to_vport_reg_c[0x1]; 3595 u8 reserved_at_1[0x2]; 3596 u8 vport_svlan_strip[0x1]; 3597 u8 vport_cvlan_strip[0x1]; 3598 u8 vport_svlan_insert[0x1]; 3599 u8 vport_cvlan_insert[0x2]; 3600 u8 fdb_to_vport_reg_c_id[0x8]; 3601 u8 reserved_at_10[0x10]; 3602 3603 u8 reserved_at_20[0x20]; 3604 3605 u8 svlan_cfi[0x1]; 3606 u8 svlan_pcp[0x3]; 3607 u8 svlan_id[0xc]; 3608 u8 cvlan_cfi[0x1]; 3609 u8 cvlan_pcp[0x3]; 3610 u8 cvlan_id[0xc]; 3611 3612 u8 reserved_at_60[0x720]; 3613 3614 u8 sw_steering_vport_icm_address_rx[0x40]; 3615 3616 u8 sw_steering_vport_icm_address_tx[0x40]; 3617 }; 3618 3619 enum { 3620 MLX5_EQC_STATUS_OK = 0x0, 3621 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3622 }; 3623 3624 enum { 3625 MLX5_EQC_ST_ARMED = 0x9, 3626 MLX5_EQC_ST_FIRED = 0xa, 3627 }; 3628 3629 struct mlx5_ifc_eqc_bits { 3630 u8 status[0x4]; 3631 u8 reserved_at_4[0x9]; 3632 u8 ec[0x1]; 3633 u8 oi[0x1]; 3634 u8 reserved_at_f[0x5]; 3635 u8 st[0x4]; 3636 u8 reserved_at_18[0x8]; 3637 3638 u8 reserved_at_20[0x20]; 3639 3640 u8 reserved_at_40[0x14]; 3641 u8 page_offset[0x6]; 3642 u8 reserved_at_5a[0x6]; 3643 3644 u8 reserved_at_60[0x3]; 3645 u8 log_eq_size[0x5]; 3646 u8 uar_page[0x18]; 3647 3648 u8 reserved_at_80[0x20]; 3649 3650 u8 reserved_at_a0[0x18]; 3651 u8 intr[0x8]; 3652 3653 u8 reserved_at_c0[0x3]; 3654 u8 log_page_size[0x5]; 3655 u8 reserved_at_c8[0x18]; 3656 3657 u8 reserved_at_e0[0x60]; 3658 3659 u8 reserved_at_140[0x8]; 3660 u8 consumer_counter[0x18]; 3661 3662 u8 reserved_at_160[0x8]; 3663 u8 producer_counter[0x18]; 3664 3665 u8 reserved_at_180[0x80]; 3666 }; 3667 3668 enum { 3669 MLX5_DCTC_STATE_ACTIVE = 0x0, 3670 MLX5_DCTC_STATE_DRAINING = 0x1, 3671 MLX5_DCTC_STATE_DRAINED = 0x2, 3672 }; 3673 3674 enum { 3675 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3676 MLX5_DCTC_CS_RES_NA = 0x1, 3677 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3678 }; 3679 3680 enum { 3681 MLX5_DCTC_MTU_256_BYTES = 0x1, 3682 MLX5_DCTC_MTU_512_BYTES = 0x2, 3683 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3684 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3685 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3686 }; 3687 3688 struct mlx5_ifc_dctc_bits { 3689 u8 reserved_at_0[0x4]; 3690 u8 state[0x4]; 3691 u8 reserved_at_8[0x18]; 3692 3693 u8 reserved_at_20[0x8]; 3694 u8 user_index[0x18]; 3695 3696 u8 reserved_at_40[0x8]; 3697 u8 cqn[0x18]; 3698 3699 u8 counter_set_id[0x8]; 3700 u8 atomic_mode[0x4]; 3701 u8 rre[0x1]; 3702 u8 rwe[0x1]; 3703 u8 rae[0x1]; 3704 u8 atomic_like_write_en[0x1]; 3705 u8 latency_sensitive[0x1]; 3706 u8 rlky[0x1]; 3707 u8 free_ar[0x1]; 3708 u8 reserved_at_73[0xd]; 3709 3710 u8 reserved_at_80[0x8]; 3711 u8 cs_res[0x8]; 3712 u8 reserved_at_90[0x3]; 3713 u8 min_rnr_nak[0x5]; 3714 u8 reserved_at_98[0x8]; 3715 3716 u8 reserved_at_a0[0x8]; 3717 u8 srqn_xrqn[0x18]; 3718 3719 u8 reserved_at_c0[0x8]; 3720 u8 pd[0x18]; 3721 3722 u8 tclass[0x8]; 3723 u8 reserved_at_e8[0x4]; 3724 u8 flow_label[0x14]; 3725 3726 u8 dc_access_key[0x40]; 3727 3728 u8 reserved_at_140[0x5]; 3729 u8 mtu[0x3]; 3730 u8 port[0x8]; 3731 u8 pkey_index[0x10]; 3732 3733 u8 reserved_at_160[0x8]; 3734 u8 my_addr_index[0x8]; 3735 u8 reserved_at_170[0x8]; 3736 u8 hop_limit[0x8]; 3737 3738 u8 dc_access_key_violation_count[0x20]; 3739 3740 u8 reserved_at_1a0[0x14]; 3741 u8 dei_cfi[0x1]; 3742 u8 eth_prio[0x3]; 3743 u8 ecn[0x2]; 3744 u8 dscp[0x6]; 3745 3746 u8 reserved_at_1c0[0x20]; 3747 u8 ece[0x20]; 3748 }; 3749 3750 enum { 3751 MLX5_CQC_STATUS_OK = 0x0, 3752 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3753 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3754 }; 3755 3756 enum { 3757 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3758 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3759 }; 3760 3761 enum { 3762 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3763 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3764 MLX5_CQC_ST_FIRED = 0xa, 3765 }; 3766 3767 enum { 3768 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3769 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3770 MLX5_CQ_PERIOD_NUM_MODES 3771 }; 3772 3773 struct mlx5_ifc_cqc_bits { 3774 u8 status[0x4]; 3775 u8 reserved_at_4[0x2]; 3776 u8 dbr_umem_valid[0x1]; 3777 u8 reserved_at_7[0x1]; 3778 u8 cqe_sz[0x3]; 3779 u8 cc[0x1]; 3780 u8 reserved_at_c[0x1]; 3781 u8 scqe_break_moderation_en[0x1]; 3782 u8 oi[0x1]; 3783 u8 cq_period_mode[0x2]; 3784 u8 cqe_comp_en[0x1]; 3785 u8 mini_cqe_res_format[0x2]; 3786 u8 st[0x4]; 3787 u8 reserved_at_18[0x8]; 3788 3789 u8 reserved_at_20[0x20]; 3790 3791 u8 reserved_at_40[0x14]; 3792 u8 page_offset[0x6]; 3793 u8 reserved_at_5a[0x6]; 3794 3795 u8 reserved_at_60[0x3]; 3796 u8 log_cq_size[0x5]; 3797 u8 uar_page[0x18]; 3798 3799 u8 reserved_at_80[0x4]; 3800 u8 cq_period[0xc]; 3801 u8 cq_max_count[0x10]; 3802 3803 u8 reserved_at_a0[0x18]; 3804 u8 c_eqn[0x8]; 3805 3806 u8 reserved_at_c0[0x3]; 3807 u8 log_page_size[0x5]; 3808 u8 reserved_at_c8[0x18]; 3809 3810 u8 reserved_at_e0[0x20]; 3811 3812 u8 reserved_at_100[0x8]; 3813 u8 last_notified_index[0x18]; 3814 3815 u8 reserved_at_120[0x8]; 3816 u8 last_solicit_index[0x18]; 3817 3818 u8 reserved_at_140[0x8]; 3819 u8 consumer_counter[0x18]; 3820 3821 u8 reserved_at_160[0x8]; 3822 u8 producer_counter[0x18]; 3823 3824 u8 reserved_at_180[0x40]; 3825 3826 u8 dbr_addr[0x40]; 3827 }; 3828 3829 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3830 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3831 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3832 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3833 u8 reserved_at_0[0x800]; 3834 }; 3835 3836 struct mlx5_ifc_query_adapter_param_block_bits { 3837 u8 reserved_at_0[0xc0]; 3838 3839 u8 reserved_at_c0[0x8]; 3840 u8 ieee_vendor_id[0x18]; 3841 3842 u8 reserved_at_e0[0x10]; 3843 u8 vsd_vendor_id[0x10]; 3844 3845 u8 vsd[208][0x8]; 3846 3847 u8 vsd_contd_psid[16][0x8]; 3848 }; 3849 3850 enum { 3851 MLX5_XRQC_STATE_GOOD = 0x0, 3852 MLX5_XRQC_STATE_ERROR = 0x1, 3853 }; 3854 3855 enum { 3856 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3857 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3858 }; 3859 3860 enum { 3861 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3862 }; 3863 3864 struct mlx5_ifc_tag_matching_topology_context_bits { 3865 u8 log_matching_list_sz[0x4]; 3866 u8 reserved_at_4[0xc]; 3867 u8 append_next_index[0x10]; 3868 3869 u8 sw_phase_cnt[0x10]; 3870 u8 hw_phase_cnt[0x10]; 3871 3872 u8 reserved_at_40[0x40]; 3873 }; 3874 3875 struct mlx5_ifc_xrqc_bits { 3876 u8 state[0x4]; 3877 u8 rlkey[0x1]; 3878 u8 reserved_at_5[0xf]; 3879 u8 topology[0x4]; 3880 u8 reserved_at_18[0x4]; 3881 u8 offload[0x4]; 3882 3883 u8 reserved_at_20[0x8]; 3884 u8 user_index[0x18]; 3885 3886 u8 reserved_at_40[0x8]; 3887 u8 cqn[0x18]; 3888 3889 u8 reserved_at_60[0xa0]; 3890 3891 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3892 3893 u8 reserved_at_180[0x280]; 3894 3895 struct mlx5_ifc_wq_bits wq; 3896 }; 3897 3898 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3899 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3900 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3901 u8 reserved_at_0[0x20]; 3902 }; 3903 3904 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3905 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3906 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3907 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3908 u8 reserved_at_0[0x20]; 3909 }; 3910 3911 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3912 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3913 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3914 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3915 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3916 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3917 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3918 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3919 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3920 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3921 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3922 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3923 u8 reserved_at_0[0x7c0]; 3924 }; 3925 3926 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3927 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3928 u8 reserved_at_0[0x7c0]; 3929 }; 3930 3931 union mlx5_ifc_event_auto_bits { 3932 struct mlx5_ifc_comp_event_bits comp_event; 3933 struct mlx5_ifc_dct_events_bits dct_events; 3934 struct mlx5_ifc_qp_events_bits qp_events; 3935 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3936 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3937 struct mlx5_ifc_cq_error_bits cq_error; 3938 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3939 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3940 struct mlx5_ifc_gpio_event_bits gpio_event; 3941 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3942 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3943 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3944 u8 reserved_at_0[0xe0]; 3945 }; 3946 3947 struct mlx5_ifc_health_buffer_bits { 3948 u8 reserved_at_0[0x100]; 3949 3950 u8 assert_existptr[0x20]; 3951 3952 u8 assert_callra[0x20]; 3953 3954 u8 reserved_at_140[0x40]; 3955 3956 u8 fw_version[0x20]; 3957 3958 u8 hw_id[0x20]; 3959 3960 u8 reserved_at_1c0[0x20]; 3961 3962 u8 irisc_index[0x8]; 3963 u8 synd[0x8]; 3964 u8 ext_synd[0x10]; 3965 }; 3966 3967 struct mlx5_ifc_register_loopback_control_bits { 3968 u8 no_lb[0x1]; 3969 u8 reserved_at_1[0x7]; 3970 u8 port[0x8]; 3971 u8 reserved_at_10[0x10]; 3972 3973 u8 reserved_at_20[0x60]; 3974 }; 3975 3976 struct mlx5_ifc_vport_tc_element_bits { 3977 u8 traffic_class[0x4]; 3978 u8 reserved_at_4[0xc]; 3979 u8 vport_number[0x10]; 3980 }; 3981 3982 struct mlx5_ifc_vport_element_bits { 3983 u8 reserved_at_0[0x10]; 3984 u8 vport_number[0x10]; 3985 }; 3986 3987 enum { 3988 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3989 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3990 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3991 }; 3992 3993 struct mlx5_ifc_tsar_element_bits { 3994 u8 reserved_at_0[0x8]; 3995 u8 tsar_type[0x8]; 3996 u8 reserved_at_10[0x10]; 3997 }; 3998 3999 enum { 4000 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4001 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4002 }; 4003 4004 struct mlx5_ifc_teardown_hca_out_bits { 4005 u8 status[0x8]; 4006 u8 reserved_at_8[0x18]; 4007 4008 u8 syndrome[0x20]; 4009 4010 u8 reserved_at_40[0x3f]; 4011 4012 u8 state[0x1]; 4013 }; 4014 4015 enum { 4016 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4017 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4018 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4019 }; 4020 4021 struct mlx5_ifc_teardown_hca_in_bits { 4022 u8 opcode[0x10]; 4023 u8 reserved_at_10[0x10]; 4024 4025 u8 reserved_at_20[0x10]; 4026 u8 op_mod[0x10]; 4027 4028 u8 reserved_at_40[0x10]; 4029 u8 profile[0x10]; 4030 4031 u8 reserved_at_60[0x20]; 4032 }; 4033 4034 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4035 u8 status[0x8]; 4036 u8 reserved_at_8[0x18]; 4037 4038 u8 syndrome[0x20]; 4039 4040 u8 reserved_at_40[0x40]; 4041 }; 4042 4043 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4044 u8 opcode[0x10]; 4045 u8 uid[0x10]; 4046 4047 u8 reserved_at_20[0x10]; 4048 u8 op_mod[0x10]; 4049 4050 u8 reserved_at_40[0x8]; 4051 u8 qpn[0x18]; 4052 4053 u8 reserved_at_60[0x20]; 4054 4055 u8 opt_param_mask[0x20]; 4056 4057 u8 reserved_at_a0[0x20]; 4058 4059 struct mlx5_ifc_qpc_bits qpc; 4060 4061 u8 reserved_at_800[0x80]; 4062 }; 4063 4064 struct mlx5_ifc_sqd2rts_qp_out_bits { 4065 u8 status[0x8]; 4066 u8 reserved_at_8[0x18]; 4067 4068 u8 syndrome[0x20]; 4069 4070 u8 reserved_at_40[0x40]; 4071 }; 4072 4073 struct mlx5_ifc_sqd2rts_qp_in_bits { 4074 u8 opcode[0x10]; 4075 u8 uid[0x10]; 4076 4077 u8 reserved_at_20[0x10]; 4078 u8 op_mod[0x10]; 4079 4080 u8 reserved_at_40[0x8]; 4081 u8 qpn[0x18]; 4082 4083 u8 reserved_at_60[0x20]; 4084 4085 u8 opt_param_mask[0x20]; 4086 4087 u8 reserved_at_a0[0x20]; 4088 4089 struct mlx5_ifc_qpc_bits qpc; 4090 4091 u8 reserved_at_800[0x80]; 4092 }; 4093 4094 struct mlx5_ifc_set_roce_address_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_at_8[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 4100 u8 reserved_at_40[0x40]; 4101 }; 4102 4103 struct mlx5_ifc_set_roce_address_in_bits { 4104 u8 opcode[0x10]; 4105 u8 reserved_at_10[0x10]; 4106 4107 u8 reserved_at_20[0x10]; 4108 u8 op_mod[0x10]; 4109 4110 u8 roce_address_index[0x10]; 4111 u8 reserved_at_50[0xc]; 4112 u8 vhca_port_num[0x4]; 4113 4114 u8 reserved_at_60[0x20]; 4115 4116 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4117 }; 4118 4119 struct mlx5_ifc_set_mad_demux_out_bits { 4120 u8 status[0x8]; 4121 u8 reserved_at_8[0x18]; 4122 4123 u8 syndrome[0x20]; 4124 4125 u8 reserved_at_40[0x40]; 4126 }; 4127 4128 enum { 4129 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4130 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4131 }; 4132 4133 struct mlx5_ifc_set_mad_demux_in_bits { 4134 u8 opcode[0x10]; 4135 u8 reserved_at_10[0x10]; 4136 4137 u8 reserved_at_20[0x10]; 4138 u8 op_mod[0x10]; 4139 4140 u8 reserved_at_40[0x20]; 4141 4142 u8 reserved_at_60[0x6]; 4143 u8 demux_mode[0x2]; 4144 u8 reserved_at_68[0x18]; 4145 }; 4146 4147 struct mlx5_ifc_set_l2_table_entry_out_bits { 4148 u8 status[0x8]; 4149 u8 reserved_at_8[0x18]; 4150 4151 u8 syndrome[0x20]; 4152 4153 u8 reserved_at_40[0x40]; 4154 }; 4155 4156 struct mlx5_ifc_set_l2_table_entry_in_bits { 4157 u8 opcode[0x10]; 4158 u8 reserved_at_10[0x10]; 4159 4160 u8 reserved_at_20[0x10]; 4161 u8 op_mod[0x10]; 4162 4163 u8 reserved_at_40[0x60]; 4164 4165 u8 reserved_at_a0[0x8]; 4166 u8 table_index[0x18]; 4167 4168 u8 reserved_at_c0[0x20]; 4169 4170 u8 reserved_at_e0[0x13]; 4171 u8 vlan_valid[0x1]; 4172 u8 vlan[0xc]; 4173 4174 struct mlx5_ifc_mac_address_layout_bits mac_address; 4175 4176 u8 reserved_at_140[0xc0]; 4177 }; 4178 4179 struct mlx5_ifc_set_issi_out_bits { 4180 u8 status[0x8]; 4181 u8 reserved_at_8[0x18]; 4182 4183 u8 syndrome[0x20]; 4184 4185 u8 reserved_at_40[0x40]; 4186 }; 4187 4188 struct mlx5_ifc_set_issi_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 reserved_at_40[0x10]; 4196 u8 current_issi[0x10]; 4197 4198 u8 reserved_at_60[0x20]; 4199 }; 4200 4201 struct mlx5_ifc_set_hca_cap_out_bits { 4202 u8 status[0x8]; 4203 u8 reserved_at_8[0x18]; 4204 4205 u8 syndrome[0x20]; 4206 4207 u8 reserved_at_40[0x40]; 4208 }; 4209 4210 struct mlx5_ifc_set_hca_cap_in_bits { 4211 u8 opcode[0x10]; 4212 u8 reserved_at_10[0x10]; 4213 4214 u8 reserved_at_20[0x10]; 4215 u8 op_mod[0x10]; 4216 4217 u8 reserved_at_40[0x40]; 4218 4219 union mlx5_ifc_hca_cap_union_bits capability; 4220 }; 4221 4222 enum { 4223 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4224 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4225 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4226 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4227 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4228 }; 4229 4230 struct mlx5_ifc_set_fte_out_bits { 4231 u8 status[0x8]; 4232 u8 reserved_at_8[0x18]; 4233 4234 u8 syndrome[0x20]; 4235 4236 u8 reserved_at_40[0x40]; 4237 }; 4238 4239 struct mlx5_ifc_set_fte_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_at_10[0x10]; 4242 4243 u8 reserved_at_20[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 other_vport[0x1]; 4247 u8 reserved_at_41[0xf]; 4248 u8 vport_number[0x10]; 4249 4250 u8 reserved_at_60[0x20]; 4251 4252 u8 table_type[0x8]; 4253 u8 reserved_at_88[0x18]; 4254 4255 u8 reserved_at_a0[0x8]; 4256 u8 table_id[0x18]; 4257 4258 u8 ignore_flow_level[0x1]; 4259 u8 reserved_at_c1[0x17]; 4260 u8 modify_enable_mask[0x8]; 4261 4262 u8 reserved_at_e0[0x20]; 4263 4264 u8 flow_index[0x20]; 4265 4266 u8 reserved_at_120[0xe0]; 4267 4268 struct mlx5_ifc_flow_context_bits flow_context; 4269 }; 4270 4271 struct mlx5_ifc_rts2rts_qp_out_bits { 4272 u8 status[0x8]; 4273 u8 reserved_at_8[0x18]; 4274 4275 u8 syndrome[0x20]; 4276 4277 u8 reserved_at_40[0x20]; 4278 u8 ece[0x20]; 4279 }; 4280 4281 struct mlx5_ifc_rts2rts_qp_in_bits { 4282 u8 opcode[0x10]; 4283 u8 uid[0x10]; 4284 4285 u8 reserved_at_20[0x10]; 4286 u8 op_mod[0x10]; 4287 4288 u8 reserved_at_40[0x8]; 4289 u8 qpn[0x18]; 4290 4291 u8 reserved_at_60[0x20]; 4292 4293 u8 opt_param_mask[0x20]; 4294 4295 u8 ece[0x20]; 4296 4297 struct mlx5_ifc_qpc_bits qpc; 4298 4299 u8 reserved_at_800[0x80]; 4300 }; 4301 4302 struct mlx5_ifc_rtr2rts_qp_out_bits { 4303 u8 status[0x8]; 4304 u8 reserved_at_8[0x18]; 4305 4306 u8 syndrome[0x20]; 4307 4308 u8 reserved_at_40[0x20]; 4309 u8 ece[0x20]; 4310 }; 4311 4312 struct mlx5_ifc_rtr2rts_qp_in_bits { 4313 u8 opcode[0x10]; 4314 u8 uid[0x10]; 4315 4316 u8 reserved_at_20[0x10]; 4317 u8 op_mod[0x10]; 4318 4319 u8 reserved_at_40[0x8]; 4320 u8 qpn[0x18]; 4321 4322 u8 reserved_at_60[0x20]; 4323 4324 u8 opt_param_mask[0x20]; 4325 4326 u8 ece[0x20]; 4327 4328 struct mlx5_ifc_qpc_bits qpc; 4329 4330 u8 reserved_at_800[0x80]; 4331 }; 4332 4333 struct mlx5_ifc_rst2init_qp_out_bits { 4334 u8 status[0x8]; 4335 u8 reserved_at_8[0x18]; 4336 4337 u8 syndrome[0x20]; 4338 4339 u8 reserved_at_40[0x20]; 4340 u8 ece[0x20]; 4341 }; 4342 4343 struct mlx5_ifc_rst2init_qp_in_bits { 4344 u8 opcode[0x10]; 4345 u8 uid[0x10]; 4346 4347 u8 reserved_at_20[0x10]; 4348 u8 op_mod[0x10]; 4349 4350 u8 reserved_at_40[0x8]; 4351 u8 qpn[0x18]; 4352 4353 u8 reserved_at_60[0x20]; 4354 4355 u8 opt_param_mask[0x20]; 4356 4357 u8 ece[0x20]; 4358 4359 struct mlx5_ifc_qpc_bits qpc; 4360 4361 u8 reserved_at_800[0x80]; 4362 }; 4363 4364 struct mlx5_ifc_query_xrq_out_bits { 4365 u8 status[0x8]; 4366 u8 reserved_at_8[0x18]; 4367 4368 u8 syndrome[0x20]; 4369 4370 u8 reserved_at_40[0x40]; 4371 4372 struct mlx5_ifc_xrqc_bits xrq_context; 4373 }; 4374 4375 struct mlx5_ifc_query_xrq_in_bits { 4376 u8 opcode[0x10]; 4377 u8 reserved_at_10[0x10]; 4378 4379 u8 reserved_at_20[0x10]; 4380 u8 op_mod[0x10]; 4381 4382 u8 reserved_at_40[0x8]; 4383 u8 xrqn[0x18]; 4384 4385 u8 reserved_at_60[0x20]; 4386 }; 4387 4388 struct mlx5_ifc_query_xrc_srq_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_at_8[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_at_40[0x40]; 4395 4396 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4397 4398 u8 reserved_at_280[0x600]; 4399 4400 u8 pas[][0x40]; 4401 }; 4402 4403 struct mlx5_ifc_query_xrc_srq_in_bits { 4404 u8 opcode[0x10]; 4405 u8 reserved_at_10[0x10]; 4406 4407 u8 reserved_at_20[0x10]; 4408 u8 op_mod[0x10]; 4409 4410 u8 reserved_at_40[0x8]; 4411 u8 xrc_srqn[0x18]; 4412 4413 u8 reserved_at_60[0x20]; 4414 }; 4415 4416 enum { 4417 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4418 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4419 }; 4420 4421 struct mlx5_ifc_query_vport_state_out_bits { 4422 u8 status[0x8]; 4423 u8 reserved_at_8[0x18]; 4424 4425 u8 syndrome[0x20]; 4426 4427 u8 reserved_at_40[0x20]; 4428 4429 u8 reserved_at_60[0x18]; 4430 u8 admin_state[0x4]; 4431 u8 state[0x4]; 4432 }; 4433 4434 enum { 4435 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4436 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4437 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4438 }; 4439 4440 struct mlx5_ifc_arm_monitor_counter_in_bits { 4441 u8 opcode[0x10]; 4442 u8 uid[0x10]; 4443 4444 u8 reserved_at_20[0x10]; 4445 u8 op_mod[0x10]; 4446 4447 u8 reserved_at_40[0x20]; 4448 4449 u8 reserved_at_60[0x20]; 4450 }; 4451 4452 struct mlx5_ifc_arm_monitor_counter_out_bits { 4453 u8 status[0x8]; 4454 u8 reserved_at_8[0x18]; 4455 4456 u8 syndrome[0x20]; 4457 4458 u8 reserved_at_40[0x40]; 4459 }; 4460 4461 enum { 4462 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4463 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4464 }; 4465 4466 enum mlx5_monitor_counter_ppcnt { 4467 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4468 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4469 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4470 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4471 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4472 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4473 }; 4474 4475 enum { 4476 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4477 }; 4478 4479 struct mlx5_ifc_monitor_counter_output_bits { 4480 u8 reserved_at_0[0x4]; 4481 u8 type[0x4]; 4482 u8 reserved_at_8[0x8]; 4483 u8 counter[0x10]; 4484 4485 u8 counter_group_id[0x20]; 4486 }; 4487 4488 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4489 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4490 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4491 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4492 4493 struct mlx5_ifc_set_monitor_counter_in_bits { 4494 u8 opcode[0x10]; 4495 u8 uid[0x10]; 4496 4497 u8 reserved_at_20[0x10]; 4498 u8 op_mod[0x10]; 4499 4500 u8 reserved_at_40[0x10]; 4501 u8 num_of_counters[0x10]; 4502 4503 u8 reserved_at_60[0x20]; 4504 4505 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4506 }; 4507 4508 struct mlx5_ifc_set_monitor_counter_out_bits { 4509 u8 status[0x8]; 4510 u8 reserved_at_8[0x18]; 4511 4512 u8 syndrome[0x20]; 4513 4514 u8 reserved_at_40[0x40]; 4515 }; 4516 4517 struct mlx5_ifc_query_vport_state_in_bits { 4518 u8 opcode[0x10]; 4519 u8 reserved_at_10[0x10]; 4520 4521 u8 reserved_at_20[0x10]; 4522 u8 op_mod[0x10]; 4523 4524 u8 other_vport[0x1]; 4525 u8 reserved_at_41[0xf]; 4526 u8 vport_number[0x10]; 4527 4528 u8 reserved_at_60[0x20]; 4529 }; 4530 4531 struct mlx5_ifc_query_vnic_env_out_bits { 4532 u8 status[0x8]; 4533 u8 reserved_at_8[0x18]; 4534 4535 u8 syndrome[0x20]; 4536 4537 u8 reserved_at_40[0x40]; 4538 4539 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4540 }; 4541 4542 enum { 4543 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4544 }; 4545 4546 struct mlx5_ifc_query_vnic_env_in_bits { 4547 u8 opcode[0x10]; 4548 u8 reserved_at_10[0x10]; 4549 4550 u8 reserved_at_20[0x10]; 4551 u8 op_mod[0x10]; 4552 4553 u8 other_vport[0x1]; 4554 u8 reserved_at_41[0xf]; 4555 u8 vport_number[0x10]; 4556 4557 u8 reserved_at_60[0x20]; 4558 }; 4559 4560 struct mlx5_ifc_query_vport_counter_out_bits { 4561 u8 status[0x8]; 4562 u8 reserved_at_8[0x18]; 4563 4564 u8 syndrome[0x20]; 4565 4566 u8 reserved_at_40[0x40]; 4567 4568 struct mlx5_ifc_traffic_counter_bits received_errors; 4569 4570 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4571 4572 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4573 4574 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4575 4576 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4577 4578 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4579 4580 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4581 4582 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4583 4584 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4585 4586 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4587 4588 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4589 4590 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4591 4592 u8 reserved_at_680[0xa00]; 4593 }; 4594 4595 enum { 4596 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4597 }; 4598 4599 struct mlx5_ifc_query_vport_counter_in_bits { 4600 u8 opcode[0x10]; 4601 u8 reserved_at_10[0x10]; 4602 4603 u8 reserved_at_20[0x10]; 4604 u8 op_mod[0x10]; 4605 4606 u8 other_vport[0x1]; 4607 u8 reserved_at_41[0xb]; 4608 u8 port_num[0x4]; 4609 u8 vport_number[0x10]; 4610 4611 u8 reserved_at_60[0x60]; 4612 4613 u8 clear[0x1]; 4614 u8 reserved_at_c1[0x1f]; 4615 4616 u8 reserved_at_e0[0x20]; 4617 }; 4618 4619 struct mlx5_ifc_query_tis_out_bits { 4620 u8 status[0x8]; 4621 u8 reserved_at_8[0x18]; 4622 4623 u8 syndrome[0x20]; 4624 4625 u8 reserved_at_40[0x40]; 4626 4627 struct mlx5_ifc_tisc_bits tis_context; 4628 }; 4629 4630 struct mlx5_ifc_query_tis_in_bits { 4631 u8 opcode[0x10]; 4632 u8 reserved_at_10[0x10]; 4633 4634 u8 reserved_at_20[0x10]; 4635 u8 op_mod[0x10]; 4636 4637 u8 reserved_at_40[0x8]; 4638 u8 tisn[0x18]; 4639 4640 u8 reserved_at_60[0x20]; 4641 }; 4642 4643 struct mlx5_ifc_query_tir_out_bits { 4644 u8 status[0x8]; 4645 u8 reserved_at_8[0x18]; 4646 4647 u8 syndrome[0x20]; 4648 4649 u8 reserved_at_40[0xc0]; 4650 4651 struct mlx5_ifc_tirc_bits tir_context; 4652 }; 4653 4654 struct mlx5_ifc_query_tir_in_bits { 4655 u8 opcode[0x10]; 4656 u8 reserved_at_10[0x10]; 4657 4658 u8 reserved_at_20[0x10]; 4659 u8 op_mod[0x10]; 4660 4661 u8 reserved_at_40[0x8]; 4662 u8 tirn[0x18]; 4663 4664 u8 reserved_at_60[0x20]; 4665 }; 4666 4667 struct mlx5_ifc_query_srq_out_bits { 4668 u8 status[0x8]; 4669 u8 reserved_at_8[0x18]; 4670 4671 u8 syndrome[0x20]; 4672 4673 u8 reserved_at_40[0x40]; 4674 4675 struct mlx5_ifc_srqc_bits srq_context_entry; 4676 4677 u8 reserved_at_280[0x600]; 4678 4679 u8 pas[][0x40]; 4680 }; 4681 4682 struct mlx5_ifc_query_srq_in_bits { 4683 u8 opcode[0x10]; 4684 u8 reserved_at_10[0x10]; 4685 4686 u8 reserved_at_20[0x10]; 4687 u8 op_mod[0x10]; 4688 4689 u8 reserved_at_40[0x8]; 4690 u8 srqn[0x18]; 4691 4692 u8 reserved_at_60[0x20]; 4693 }; 4694 4695 struct mlx5_ifc_query_sq_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_at_8[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_at_40[0xc0]; 4702 4703 struct mlx5_ifc_sqc_bits sq_context; 4704 }; 4705 4706 struct mlx5_ifc_query_sq_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x8]; 4714 u8 sqn[0x18]; 4715 4716 u8 reserved_at_60[0x20]; 4717 }; 4718 4719 struct mlx5_ifc_query_special_contexts_out_bits { 4720 u8 status[0x8]; 4721 u8 reserved_at_8[0x18]; 4722 4723 u8 syndrome[0x20]; 4724 4725 u8 dump_fill_mkey[0x20]; 4726 4727 u8 resd_lkey[0x20]; 4728 4729 u8 null_mkey[0x20]; 4730 4731 u8 reserved_at_a0[0x60]; 4732 }; 4733 4734 struct mlx5_ifc_query_special_contexts_in_bits { 4735 u8 opcode[0x10]; 4736 u8 reserved_at_10[0x10]; 4737 4738 u8 reserved_at_20[0x10]; 4739 u8 op_mod[0x10]; 4740 4741 u8 reserved_at_40[0x40]; 4742 }; 4743 4744 struct mlx5_ifc_query_scheduling_element_out_bits { 4745 u8 opcode[0x10]; 4746 u8 reserved_at_10[0x10]; 4747 4748 u8 reserved_at_20[0x10]; 4749 u8 op_mod[0x10]; 4750 4751 u8 reserved_at_40[0xc0]; 4752 4753 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4754 4755 u8 reserved_at_300[0x100]; 4756 }; 4757 4758 enum { 4759 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4760 }; 4761 4762 struct mlx5_ifc_query_scheduling_element_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_at_10[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 scheduling_hierarchy[0x8]; 4770 u8 reserved_at_48[0x18]; 4771 4772 u8 scheduling_element_id[0x20]; 4773 4774 u8 reserved_at_80[0x180]; 4775 }; 4776 4777 struct mlx5_ifc_query_rqt_out_bits { 4778 u8 status[0x8]; 4779 u8 reserved_at_8[0x18]; 4780 4781 u8 syndrome[0x20]; 4782 4783 u8 reserved_at_40[0xc0]; 4784 4785 struct mlx5_ifc_rqtc_bits rqt_context; 4786 }; 4787 4788 struct mlx5_ifc_query_rqt_in_bits { 4789 u8 opcode[0x10]; 4790 u8 reserved_at_10[0x10]; 4791 4792 u8 reserved_at_20[0x10]; 4793 u8 op_mod[0x10]; 4794 4795 u8 reserved_at_40[0x8]; 4796 u8 rqtn[0x18]; 4797 4798 u8 reserved_at_60[0x20]; 4799 }; 4800 4801 struct mlx5_ifc_query_rq_out_bits { 4802 u8 status[0x8]; 4803 u8 reserved_at_8[0x18]; 4804 4805 u8 syndrome[0x20]; 4806 4807 u8 reserved_at_40[0xc0]; 4808 4809 struct mlx5_ifc_rqc_bits rq_context; 4810 }; 4811 4812 struct mlx5_ifc_query_rq_in_bits { 4813 u8 opcode[0x10]; 4814 u8 reserved_at_10[0x10]; 4815 4816 u8 reserved_at_20[0x10]; 4817 u8 op_mod[0x10]; 4818 4819 u8 reserved_at_40[0x8]; 4820 u8 rqn[0x18]; 4821 4822 u8 reserved_at_60[0x20]; 4823 }; 4824 4825 struct mlx5_ifc_query_roce_address_out_bits { 4826 u8 status[0x8]; 4827 u8 reserved_at_8[0x18]; 4828 4829 u8 syndrome[0x20]; 4830 4831 u8 reserved_at_40[0x40]; 4832 4833 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4834 }; 4835 4836 struct mlx5_ifc_query_roce_address_in_bits { 4837 u8 opcode[0x10]; 4838 u8 reserved_at_10[0x10]; 4839 4840 u8 reserved_at_20[0x10]; 4841 u8 op_mod[0x10]; 4842 4843 u8 roce_address_index[0x10]; 4844 u8 reserved_at_50[0xc]; 4845 u8 vhca_port_num[0x4]; 4846 4847 u8 reserved_at_60[0x20]; 4848 }; 4849 4850 struct mlx5_ifc_query_rmp_out_bits { 4851 u8 status[0x8]; 4852 u8 reserved_at_8[0x18]; 4853 4854 u8 syndrome[0x20]; 4855 4856 u8 reserved_at_40[0xc0]; 4857 4858 struct mlx5_ifc_rmpc_bits rmp_context; 4859 }; 4860 4861 struct mlx5_ifc_query_rmp_in_bits { 4862 u8 opcode[0x10]; 4863 u8 reserved_at_10[0x10]; 4864 4865 u8 reserved_at_20[0x10]; 4866 u8 op_mod[0x10]; 4867 4868 u8 reserved_at_40[0x8]; 4869 u8 rmpn[0x18]; 4870 4871 u8 reserved_at_60[0x20]; 4872 }; 4873 4874 struct mlx5_ifc_query_qp_out_bits { 4875 u8 status[0x8]; 4876 u8 reserved_at_8[0x18]; 4877 4878 u8 syndrome[0x20]; 4879 4880 u8 reserved_at_40[0x40]; 4881 4882 u8 opt_param_mask[0x20]; 4883 4884 u8 ece[0x20]; 4885 4886 struct mlx5_ifc_qpc_bits qpc; 4887 4888 u8 reserved_at_800[0x80]; 4889 4890 u8 pas[][0x40]; 4891 }; 4892 4893 struct mlx5_ifc_query_qp_in_bits { 4894 u8 opcode[0x10]; 4895 u8 reserved_at_10[0x10]; 4896 4897 u8 reserved_at_20[0x10]; 4898 u8 op_mod[0x10]; 4899 4900 u8 reserved_at_40[0x8]; 4901 u8 qpn[0x18]; 4902 4903 u8 reserved_at_60[0x20]; 4904 }; 4905 4906 struct mlx5_ifc_query_q_counter_out_bits { 4907 u8 status[0x8]; 4908 u8 reserved_at_8[0x18]; 4909 4910 u8 syndrome[0x20]; 4911 4912 u8 reserved_at_40[0x40]; 4913 4914 u8 rx_write_requests[0x20]; 4915 4916 u8 reserved_at_a0[0x20]; 4917 4918 u8 rx_read_requests[0x20]; 4919 4920 u8 reserved_at_e0[0x20]; 4921 4922 u8 rx_atomic_requests[0x20]; 4923 4924 u8 reserved_at_120[0x20]; 4925 4926 u8 rx_dct_connect[0x20]; 4927 4928 u8 reserved_at_160[0x20]; 4929 4930 u8 out_of_buffer[0x20]; 4931 4932 u8 reserved_at_1a0[0x20]; 4933 4934 u8 out_of_sequence[0x20]; 4935 4936 u8 reserved_at_1e0[0x20]; 4937 4938 u8 duplicate_request[0x20]; 4939 4940 u8 reserved_at_220[0x20]; 4941 4942 u8 rnr_nak_retry_err[0x20]; 4943 4944 u8 reserved_at_260[0x20]; 4945 4946 u8 packet_seq_err[0x20]; 4947 4948 u8 reserved_at_2a0[0x20]; 4949 4950 u8 implied_nak_seq_err[0x20]; 4951 4952 u8 reserved_at_2e0[0x20]; 4953 4954 u8 local_ack_timeout_err[0x20]; 4955 4956 u8 reserved_at_320[0xa0]; 4957 4958 u8 resp_local_length_error[0x20]; 4959 4960 u8 req_local_length_error[0x20]; 4961 4962 u8 resp_local_qp_error[0x20]; 4963 4964 u8 local_operation_error[0x20]; 4965 4966 u8 resp_local_protection[0x20]; 4967 4968 u8 req_local_protection[0x20]; 4969 4970 u8 resp_cqe_error[0x20]; 4971 4972 u8 req_cqe_error[0x20]; 4973 4974 u8 req_mw_binding[0x20]; 4975 4976 u8 req_bad_response[0x20]; 4977 4978 u8 req_remote_invalid_request[0x20]; 4979 4980 u8 resp_remote_invalid_request[0x20]; 4981 4982 u8 req_remote_access_errors[0x20]; 4983 4984 u8 resp_remote_access_errors[0x20]; 4985 4986 u8 req_remote_operation_errors[0x20]; 4987 4988 u8 req_transport_retries_exceeded[0x20]; 4989 4990 u8 cq_overflow[0x20]; 4991 4992 u8 resp_cqe_flush_error[0x20]; 4993 4994 u8 req_cqe_flush_error[0x20]; 4995 4996 u8 reserved_at_620[0x20]; 4997 4998 u8 roce_adp_retrans[0x20]; 4999 5000 u8 roce_adp_retrans_to[0x20]; 5001 5002 u8 roce_slow_restart[0x20]; 5003 5004 u8 roce_slow_restart_cnps[0x20]; 5005 5006 u8 roce_slow_restart_trans[0x20]; 5007 5008 u8 reserved_at_6e0[0x120]; 5009 }; 5010 5011 struct mlx5_ifc_query_q_counter_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 reserved_at_40[0x80]; 5019 5020 u8 clear[0x1]; 5021 u8 reserved_at_c1[0x1f]; 5022 5023 u8 reserved_at_e0[0x18]; 5024 u8 counter_set_id[0x8]; 5025 }; 5026 5027 struct mlx5_ifc_query_pages_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_at_8[0x18]; 5030 5031 u8 syndrome[0x20]; 5032 5033 u8 embedded_cpu_function[0x1]; 5034 u8 reserved_at_41[0xf]; 5035 u8 function_id[0x10]; 5036 5037 u8 num_pages[0x20]; 5038 }; 5039 5040 enum { 5041 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5042 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5043 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5044 }; 5045 5046 struct mlx5_ifc_query_pages_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_at_10[0x10]; 5049 5050 u8 reserved_at_20[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 embedded_cpu_function[0x1]; 5054 u8 reserved_at_41[0xf]; 5055 u8 function_id[0x10]; 5056 5057 u8 reserved_at_60[0x20]; 5058 }; 5059 5060 struct mlx5_ifc_query_nic_vport_context_out_bits { 5061 u8 status[0x8]; 5062 u8 reserved_at_8[0x18]; 5063 5064 u8 syndrome[0x20]; 5065 5066 u8 reserved_at_40[0x40]; 5067 5068 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5069 }; 5070 5071 struct mlx5_ifc_query_nic_vport_context_in_bits { 5072 u8 opcode[0x10]; 5073 u8 reserved_at_10[0x10]; 5074 5075 u8 reserved_at_20[0x10]; 5076 u8 op_mod[0x10]; 5077 5078 u8 other_vport[0x1]; 5079 u8 reserved_at_41[0xf]; 5080 u8 vport_number[0x10]; 5081 5082 u8 reserved_at_60[0x5]; 5083 u8 allowed_list_type[0x3]; 5084 u8 reserved_at_68[0x18]; 5085 }; 5086 5087 struct mlx5_ifc_query_mkey_out_bits { 5088 u8 status[0x8]; 5089 u8 reserved_at_8[0x18]; 5090 5091 u8 syndrome[0x20]; 5092 5093 u8 reserved_at_40[0x40]; 5094 5095 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5096 5097 u8 reserved_at_280[0x600]; 5098 5099 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5100 5101 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5102 }; 5103 5104 struct mlx5_ifc_query_mkey_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 mkey_index[0x18]; 5113 5114 u8 pg_access[0x1]; 5115 u8 reserved_at_61[0x1f]; 5116 }; 5117 5118 struct mlx5_ifc_query_mad_demux_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 5126 u8 mad_dumux_parameters_block[0x20]; 5127 }; 5128 5129 struct mlx5_ifc_query_mad_demux_in_bits { 5130 u8 opcode[0x10]; 5131 u8 reserved_at_10[0x10]; 5132 5133 u8 reserved_at_20[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_at_40[0x40]; 5137 }; 5138 5139 struct mlx5_ifc_query_l2_table_entry_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_at_8[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_at_40[0xa0]; 5146 5147 u8 reserved_at_e0[0x13]; 5148 u8 vlan_valid[0x1]; 5149 u8 vlan[0xc]; 5150 5151 struct mlx5_ifc_mac_address_layout_bits mac_address; 5152 5153 u8 reserved_at_140[0xc0]; 5154 }; 5155 5156 struct mlx5_ifc_query_l2_table_entry_in_bits { 5157 u8 opcode[0x10]; 5158 u8 reserved_at_10[0x10]; 5159 5160 u8 reserved_at_20[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 reserved_at_40[0x60]; 5164 5165 u8 reserved_at_a0[0x8]; 5166 u8 table_index[0x18]; 5167 5168 u8 reserved_at_c0[0x140]; 5169 }; 5170 5171 struct mlx5_ifc_query_issi_out_bits { 5172 u8 status[0x8]; 5173 u8 reserved_at_8[0x18]; 5174 5175 u8 syndrome[0x20]; 5176 5177 u8 reserved_at_40[0x10]; 5178 u8 current_issi[0x10]; 5179 5180 u8 reserved_at_60[0xa0]; 5181 5182 u8 reserved_at_100[76][0x8]; 5183 u8 supported_issi_dw0[0x20]; 5184 }; 5185 5186 struct mlx5_ifc_query_issi_in_bits { 5187 u8 opcode[0x10]; 5188 u8 reserved_at_10[0x10]; 5189 5190 u8 reserved_at_20[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_at_40[0x40]; 5194 }; 5195 5196 struct mlx5_ifc_set_driver_version_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_0[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 u8 reserved_1[0x40]; 5202 }; 5203 5204 struct mlx5_ifc_set_driver_version_in_bits { 5205 u8 opcode[0x10]; 5206 u8 reserved_0[0x10]; 5207 5208 u8 reserved_1[0x10]; 5209 u8 op_mod[0x10]; 5210 5211 u8 reserved_2[0x40]; 5212 u8 driver_version[64][0x8]; 5213 }; 5214 5215 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5216 u8 status[0x8]; 5217 u8 reserved_at_8[0x18]; 5218 5219 u8 syndrome[0x20]; 5220 5221 u8 reserved_at_40[0x40]; 5222 5223 struct mlx5_ifc_pkey_bits pkey[]; 5224 }; 5225 5226 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5227 u8 opcode[0x10]; 5228 u8 reserved_at_10[0x10]; 5229 5230 u8 reserved_at_20[0x10]; 5231 u8 op_mod[0x10]; 5232 5233 u8 other_vport[0x1]; 5234 u8 reserved_at_41[0xb]; 5235 u8 port_num[0x4]; 5236 u8 vport_number[0x10]; 5237 5238 u8 reserved_at_60[0x10]; 5239 u8 pkey_index[0x10]; 5240 }; 5241 5242 enum { 5243 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5244 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5245 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5246 }; 5247 5248 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5249 u8 status[0x8]; 5250 u8 reserved_at_8[0x18]; 5251 5252 u8 syndrome[0x20]; 5253 5254 u8 reserved_at_40[0x20]; 5255 5256 u8 gids_num[0x10]; 5257 u8 reserved_at_70[0x10]; 5258 5259 struct mlx5_ifc_array128_auto_bits gid[]; 5260 }; 5261 5262 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5263 u8 opcode[0x10]; 5264 u8 reserved_at_10[0x10]; 5265 5266 u8 reserved_at_20[0x10]; 5267 u8 op_mod[0x10]; 5268 5269 u8 other_vport[0x1]; 5270 u8 reserved_at_41[0xb]; 5271 u8 port_num[0x4]; 5272 u8 vport_number[0x10]; 5273 5274 u8 reserved_at_60[0x10]; 5275 u8 gid_index[0x10]; 5276 }; 5277 5278 struct mlx5_ifc_query_hca_vport_context_out_bits { 5279 u8 status[0x8]; 5280 u8 reserved_at_8[0x18]; 5281 5282 u8 syndrome[0x20]; 5283 5284 u8 reserved_at_40[0x40]; 5285 5286 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5287 }; 5288 5289 struct mlx5_ifc_query_hca_vport_context_in_bits { 5290 u8 opcode[0x10]; 5291 u8 reserved_at_10[0x10]; 5292 5293 u8 reserved_at_20[0x10]; 5294 u8 op_mod[0x10]; 5295 5296 u8 other_vport[0x1]; 5297 u8 reserved_at_41[0xb]; 5298 u8 port_num[0x4]; 5299 u8 vport_number[0x10]; 5300 5301 u8 reserved_at_60[0x20]; 5302 }; 5303 5304 struct mlx5_ifc_query_hca_cap_out_bits { 5305 u8 status[0x8]; 5306 u8 reserved_at_8[0x18]; 5307 5308 u8 syndrome[0x20]; 5309 5310 u8 reserved_at_40[0x40]; 5311 5312 union mlx5_ifc_hca_cap_union_bits capability; 5313 }; 5314 5315 struct mlx5_ifc_query_hca_cap_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_at_10[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 other_function[0x1]; 5323 u8 reserved_at_41[0xf]; 5324 u8 function_id[0x10]; 5325 5326 u8 reserved_at_60[0x20]; 5327 }; 5328 5329 struct mlx5_ifc_other_hca_cap_bits { 5330 u8 roce[0x1]; 5331 u8 reserved_at_1[0x27f]; 5332 }; 5333 5334 struct mlx5_ifc_query_other_hca_cap_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_at_40[0x40]; 5341 5342 struct mlx5_ifc_other_hca_cap_bits other_capability; 5343 }; 5344 5345 struct mlx5_ifc_query_other_hca_cap_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_at_40[0x10]; 5353 u8 function_id[0x10]; 5354 5355 u8 reserved_at_60[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x40]; 5365 }; 5366 5367 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5368 u8 opcode[0x10]; 5369 u8 reserved_at_10[0x10]; 5370 5371 u8 reserved_at_20[0x10]; 5372 u8 op_mod[0x10]; 5373 5374 u8 reserved_at_40[0x10]; 5375 u8 function_id[0x10]; 5376 u8 field_select[0x20]; 5377 5378 struct mlx5_ifc_other_hca_cap_bits other_capability; 5379 }; 5380 5381 struct mlx5_ifc_flow_table_context_bits { 5382 u8 reformat_en[0x1]; 5383 u8 decap_en[0x1]; 5384 u8 sw_owner[0x1]; 5385 u8 termination_table[0x1]; 5386 u8 table_miss_action[0x4]; 5387 u8 level[0x8]; 5388 u8 reserved_at_10[0x8]; 5389 u8 log_size[0x8]; 5390 5391 u8 reserved_at_20[0x8]; 5392 u8 table_miss_id[0x18]; 5393 5394 u8 reserved_at_40[0x8]; 5395 u8 lag_master_next_table_id[0x18]; 5396 5397 u8 reserved_at_60[0x60]; 5398 5399 u8 sw_owner_icm_root_1[0x40]; 5400 5401 u8 sw_owner_icm_root_0[0x40]; 5402 5403 }; 5404 5405 struct mlx5_ifc_query_flow_table_out_bits { 5406 u8 status[0x8]; 5407 u8 reserved_at_8[0x18]; 5408 5409 u8 syndrome[0x20]; 5410 5411 u8 reserved_at_40[0x80]; 5412 5413 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5414 }; 5415 5416 struct mlx5_ifc_query_flow_table_in_bits { 5417 u8 opcode[0x10]; 5418 u8 reserved_at_10[0x10]; 5419 5420 u8 reserved_at_20[0x10]; 5421 u8 op_mod[0x10]; 5422 5423 u8 reserved_at_40[0x40]; 5424 5425 u8 table_type[0x8]; 5426 u8 reserved_at_88[0x18]; 5427 5428 u8 reserved_at_a0[0x8]; 5429 u8 table_id[0x18]; 5430 5431 u8 reserved_at_c0[0x140]; 5432 }; 5433 5434 struct mlx5_ifc_query_fte_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x1c0]; 5441 5442 struct mlx5_ifc_flow_context_bits flow_context; 5443 }; 5444 5445 struct mlx5_ifc_query_fte_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x40]; 5453 5454 u8 table_type[0x8]; 5455 u8 reserved_at_88[0x18]; 5456 5457 u8 reserved_at_a0[0x8]; 5458 u8 table_id[0x18]; 5459 5460 u8 reserved_at_c0[0x40]; 5461 5462 u8 flow_index[0x20]; 5463 5464 u8 reserved_at_120[0xe0]; 5465 }; 5466 5467 enum { 5468 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5469 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5470 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5471 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5472 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5473 }; 5474 5475 struct mlx5_ifc_query_flow_group_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0xa0]; 5482 5483 u8 start_flow_index[0x20]; 5484 5485 u8 reserved_at_100[0x20]; 5486 5487 u8 end_flow_index[0x20]; 5488 5489 u8 reserved_at_140[0xa0]; 5490 5491 u8 reserved_at_1e0[0x18]; 5492 u8 match_criteria_enable[0x8]; 5493 5494 struct mlx5_ifc_fte_match_param_bits match_criteria; 5495 5496 u8 reserved_at_1200[0xe00]; 5497 }; 5498 5499 struct mlx5_ifc_query_flow_group_in_bits { 5500 u8 opcode[0x10]; 5501 u8 reserved_at_10[0x10]; 5502 5503 u8 reserved_at_20[0x10]; 5504 u8 op_mod[0x10]; 5505 5506 u8 reserved_at_40[0x40]; 5507 5508 u8 table_type[0x8]; 5509 u8 reserved_at_88[0x18]; 5510 5511 u8 reserved_at_a0[0x8]; 5512 u8 table_id[0x18]; 5513 5514 u8 group_id[0x20]; 5515 5516 u8 reserved_at_e0[0x120]; 5517 }; 5518 5519 struct mlx5_ifc_query_flow_counter_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0x40]; 5526 5527 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5528 }; 5529 5530 struct mlx5_ifc_query_flow_counter_in_bits { 5531 u8 opcode[0x10]; 5532 u8 reserved_at_10[0x10]; 5533 5534 u8 reserved_at_20[0x10]; 5535 u8 op_mod[0x10]; 5536 5537 u8 reserved_at_40[0x80]; 5538 5539 u8 clear[0x1]; 5540 u8 reserved_at_c1[0xf]; 5541 u8 num_of_counters[0x10]; 5542 5543 u8 flow_counter_id[0x20]; 5544 }; 5545 5546 struct mlx5_ifc_query_esw_vport_context_out_bits { 5547 u8 status[0x8]; 5548 u8 reserved_at_8[0x18]; 5549 5550 u8 syndrome[0x20]; 5551 5552 u8 reserved_at_40[0x40]; 5553 5554 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5555 }; 5556 5557 struct mlx5_ifc_query_esw_vport_context_in_bits { 5558 u8 opcode[0x10]; 5559 u8 reserved_at_10[0x10]; 5560 5561 u8 reserved_at_20[0x10]; 5562 u8 op_mod[0x10]; 5563 5564 u8 other_vport[0x1]; 5565 u8 reserved_at_41[0xf]; 5566 u8 vport_number[0x10]; 5567 5568 u8 reserved_at_60[0x20]; 5569 }; 5570 5571 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5572 u8 status[0x8]; 5573 u8 reserved_at_8[0x18]; 5574 5575 u8 syndrome[0x20]; 5576 5577 u8 reserved_at_40[0x40]; 5578 }; 5579 5580 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5581 u8 reserved_at_0[0x1b]; 5582 u8 fdb_to_vport_reg_c_id[0x1]; 5583 u8 vport_cvlan_insert[0x1]; 5584 u8 vport_svlan_insert[0x1]; 5585 u8 vport_cvlan_strip[0x1]; 5586 u8 vport_svlan_strip[0x1]; 5587 }; 5588 5589 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5590 u8 opcode[0x10]; 5591 u8 reserved_at_10[0x10]; 5592 5593 u8 reserved_at_20[0x10]; 5594 u8 op_mod[0x10]; 5595 5596 u8 other_vport[0x1]; 5597 u8 reserved_at_41[0xf]; 5598 u8 vport_number[0x10]; 5599 5600 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5601 5602 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5603 }; 5604 5605 struct mlx5_ifc_query_eq_out_bits { 5606 u8 status[0x8]; 5607 u8 reserved_at_8[0x18]; 5608 5609 u8 syndrome[0x20]; 5610 5611 u8 reserved_at_40[0x40]; 5612 5613 struct mlx5_ifc_eqc_bits eq_context_entry; 5614 5615 u8 reserved_at_280[0x40]; 5616 5617 u8 event_bitmask[0x40]; 5618 5619 u8 reserved_at_300[0x580]; 5620 5621 u8 pas[][0x40]; 5622 }; 5623 5624 struct mlx5_ifc_query_eq_in_bits { 5625 u8 opcode[0x10]; 5626 u8 reserved_at_10[0x10]; 5627 5628 u8 reserved_at_20[0x10]; 5629 u8 op_mod[0x10]; 5630 5631 u8 reserved_at_40[0x18]; 5632 u8 eq_number[0x8]; 5633 5634 u8 reserved_at_60[0x20]; 5635 }; 5636 5637 struct mlx5_ifc_packet_reformat_context_in_bits { 5638 u8 reserved_at_0[0x5]; 5639 u8 reformat_type[0x3]; 5640 u8 reserved_at_8[0xe]; 5641 u8 reformat_data_size[0xa]; 5642 5643 u8 reserved_at_20[0x10]; 5644 u8 reformat_data[2][0x8]; 5645 5646 u8 more_reformat_data[][0x8]; 5647 }; 5648 5649 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5650 u8 status[0x8]; 5651 u8 reserved_at_8[0x18]; 5652 5653 u8 syndrome[0x20]; 5654 5655 u8 reserved_at_40[0xa0]; 5656 5657 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5658 }; 5659 5660 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5661 u8 opcode[0x10]; 5662 u8 reserved_at_10[0x10]; 5663 5664 u8 reserved_at_20[0x10]; 5665 u8 op_mod[0x10]; 5666 5667 u8 packet_reformat_id[0x20]; 5668 5669 u8 reserved_at_60[0xa0]; 5670 }; 5671 5672 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 packet_reformat_id[0x20]; 5679 5680 u8 reserved_at_60[0x20]; 5681 }; 5682 5683 enum mlx5_reformat_ctx_type { 5684 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5685 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5686 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5687 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5688 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5689 }; 5690 5691 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 reserved_at_40[0xa0]; 5699 5700 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5701 }; 5702 5703 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_at_8[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_at_40[0x40]; 5710 }; 5711 5712 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5713 u8 opcode[0x10]; 5714 u8 reserved_at_10[0x10]; 5715 5716 u8 reserved_20[0x10]; 5717 u8 op_mod[0x10]; 5718 5719 u8 packet_reformat_id[0x20]; 5720 5721 u8 reserved_60[0x20]; 5722 }; 5723 5724 struct mlx5_ifc_set_action_in_bits { 5725 u8 action_type[0x4]; 5726 u8 field[0xc]; 5727 u8 reserved_at_10[0x3]; 5728 u8 offset[0x5]; 5729 u8 reserved_at_18[0x3]; 5730 u8 length[0x5]; 5731 5732 u8 data[0x20]; 5733 }; 5734 5735 struct mlx5_ifc_add_action_in_bits { 5736 u8 action_type[0x4]; 5737 u8 field[0xc]; 5738 u8 reserved_at_10[0x10]; 5739 5740 u8 data[0x20]; 5741 }; 5742 5743 struct mlx5_ifc_copy_action_in_bits { 5744 u8 action_type[0x4]; 5745 u8 src_field[0xc]; 5746 u8 reserved_at_10[0x3]; 5747 u8 src_offset[0x5]; 5748 u8 reserved_at_18[0x3]; 5749 u8 length[0x5]; 5750 5751 u8 reserved_at_20[0x4]; 5752 u8 dst_field[0xc]; 5753 u8 reserved_at_30[0x3]; 5754 u8 dst_offset[0x5]; 5755 u8 reserved_at_38[0x8]; 5756 }; 5757 5758 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5759 struct mlx5_ifc_set_action_in_bits set_action_in; 5760 struct mlx5_ifc_add_action_in_bits add_action_in; 5761 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5762 u8 reserved_at_0[0x40]; 5763 }; 5764 5765 enum { 5766 MLX5_ACTION_TYPE_SET = 0x1, 5767 MLX5_ACTION_TYPE_ADD = 0x2, 5768 MLX5_ACTION_TYPE_COPY = 0x3, 5769 }; 5770 5771 enum { 5772 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5773 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5774 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5775 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5776 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5777 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5778 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5779 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5780 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5781 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5782 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5783 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5784 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5785 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5786 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5787 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5788 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5789 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5790 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5791 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5792 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5793 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5794 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5795 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5796 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5797 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5798 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5799 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5800 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5801 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5802 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5803 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5804 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5805 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5806 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5807 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5808 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5809 }; 5810 5811 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5812 u8 status[0x8]; 5813 u8 reserved_at_8[0x18]; 5814 5815 u8 syndrome[0x20]; 5816 5817 u8 modify_header_id[0x20]; 5818 5819 u8 reserved_at_60[0x20]; 5820 }; 5821 5822 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5823 u8 opcode[0x10]; 5824 u8 reserved_at_10[0x10]; 5825 5826 u8 reserved_at_20[0x10]; 5827 u8 op_mod[0x10]; 5828 5829 u8 reserved_at_40[0x20]; 5830 5831 u8 table_type[0x8]; 5832 u8 reserved_at_68[0x10]; 5833 u8 num_of_actions[0x8]; 5834 5835 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5836 }; 5837 5838 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5839 u8 status[0x8]; 5840 u8 reserved_at_8[0x18]; 5841 5842 u8 syndrome[0x20]; 5843 5844 u8 reserved_at_40[0x40]; 5845 }; 5846 5847 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_at_10[0x10]; 5850 5851 u8 reserved_at_20[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 modify_header_id[0x20]; 5855 5856 u8 reserved_at_60[0x20]; 5857 }; 5858 5859 struct mlx5_ifc_query_dct_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x40]; 5866 5867 struct mlx5_ifc_dctc_bits dct_context_entry; 5868 5869 u8 reserved_at_280[0x180]; 5870 }; 5871 5872 struct mlx5_ifc_query_dct_in_bits { 5873 u8 opcode[0x10]; 5874 u8 reserved_at_10[0x10]; 5875 5876 u8 reserved_at_20[0x10]; 5877 u8 op_mod[0x10]; 5878 5879 u8 reserved_at_40[0x8]; 5880 u8 dctn[0x18]; 5881 5882 u8 reserved_at_60[0x20]; 5883 }; 5884 5885 struct mlx5_ifc_query_cq_out_bits { 5886 u8 status[0x8]; 5887 u8 reserved_at_8[0x18]; 5888 5889 u8 syndrome[0x20]; 5890 5891 u8 reserved_at_40[0x40]; 5892 5893 struct mlx5_ifc_cqc_bits cq_context; 5894 5895 u8 reserved_at_280[0x600]; 5896 5897 u8 pas[][0x40]; 5898 }; 5899 5900 struct mlx5_ifc_query_cq_in_bits { 5901 u8 opcode[0x10]; 5902 u8 reserved_at_10[0x10]; 5903 5904 u8 reserved_at_20[0x10]; 5905 u8 op_mod[0x10]; 5906 5907 u8 reserved_at_40[0x8]; 5908 u8 cqn[0x18]; 5909 5910 u8 reserved_at_60[0x20]; 5911 }; 5912 5913 struct mlx5_ifc_query_cong_status_out_bits { 5914 u8 status[0x8]; 5915 u8 reserved_at_8[0x18]; 5916 5917 u8 syndrome[0x20]; 5918 5919 u8 reserved_at_40[0x20]; 5920 5921 u8 enable[0x1]; 5922 u8 tag_enable[0x1]; 5923 u8 reserved_at_62[0x1e]; 5924 }; 5925 5926 struct mlx5_ifc_query_cong_status_in_bits { 5927 u8 opcode[0x10]; 5928 u8 reserved_at_10[0x10]; 5929 5930 u8 reserved_at_20[0x10]; 5931 u8 op_mod[0x10]; 5932 5933 u8 reserved_at_40[0x18]; 5934 u8 priority[0x4]; 5935 u8 cong_protocol[0x4]; 5936 5937 u8 reserved_at_60[0x20]; 5938 }; 5939 5940 struct mlx5_ifc_query_cong_statistics_out_bits { 5941 u8 status[0x8]; 5942 u8 reserved_at_8[0x18]; 5943 5944 u8 syndrome[0x20]; 5945 5946 u8 reserved_at_40[0x40]; 5947 5948 u8 rp_cur_flows[0x20]; 5949 5950 u8 sum_flows[0x20]; 5951 5952 u8 rp_cnp_ignored_high[0x20]; 5953 5954 u8 rp_cnp_ignored_low[0x20]; 5955 5956 u8 rp_cnp_handled_high[0x20]; 5957 5958 u8 rp_cnp_handled_low[0x20]; 5959 5960 u8 reserved_at_140[0x100]; 5961 5962 u8 time_stamp_high[0x20]; 5963 5964 u8 time_stamp_low[0x20]; 5965 5966 u8 accumulators_period[0x20]; 5967 5968 u8 np_ecn_marked_roce_packets_high[0x20]; 5969 5970 u8 np_ecn_marked_roce_packets_low[0x20]; 5971 5972 u8 np_cnp_sent_high[0x20]; 5973 5974 u8 np_cnp_sent_low[0x20]; 5975 5976 u8 reserved_at_320[0x560]; 5977 }; 5978 5979 struct mlx5_ifc_query_cong_statistics_in_bits { 5980 u8 opcode[0x10]; 5981 u8 reserved_at_10[0x10]; 5982 5983 u8 reserved_at_20[0x10]; 5984 u8 op_mod[0x10]; 5985 5986 u8 clear[0x1]; 5987 u8 reserved_at_41[0x1f]; 5988 5989 u8 reserved_at_60[0x20]; 5990 }; 5991 5992 struct mlx5_ifc_query_cong_params_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x40]; 5999 6000 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6001 }; 6002 6003 struct mlx5_ifc_query_cong_params_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x1c]; 6011 u8 cong_protocol[0x4]; 6012 6013 u8 reserved_at_60[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_query_adapter_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x40]; 6023 6024 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6025 }; 6026 6027 struct mlx5_ifc_query_adapter_in_bits { 6028 u8 opcode[0x10]; 6029 u8 reserved_at_10[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x40]; 6035 }; 6036 6037 struct mlx5_ifc_qp_2rst_out_bits { 6038 u8 status[0x8]; 6039 u8 reserved_at_8[0x18]; 6040 6041 u8 syndrome[0x20]; 6042 6043 u8 reserved_at_40[0x40]; 6044 }; 6045 6046 struct mlx5_ifc_qp_2rst_in_bits { 6047 u8 opcode[0x10]; 6048 u8 uid[0x10]; 6049 6050 u8 reserved_at_20[0x10]; 6051 u8 op_mod[0x10]; 6052 6053 u8 reserved_at_40[0x8]; 6054 u8 qpn[0x18]; 6055 6056 u8 reserved_at_60[0x20]; 6057 }; 6058 6059 struct mlx5_ifc_qp_2err_out_bits { 6060 u8 status[0x8]; 6061 u8 reserved_at_8[0x18]; 6062 6063 u8 syndrome[0x20]; 6064 6065 u8 reserved_at_40[0x40]; 6066 }; 6067 6068 struct mlx5_ifc_qp_2err_in_bits { 6069 u8 opcode[0x10]; 6070 u8 uid[0x10]; 6071 6072 u8 reserved_at_20[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 reserved_at_40[0x8]; 6076 u8 qpn[0x18]; 6077 6078 u8 reserved_at_60[0x20]; 6079 }; 6080 6081 struct mlx5_ifc_page_fault_resume_out_bits { 6082 u8 status[0x8]; 6083 u8 reserved_at_8[0x18]; 6084 6085 u8 syndrome[0x20]; 6086 6087 u8 reserved_at_40[0x40]; 6088 }; 6089 6090 struct mlx5_ifc_page_fault_resume_in_bits { 6091 u8 opcode[0x10]; 6092 u8 reserved_at_10[0x10]; 6093 6094 u8 reserved_at_20[0x10]; 6095 u8 op_mod[0x10]; 6096 6097 u8 error[0x1]; 6098 u8 reserved_at_41[0x4]; 6099 u8 page_fault_type[0x3]; 6100 u8 wq_number[0x18]; 6101 6102 u8 reserved_at_60[0x8]; 6103 u8 token[0x18]; 6104 }; 6105 6106 struct mlx5_ifc_nop_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_nop_in_bits { 6116 u8 opcode[0x10]; 6117 u8 reserved_at_10[0x10]; 6118 6119 u8 reserved_at_20[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_at_40[0x40]; 6123 }; 6124 6125 struct mlx5_ifc_modify_vport_state_out_bits { 6126 u8 status[0x8]; 6127 u8 reserved_at_8[0x18]; 6128 6129 u8 syndrome[0x20]; 6130 6131 u8 reserved_at_40[0x40]; 6132 }; 6133 6134 struct mlx5_ifc_modify_vport_state_in_bits { 6135 u8 opcode[0x10]; 6136 u8 reserved_at_10[0x10]; 6137 6138 u8 reserved_at_20[0x10]; 6139 u8 op_mod[0x10]; 6140 6141 u8 other_vport[0x1]; 6142 u8 reserved_at_41[0xf]; 6143 u8 vport_number[0x10]; 6144 6145 u8 reserved_at_60[0x18]; 6146 u8 admin_state[0x4]; 6147 u8 reserved_at_7c[0x4]; 6148 }; 6149 6150 struct mlx5_ifc_modify_tis_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_at_8[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_at_40[0x40]; 6157 }; 6158 6159 struct mlx5_ifc_modify_tis_bitmask_bits { 6160 u8 reserved_at_0[0x20]; 6161 6162 u8 reserved_at_20[0x1d]; 6163 u8 lag_tx_port_affinity[0x1]; 6164 u8 strict_lag_tx_port_affinity[0x1]; 6165 u8 prio[0x1]; 6166 }; 6167 6168 struct mlx5_ifc_modify_tis_in_bits { 6169 u8 opcode[0x10]; 6170 u8 uid[0x10]; 6171 6172 u8 reserved_at_20[0x10]; 6173 u8 op_mod[0x10]; 6174 6175 u8 reserved_at_40[0x8]; 6176 u8 tisn[0x18]; 6177 6178 u8 reserved_at_60[0x20]; 6179 6180 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6181 6182 u8 reserved_at_c0[0x40]; 6183 6184 struct mlx5_ifc_tisc_bits ctx; 6185 }; 6186 6187 struct mlx5_ifc_modify_tir_bitmask_bits { 6188 u8 reserved_at_0[0x20]; 6189 6190 u8 reserved_at_20[0x1b]; 6191 u8 self_lb_en[0x1]; 6192 u8 reserved_at_3c[0x1]; 6193 u8 hash[0x1]; 6194 u8 reserved_at_3e[0x1]; 6195 u8 lro[0x1]; 6196 }; 6197 6198 struct mlx5_ifc_modify_tir_out_bits { 6199 u8 status[0x8]; 6200 u8 reserved_at_8[0x18]; 6201 6202 u8 syndrome[0x20]; 6203 6204 u8 reserved_at_40[0x40]; 6205 }; 6206 6207 struct mlx5_ifc_modify_tir_in_bits { 6208 u8 opcode[0x10]; 6209 u8 uid[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 reserved_at_40[0x8]; 6215 u8 tirn[0x18]; 6216 6217 u8 reserved_at_60[0x20]; 6218 6219 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6220 6221 u8 reserved_at_c0[0x40]; 6222 6223 struct mlx5_ifc_tirc_bits ctx; 6224 }; 6225 6226 struct mlx5_ifc_modify_sq_out_bits { 6227 u8 status[0x8]; 6228 u8 reserved_at_8[0x18]; 6229 6230 u8 syndrome[0x20]; 6231 6232 u8 reserved_at_40[0x40]; 6233 }; 6234 6235 struct mlx5_ifc_modify_sq_in_bits { 6236 u8 opcode[0x10]; 6237 u8 uid[0x10]; 6238 6239 u8 reserved_at_20[0x10]; 6240 u8 op_mod[0x10]; 6241 6242 u8 sq_state[0x4]; 6243 u8 reserved_at_44[0x4]; 6244 u8 sqn[0x18]; 6245 6246 u8 reserved_at_60[0x20]; 6247 6248 u8 modify_bitmask[0x40]; 6249 6250 u8 reserved_at_c0[0x40]; 6251 6252 struct mlx5_ifc_sqc_bits ctx; 6253 }; 6254 6255 struct mlx5_ifc_modify_scheduling_element_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x1c0]; 6262 }; 6263 6264 enum { 6265 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6266 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6267 }; 6268 6269 struct mlx5_ifc_modify_scheduling_element_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 scheduling_hierarchy[0x8]; 6277 u8 reserved_at_48[0x18]; 6278 6279 u8 scheduling_element_id[0x20]; 6280 6281 u8 reserved_at_80[0x20]; 6282 6283 u8 modify_bitmask[0x20]; 6284 6285 u8 reserved_at_c0[0x40]; 6286 6287 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6288 6289 u8 reserved_at_300[0x100]; 6290 }; 6291 6292 struct mlx5_ifc_modify_rqt_out_bits { 6293 u8 status[0x8]; 6294 u8 reserved_at_8[0x18]; 6295 6296 u8 syndrome[0x20]; 6297 6298 u8 reserved_at_40[0x40]; 6299 }; 6300 6301 struct mlx5_ifc_rqt_bitmask_bits { 6302 u8 reserved_at_0[0x20]; 6303 6304 u8 reserved_at_20[0x1f]; 6305 u8 rqn_list[0x1]; 6306 }; 6307 6308 struct mlx5_ifc_modify_rqt_in_bits { 6309 u8 opcode[0x10]; 6310 u8 uid[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x8]; 6316 u8 rqtn[0x18]; 6317 6318 u8 reserved_at_60[0x20]; 6319 6320 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6321 6322 u8 reserved_at_c0[0x40]; 6323 6324 struct mlx5_ifc_rqtc_bits ctx; 6325 }; 6326 6327 struct mlx5_ifc_modify_rq_out_bits { 6328 u8 status[0x8]; 6329 u8 reserved_at_8[0x18]; 6330 6331 u8 syndrome[0x20]; 6332 6333 u8 reserved_at_40[0x40]; 6334 }; 6335 6336 enum { 6337 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6338 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6339 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6340 }; 6341 6342 struct mlx5_ifc_modify_rq_in_bits { 6343 u8 opcode[0x10]; 6344 u8 uid[0x10]; 6345 6346 u8 reserved_at_20[0x10]; 6347 u8 op_mod[0x10]; 6348 6349 u8 rq_state[0x4]; 6350 u8 reserved_at_44[0x4]; 6351 u8 rqn[0x18]; 6352 6353 u8 reserved_at_60[0x20]; 6354 6355 u8 modify_bitmask[0x40]; 6356 6357 u8 reserved_at_c0[0x40]; 6358 6359 struct mlx5_ifc_rqc_bits ctx; 6360 }; 6361 6362 struct mlx5_ifc_modify_rmp_out_bits { 6363 u8 status[0x8]; 6364 u8 reserved_at_8[0x18]; 6365 6366 u8 syndrome[0x20]; 6367 6368 u8 reserved_at_40[0x40]; 6369 }; 6370 6371 struct mlx5_ifc_rmp_bitmask_bits { 6372 u8 reserved_at_0[0x20]; 6373 6374 u8 reserved_at_20[0x1f]; 6375 u8 lwm[0x1]; 6376 }; 6377 6378 struct mlx5_ifc_modify_rmp_in_bits { 6379 u8 opcode[0x10]; 6380 u8 uid[0x10]; 6381 6382 u8 reserved_at_20[0x10]; 6383 u8 op_mod[0x10]; 6384 6385 u8 rmp_state[0x4]; 6386 u8 reserved_at_44[0x4]; 6387 u8 rmpn[0x18]; 6388 6389 u8 reserved_at_60[0x20]; 6390 6391 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6392 6393 u8 reserved_at_c0[0x40]; 6394 6395 struct mlx5_ifc_rmpc_bits ctx; 6396 }; 6397 6398 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6399 u8 status[0x8]; 6400 u8 reserved_at_8[0x18]; 6401 6402 u8 syndrome[0x20]; 6403 6404 u8 reserved_at_40[0x40]; 6405 }; 6406 6407 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6408 u8 reserved_at_0[0x12]; 6409 u8 affiliation[0x1]; 6410 u8 reserved_at_13[0x1]; 6411 u8 disable_uc_local_lb[0x1]; 6412 u8 disable_mc_local_lb[0x1]; 6413 u8 node_guid[0x1]; 6414 u8 port_guid[0x1]; 6415 u8 min_inline[0x1]; 6416 u8 mtu[0x1]; 6417 u8 change_event[0x1]; 6418 u8 promisc[0x1]; 6419 u8 permanent_address[0x1]; 6420 u8 addresses_list[0x1]; 6421 u8 roce_en[0x1]; 6422 u8 reserved_at_1f[0x1]; 6423 }; 6424 6425 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6426 u8 opcode[0x10]; 6427 u8 reserved_at_10[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 other_vport[0x1]; 6433 u8 reserved_at_41[0xf]; 6434 u8 vport_number[0x10]; 6435 6436 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6437 6438 u8 reserved_at_80[0x780]; 6439 6440 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6441 }; 6442 6443 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6444 u8 status[0x8]; 6445 u8 reserved_at_8[0x18]; 6446 6447 u8 syndrome[0x20]; 6448 6449 u8 reserved_at_40[0x40]; 6450 }; 6451 6452 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6453 u8 opcode[0x10]; 6454 u8 reserved_at_10[0x10]; 6455 6456 u8 reserved_at_20[0x10]; 6457 u8 op_mod[0x10]; 6458 6459 u8 other_vport[0x1]; 6460 u8 reserved_at_41[0xb]; 6461 u8 port_num[0x4]; 6462 u8 vport_number[0x10]; 6463 6464 u8 reserved_at_60[0x20]; 6465 6466 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6467 }; 6468 6469 struct mlx5_ifc_modify_cq_out_bits { 6470 u8 status[0x8]; 6471 u8 reserved_at_8[0x18]; 6472 6473 u8 syndrome[0x20]; 6474 6475 u8 reserved_at_40[0x40]; 6476 }; 6477 6478 enum { 6479 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6480 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6481 }; 6482 6483 struct mlx5_ifc_modify_cq_in_bits { 6484 u8 opcode[0x10]; 6485 u8 uid[0x10]; 6486 6487 u8 reserved_at_20[0x10]; 6488 u8 op_mod[0x10]; 6489 6490 u8 reserved_at_40[0x8]; 6491 u8 cqn[0x18]; 6492 6493 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6494 6495 struct mlx5_ifc_cqc_bits cq_context; 6496 6497 u8 reserved_at_280[0x60]; 6498 6499 u8 cq_umem_valid[0x1]; 6500 u8 reserved_at_2e1[0x1f]; 6501 6502 u8 reserved_at_300[0x580]; 6503 6504 u8 pas[][0x40]; 6505 }; 6506 6507 struct mlx5_ifc_modify_cong_status_out_bits { 6508 u8 status[0x8]; 6509 u8 reserved_at_8[0x18]; 6510 6511 u8 syndrome[0x20]; 6512 6513 u8 reserved_at_40[0x40]; 6514 }; 6515 6516 struct mlx5_ifc_modify_cong_status_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 reserved_at_40[0x18]; 6524 u8 priority[0x4]; 6525 u8 cong_protocol[0x4]; 6526 6527 u8 enable[0x1]; 6528 u8 tag_enable[0x1]; 6529 u8 reserved_at_62[0x1e]; 6530 }; 6531 6532 struct mlx5_ifc_modify_cong_params_out_bits { 6533 u8 status[0x8]; 6534 u8 reserved_at_8[0x18]; 6535 6536 u8 syndrome[0x20]; 6537 6538 u8 reserved_at_40[0x40]; 6539 }; 6540 6541 struct mlx5_ifc_modify_cong_params_in_bits { 6542 u8 opcode[0x10]; 6543 u8 reserved_at_10[0x10]; 6544 6545 u8 reserved_at_20[0x10]; 6546 u8 op_mod[0x10]; 6547 6548 u8 reserved_at_40[0x1c]; 6549 u8 cong_protocol[0x4]; 6550 6551 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6552 6553 u8 reserved_at_80[0x80]; 6554 6555 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6556 }; 6557 6558 struct mlx5_ifc_manage_pages_out_bits { 6559 u8 status[0x8]; 6560 u8 reserved_at_8[0x18]; 6561 6562 u8 syndrome[0x20]; 6563 6564 u8 output_num_entries[0x20]; 6565 6566 u8 reserved_at_60[0x20]; 6567 6568 u8 pas[][0x40]; 6569 }; 6570 6571 enum { 6572 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6573 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6574 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6575 }; 6576 6577 struct mlx5_ifc_manage_pages_in_bits { 6578 u8 opcode[0x10]; 6579 u8 reserved_at_10[0x10]; 6580 6581 u8 reserved_at_20[0x10]; 6582 u8 op_mod[0x10]; 6583 6584 u8 embedded_cpu_function[0x1]; 6585 u8 reserved_at_41[0xf]; 6586 u8 function_id[0x10]; 6587 6588 u8 input_num_entries[0x20]; 6589 6590 u8 pas[][0x40]; 6591 }; 6592 6593 struct mlx5_ifc_mad_ifc_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x40]; 6600 6601 u8 response_mad_packet[256][0x8]; 6602 }; 6603 6604 struct mlx5_ifc_mad_ifc_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 remote_lid[0x10]; 6612 u8 reserved_at_50[0x8]; 6613 u8 port[0x8]; 6614 6615 u8 reserved_at_60[0x20]; 6616 6617 u8 mad[256][0x8]; 6618 }; 6619 6620 struct mlx5_ifc_init_hca_out_bits { 6621 u8 status[0x8]; 6622 u8 reserved_at_8[0x18]; 6623 6624 u8 syndrome[0x20]; 6625 6626 u8 reserved_at_40[0x40]; 6627 }; 6628 6629 struct mlx5_ifc_init_hca_in_bits { 6630 u8 opcode[0x10]; 6631 u8 reserved_at_10[0x10]; 6632 6633 u8 reserved_at_20[0x10]; 6634 u8 op_mod[0x10]; 6635 6636 u8 reserved_at_40[0x40]; 6637 u8 sw_owner_id[4][0x20]; 6638 }; 6639 6640 struct mlx5_ifc_init2rtr_qp_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_at_8[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_at_40[0x20]; 6647 u8 ece[0x20]; 6648 }; 6649 6650 struct mlx5_ifc_init2rtr_qp_in_bits { 6651 u8 opcode[0x10]; 6652 u8 uid[0x10]; 6653 6654 u8 reserved_at_20[0x10]; 6655 u8 op_mod[0x10]; 6656 6657 u8 reserved_at_40[0x8]; 6658 u8 qpn[0x18]; 6659 6660 u8 reserved_at_60[0x20]; 6661 6662 u8 opt_param_mask[0x20]; 6663 6664 u8 ece[0x20]; 6665 6666 struct mlx5_ifc_qpc_bits qpc; 6667 6668 u8 reserved_at_800[0x80]; 6669 }; 6670 6671 struct mlx5_ifc_init2init_qp_out_bits { 6672 u8 status[0x8]; 6673 u8 reserved_at_8[0x18]; 6674 6675 u8 syndrome[0x20]; 6676 6677 u8 reserved_at_40[0x20]; 6678 u8 ece[0x20]; 6679 }; 6680 6681 struct mlx5_ifc_init2init_qp_in_bits { 6682 u8 opcode[0x10]; 6683 u8 uid[0x10]; 6684 6685 u8 reserved_at_20[0x10]; 6686 u8 op_mod[0x10]; 6687 6688 u8 reserved_at_40[0x8]; 6689 u8 qpn[0x18]; 6690 6691 u8 reserved_at_60[0x20]; 6692 6693 u8 opt_param_mask[0x20]; 6694 6695 u8 ece[0x20]; 6696 6697 struct mlx5_ifc_qpc_bits qpc; 6698 6699 u8 reserved_at_800[0x80]; 6700 }; 6701 6702 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6703 u8 status[0x8]; 6704 u8 reserved_at_8[0x18]; 6705 6706 u8 syndrome[0x20]; 6707 6708 u8 reserved_at_40[0x40]; 6709 6710 u8 packet_headers_log[128][0x8]; 6711 6712 u8 packet_syndrome[64][0x8]; 6713 }; 6714 6715 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6716 u8 opcode[0x10]; 6717 u8 reserved_at_10[0x10]; 6718 6719 u8 reserved_at_20[0x10]; 6720 u8 op_mod[0x10]; 6721 6722 u8 reserved_at_40[0x40]; 6723 }; 6724 6725 struct mlx5_ifc_gen_eqe_in_bits { 6726 u8 opcode[0x10]; 6727 u8 reserved_at_10[0x10]; 6728 6729 u8 reserved_at_20[0x10]; 6730 u8 op_mod[0x10]; 6731 6732 u8 reserved_at_40[0x18]; 6733 u8 eq_number[0x8]; 6734 6735 u8 reserved_at_60[0x20]; 6736 6737 u8 eqe[64][0x8]; 6738 }; 6739 6740 struct mlx5_ifc_gen_eq_out_bits { 6741 u8 status[0x8]; 6742 u8 reserved_at_8[0x18]; 6743 6744 u8 syndrome[0x20]; 6745 6746 u8 reserved_at_40[0x40]; 6747 }; 6748 6749 struct mlx5_ifc_enable_hca_out_bits { 6750 u8 status[0x8]; 6751 u8 reserved_at_8[0x18]; 6752 6753 u8 syndrome[0x20]; 6754 6755 u8 reserved_at_40[0x20]; 6756 }; 6757 6758 struct mlx5_ifc_enable_hca_in_bits { 6759 u8 opcode[0x10]; 6760 u8 reserved_at_10[0x10]; 6761 6762 u8 reserved_at_20[0x10]; 6763 u8 op_mod[0x10]; 6764 6765 u8 embedded_cpu_function[0x1]; 6766 u8 reserved_at_41[0xf]; 6767 u8 function_id[0x10]; 6768 6769 u8 reserved_at_60[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_drain_dct_out_bits { 6773 u8 status[0x8]; 6774 u8 reserved_at_8[0x18]; 6775 6776 u8 syndrome[0x20]; 6777 6778 u8 reserved_at_40[0x40]; 6779 }; 6780 6781 struct mlx5_ifc_drain_dct_in_bits { 6782 u8 opcode[0x10]; 6783 u8 uid[0x10]; 6784 6785 u8 reserved_at_20[0x10]; 6786 u8 op_mod[0x10]; 6787 6788 u8 reserved_at_40[0x8]; 6789 u8 dctn[0x18]; 6790 6791 u8 reserved_at_60[0x20]; 6792 }; 6793 6794 struct mlx5_ifc_disable_hca_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x20]; 6801 }; 6802 6803 struct mlx5_ifc_disable_hca_in_bits { 6804 u8 opcode[0x10]; 6805 u8 reserved_at_10[0x10]; 6806 6807 u8 reserved_at_20[0x10]; 6808 u8 op_mod[0x10]; 6809 6810 u8 embedded_cpu_function[0x1]; 6811 u8 reserved_at_41[0xf]; 6812 u8 function_id[0x10]; 6813 6814 u8 reserved_at_60[0x20]; 6815 }; 6816 6817 struct mlx5_ifc_detach_from_mcg_out_bits { 6818 u8 status[0x8]; 6819 u8 reserved_at_8[0x18]; 6820 6821 u8 syndrome[0x20]; 6822 6823 u8 reserved_at_40[0x40]; 6824 }; 6825 6826 struct mlx5_ifc_detach_from_mcg_in_bits { 6827 u8 opcode[0x10]; 6828 u8 uid[0x10]; 6829 6830 u8 reserved_at_20[0x10]; 6831 u8 op_mod[0x10]; 6832 6833 u8 reserved_at_40[0x8]; 6834 u8 qpn[0x18]; 6835 6836 u8 reserved_at_60[0x20]; 6837 6838 u8 multicast_gid[16][0x8]; 6839 }; 6840 6841 struct mlx5_ifc_destroy_xrq_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x40]; 6848 }; 6849 6850 struct mlx5_ifc_destroy_xrq_in_bits { 6851 u8 opcode[0x10]; 6852 u8 uid[0x10]; 6853 6854 u8 reserved_at_20[0x10]; 6855 u8 op_mod[0x10]; 6856 6857 u8 reserved_at_40[0x8]; 6858 u8 xrqn[0x18]; 6859 6860 u8 reserved_at_60[0x20]; 6861 }; 6862 6863 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6864 u8 status[0x8]; 6865 u8 reserved_at_8[0x18]; 6866 6867 u8 syndrome[0x20]; 6868 6869 u8 reserved_at_40[0x40]; 6870 }; 6871 6872 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6873 u8 opcode[0x10]; 6874 u8 uid[0x10]; 6875 6876 u8 reserved_at_20[0x10]; 6877 u8 op_mod[0x10]; 6878 6879 u8 reserved_at_40[0x8]; 6880 u8 xrc_srqn[0x18]; 6881 6882 u8 reserved_at_60[0x20]; 6883 }; 6884 6885 struct mlx5_ifc_destroy_tis_out_bits { 6886 u8 status[0x8]; 6887 u8 reserved_at_8[0x18]; 6888 6889 u8 syndrome[0x20]; 6890 6891 u8 reserved_at_40[0x40]; 6892 }; 6893 6894 struct mlx5_ifc_destroy_tis_in_bits { 6895 u8 opcode[0x10]; 6896 u8 uid[0x10]; 6897 6898 u8 reserved_at_20[0x10]; 6899 u8 op_mod[0x10]; 6900 6901 u8 reserved_at_40[0x8]; 6902 u8 tisn[0x18]; 6903 6904 u8 reserved_at_60[0x20]; 6905 }; 6906 6907 struct mlx5_ifc_destroy_tir_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x40]; 6914 }; 6915 6916 struct mlx5_ifc_destroy_tir_in_bits { 6917 u8 opcode[0x10]; 6918 u8 uid[0x10]; 6919 6920 u8 reserved_at_20[0x10]; 6921 u8 op_mod[0x10]; 6922 6923 u8 reserved_at_40[0x8]; 6924 u8 tirn[0x18]; 6925 6926 u8 reserved_at_60[0x20]; 6927 }; 6928 6929 struct mlx5_ifc_destroy_srq_out_bits { 6930 u8 status[0x8]; 6931 u8 reserved_at_8[0x18]; 6932 6933 u8 syndrome[0x20]; 6934 6935 u8 reserved_at_40[0x40]; 6936 }; 6937 6938 struct mlx5_ifc_destroy_srq_in_bits { 6939 u8 opcode[0x10]; 6940 u8 uid[0x10]; 6941 6942 u8 reserved_at_20[0x10]; 6943 u8 op_mod[0x10]; 6944 6945 u8 reserved_at_40[0x8]; 6946 u8 srqn[0x18]; 6947 6948 u8 reserved_at_60[0x20]; 6949 }; 6950 6951 struct mlx5_ifc_destroy_sq_out_bits { 6952 u8 status[0x8]; 6953 u8 reserved_at_8[0x18]; 6954 6955 u8 syndrome[0x20]; 6956 6957 u8 reserved_at_40[0x40]; 6958 }; 6959 6960 struct mlx5_ifc_destroy_sq_in_bits { 6961 u8 opcode[0x10]; 6962 u8 uid[0x10]; 6963 6964 u8 reserved_at_20[0x10]; 6965 u8 op_mod[0x10]; 6966 6967 u8 reserved_at_40[0x8]; 6968 u8 sqn[0x18]; 6969 6970 u8 reserved_at_60[0x20]; 6971 }; 6972 6973 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6974 u8 status[0x8]; 6975 u8 reserved_at_8[0x18]; 6976 6977 u8 syndrome[0x20]; 6978 6979 u8 reserved_at_40[0x1c0]; 6980 }; 6981 6982 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6983 u8 opcode[0x10]; 6984 u8 reserved_at_10[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 scheduling_hierarchy[0x8]; 6990 u8 reserved_at_48[0x18]; 6991 6992 u8 scheduling_element_id[0x20]; 6993 6994 u8 reserved_at_80[0x180]; 6995 }; 6996 6997 struct mlx5_ifc_destroy_rqt_out_bits { 6998 u8 status[0x8]; 6999 u8 reserved_at_8[0x18]; 7000 7001 u8 syndrome[0x20]; 7002 7003 u8 reserved_at_40[0x40]; 7004 }; 7005 7006 struct mlx5_ifc_destroy_rqt_in_bits { 7007 u8 opcode[0x10]; 7008 u8 uid[0x10]; 7009 7010 u8 reserved_at_20[0x10]; 7011 u8 op_mod[0x10]; 7012 7013 u8 reserved_at_40[0x8]; 7014 u8 rqtn[0x18]; 7015 7016 u8 reserved_at_60[0x20]; 7017 }; 7018 7019 struct mlx5_ifc_destroy_rq_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_at_8[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_at_40[0x40]; 7026 }; 7027 7028 struct mlx5_ifc_destroy_rq_in_bits { 7029 u8 opcode[0x10]; 7030 u8 uid[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 reserved_at_40[0x8]; 7036 u8 rqn[0x18]; 7037 7038 u8 reserved_at_60[0x20]; 7039 }; 7040 7041 struct mlx5_ifc_set_delay_drop_params_in_bits { 7042 u8 opcode[0x10]; 7043 u8 reserved_at_10[0x10]; 7044 7045 u8 reserved_at_20[0x10]; 7046 u8 op_mod[0x10]; 7047 7048 u8 reserved_at_40[0x20]; 7049 7050 u8 reserved_at_60[0x10]; 7051 u8 delay_drop_timeout[0x10]; 7052 }; 7053 7054 struct mlx5_ifc_set_delay_drop_params_out_bits { 7055 u8 status[0x8]; 7056 u8 reserved_at_8[0x18]; 7057 7058 u8 syndrome[0x20]; 7059 7060 u8 reserved_at_40[0x40]; 7061 }; 7062 7063 struct mlx5_ifc_destroy_rmp_out_bits { 7064 u8 status[0x8]; 7065 u8 reserved_at_8[0x18]; 7066 7067 u8 syndrome[0x20]; 7068 7069 u8 reserved_at_40[0x40]; 7070 }; 7071 7072 struct mlx5_ifc_destroy_rmp_in_bits { 7073 u8 opcode[0x10]; 7074 u8 uid[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 reserved_at_40[0x8]; 7080 u8 rmpn[0x18]; 7081 7082 u8 reserved_at_60[0x20]; 7083 }; 7084 7085 struct mlx5_ifc_destroy_qp_out_bits { 7086 u8 status[0x8]; 7087 u8 reserved_at_8[0x18]; 7088 7089 u8 syndrome[0x20]; 7090 7091 u8 reserved_at_40[0x40]; 7092 }; 7093 7094 struct mlx5_ifc_destroy_qp_in_bits { 7095 u8 opcode[0x10]; 7096 u8 uid[0x10]; 7097 7098 u8 reserved_at_20[0x10]; 7099 u8 op_mod[0x10]; 7100 7101 u8 reserved_at_40[0x8]; 7102 u8 qpn[0x18]; 7103 7104 u8 reserved_at_60[0x20]; 7105 }; 7106 7107 struct mlx5_ifc_destroy_psv_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 reserved_at_40[0x40]; 7114 }; 7115 7116 struct mlx5_ifc_destroy_psv_in_bits { 7117 u8 opcode[0x10]; 7118 u8 reserved_at_10[0x10]; 7119 7120 u8 reserved_at_20[0x10]; 7121 u8 op_mod[0x10]; 7122 7123 u8 reserved_at_40[0x8]; 7124 u8 psvn[0x18]; 7125 7126 u8 reserved_at_60[0x20]; 7127 }; 7128 7129 struct mlx5_ifc_destroy_mkey_out_bits { 7130 u8 status[0x8]; 7131 u8 reserved_at_8[0x18]; 7132 7133 u8 syndrome[0x20]; 7134 7135 u8 reserved_at_40[0x40]; 7136 }; 7137 7138 struct mlx5_ifc_destroy_mkey_in_bits { 7139 u8 opcode[0x10]; 7140 u8 uid[0x10]; 7141 7142 u8 reserved_at_20[0x10]; 7143 u8 op_mod[0x10]; 7144 7145 u8 reserved_at_40[0x8]; 7146 u8 mkey_index[0x18]; 7147 7148 u8 reserved_at_60[0x20]; 7149 }; 7150 7151 struct mlx5_ifc_destroy_flow_table_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_at_8[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_at_40[0x40]; 7158 }; 7159 7160 struct mlx5_ifc_destroy_flow_table_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 other_vport[0x1]; 7168 u8 reserved_at_41[0xf]; 7169 u8 vport_number[0x10]; 7170 7171 u8 reserved_at_60[0x20]; 7172 7173 u8 table_type[0x8]; 7174 u8 reserved_at_88[0x18]; 7175 7176 u8 reserved_at_a0[0x8]; 7177 u8 table_id[0x18]; 7178 7179 u8 reserved_at_c0[0x140]; 7180 }; 7181 7182 struct mlx5_ifc_destroy_flow_group_out_bits { 7183 u8 status[0x8]; 7184 u8 reserved_at_8[0x18]; 7185 7186 u8 syndrome[0x20]; 7187 7188 u8 reserved_at_40[0x40]; 7189 }; 7190 7191 struct mlx5_ifc_destroy_flow_group_in_bits { 7192 u8 opcode[0x10]; 7193 u8 reserved_at_10[0x10]; 7194 7195 u8 reserved_at_20[0x10]; 7196 u8 op_mod[0x10]; 7197 7198 u8 other_vport[0x1]; 7199 u8 reserved_at_41[0xf]; 7200 u8 vport_number[0x10]; 7201 7202 u8 reserved_at_60[0x20]; 7203 7204 u8 table_type[0x8]; 7205 u8 reserved_at_88[0x18]; 7206 7207 u8 reserved_at_a0[0x8]; 7208 u8 table_id[0x18]; 7209 7210 u8 group_id[0x20]; 7211 7212 u8 reserved_at_e0[0x120]; 7213 }; 7214 7215 struct mlx5_ifc_destroy_eq_out_bits { 7216 u8 status[0x8]; 7217 u8 reserved_at_8[0x18]; 7218 7219 u8 syndrome[0x20]; 7220 7221 u8 reserved_at_40[0x40]; 7222 }; 7223 7224 struct mlx5_ifc_destroy_eq_in_bits { 7225 u8 opcode[0x10]; 7226 u8 reserved_at_10[0x10]; 7227 7228 u8 reserved_at_20[0x10]; 7229 u8 op_mod[0x10]; 7230 7231 u8 reserved_at_40[0x18]; 7232 u8 eq_number[0x8]; 7233 7234 u8 reserved_at_60[0x20]; 7235 }; 7236 7237 struct mlx5_ifc_destroy_dct_out_bits { 7238 u8 status[0x8]; 7239 u8 reserved_at_8[0x18]; 7240 7241 u8 syndrome[0x20]; 7242 7243 u8 reserved_at_40[0x40]; 7244 }; 7245 7246 struct mlx5_ifc_destroy_dct_in_bits { 7247 u8 opcode[0x10]; 7248 u8 uid[0x10]; 7249 7250 u8 reserved_at_20[0x10]; 7251 u8 op_mod[0x10]; 7252 7253 u8 reserved_at_40[0x8]; 7254 u8 dctn[0x18]; 7255 7256 u8 reserved_at_60[0x20]; 7257 }; 7258 7259 struct mlx5_ifc_destroy_cq_out_bits { 7260 u8 status[0x8]; 7261 u8 reserved_at_8[0x18]; 7262 7263 u8 syndrome[0x20]; 7264 7265 u8 reserved_at_40[0x40]; 7266 }; 7267 7268 struct mlx5_ifc_destroy_cq_in_bits { 7269 u8 opcode[0x10]; 7270 u8 uid[0x10]; 7271 7272 u8 reserved_at_20[0x10]; 7273 u8 op_mod[0x10]; 7274 7275 u8 reserved_at_40[0x8]; 7276 u8 cqn[0x18]; 7277 7278 u8 reserved_at_60[0x20]; 7279 }; 7280 7281 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7282 u8 status[0x8]; 7283 u8 reserved_at_8[0x18]; 7284 7285 u8 syndrome[0x20]; 7286 7287 u8 reserved_at_40[0x40]; 7288 }; 7289 7290 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7291 u8 opcode[0x10]; 7292 u8 reserved_at_10[0x10]; 7293 7294 u8 reserved_at_20[0x10]; 7295 u8 op_mod[0x10]; 7296 7297 u8 reserved_at_40[0x20]; 7298 7299 u8 reserved_at_60[0x10]; 7300 u8 vxlan_udp_port[0x10]; 7301 }; 7302 7303 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_at_8[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_at_40[0x40]; 7310 }; 7311 7312 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7313 u8 opcode[0x10]; 7314 u8 reserved_at_10[0x10]; 7315 7316 u8 reserved_at_20[0x10]; 7317 u8 op_mod[0x10]; 7318 7319 u8 reserved_at_40[0x60]; 7320 7321 u8 reserved_at_a0[0x8]; 7322 u8 table_index[0x18]; 7323 7324 u8 reserved_at_c0[0x140]; 7325 }; 7326 7327 struct mlx5_ifc_delete_fte_out_bits { 7328 u8 status[0x8]; 7329 u8 reserved_at_8[0x18]; 7330 7331 u8 syndrome[0x20]; 7332 7333 u8 reserved_at_40[0x40]; 7334 }; 7335 7336 struct mlx5_ifc_delete_fte_in_bits { 7337 u8 opcode[0x10]; 7338 u8 reserved_at_10[0x10]; 7339 7340 u8 reserved_at_20[0x10]; 7341 u8 op_mod[0x10]; 7342 7343 u8 other_vport[0x1]; 7344 u8 reserved_at_41[0xf]; 7345 u8 vport_number[0x10]; 7346 7347 u8 reserved_at_60[0x20]; 7348 7349 u8 table_type[0x8]; 7350 u8 reserved_at_88[0x18]; 7351 7352 u8 reserved_at_a0[0x8]; 7353 u8 table_id[0x18]; 7354 7355 u8 reserved_at_c0[0x40]; 7356 7357 u8 flow_index[0x20]; 7358 7359 u8 reserved_at_120[0xe0]; 7360 }; 7361 7362 struct mlx5_ifc_dealloc_xrcd_out_bits { 7363 u8 status[0x8]; 7364 u8 reserved_at_8[0x18]; 7365 7366 u8 syndrome[0x20]; 7367 7368 u8 reserved_at_40[0x40]; 7369 }; 7370 7371 struct mlx5_ifc_dealloc_xrcd_in_bits { 7372 u8 opcode[0x10]; 7373 u8 uid[0x10]; 7374 7375 u8 reserved_at_20[0x10]; 7376 u8 op_mod[0x10]; 7377 7378 u8 reserved_at_40[0x8]; 7379 u8 xrcd[0x18]; 7380 7381 u8 reserved_at_60[0x20]; 7382 }; 7383 7384 struct mlx5_ifc_dealloc_uar_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x40]; 7391 }; 7392 7393 struct mlx5_ifc_dealloc_uar_in_bits { 7394 u8 opcode[0x10]; 7395 u8 reserved_at_10[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 reserved_at_40[0x8]; 7401 u8 uar[0x18]; 7402 7403 u8 reserved_at_60[0x20]; 7404 }; 7405 7406 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_at_8[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_at_40[0x40]; 7413 }; 7414 7415 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7416 u8 opcode[0x10]; 7417 u8 uid[0x10]; 7418 7419 u8 reserved_at_20[0x10]; 7420 u8 op_mod[0x10]; 7421 7422 u8 reserved_at_40[0x8]; 7423 u8 transport_domain[0x18]; 7424 7425 u8 reserved_at_60[0x20]; 7426 }; 7427 7428 struct mlx5_ifc_dealloc_q_counter_out_bits { 7429 u8 status[0x8]; 7430 u8 reserved_at_8[0x18]; 7431 7432 u8 syndrome[0x20]; 7433 7434 u8 reserved_at_40[0x40]; 7435 }; 7436 7437 struct mlx5_ifc_dealloc_q_counter_in_bits { 7438 u8 opcode[0x10]; 7439 u8 reserved_at_10[0x10]; 7440 7441 u8 reserved_at_20[0x10]; 7442 u8 op_mod[0x10]; 7443 7444 u8 reserved_at_40[0x18]; 7445 u8 counter_set_id[0x8]; 7446 7447 u8 reserved_at_60[0x20]; 7448 }; 7449 7450 struct mlx5_ifc_dealloc_pd_out_bits { 7451 u8 status[0x8]; 7452 u8 reserved_at_8[0x18]; 7453 7454 u8 syndrome[0x20]; 7455 7456 u8 reserved_at_40[0x40]; 7457 }; 7458 7459 struct mlx5_ifc_dealloc_pd_in_bits { 7460 u8 opcode[0x10]; 7461 u8 uid[0x10]; 7462 7463 u8 reserved_at_20[0x10]; 7464 u8 op_mod[0x10]; 7465 7466 u8 reserved_at_40[0x8]; 7467 u8 pd[0x18]; 7468 7469 u8 reserved_at_60[0x20]; 7470 }; 7471 7472 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7473 u8 status[0x8]; 7474 u8 reserved_at_8[0x18]; 7475 7476 u8 syndrome[0x20]; 7477 7478 u8 reserved_at_40[0x40]; 7479 }; 7480 7481 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7482 u8 opcode[0x10]; 7483 u8 reserved_at_10[0x10]; 7484 7485 u8 reserved_at_20[0x10]; 7486 u8 op_mod[0x10]; 7487 7488 u8 flow_counter_id[0x20]; 7489 7490 u8 reserved_at_60[0x20]; 7491 }; 7492 7493 struct mlx5_ifc_create_xrq_out_bits { 7494 u8 status[0x8]; 7495 u8 reserved_at_8[0x18]; 7496 7497 u8 syndrome[0x20]; 7498 7499 u8 reserved_at_40[0x8]; 7500 u8 xrqn[0x18]; 7501 7502 u8 reserved_at_60[0x20]; 7503 }; 7504 7505 struct mlx5_ifc_create_xrq_in_bits { 7506 u8 opcode[0x10]; 7507 u8 uid[0x10]; 7508 7509 u8 reserved_at_20[0x10]; 7510 u8 op_mod[0x10]; 7511 7512 u8 reserved_at_40[0x40]; 7513 7514 struct mlx5_ifc_xrqc_bits xrq_context; 7515 }; 7516 7517 struct mlx5_ifc_create_xrc_srq_out_bits { 7518 u8 status[0x8]; 7519 u8 reserved_at_8[0x18]; 7520 7521 u8 syndrome[0x20]; 7522 7523 u8 reserved_at_40[0x8]; 7524 u8 xrc_srqn[0x18]; 7525 7526 u8 reserved_at_60[0x20]; 7527 }; 7528 7529 struct mlx5_ifc_create_xrc_srq_in_bits { 7530 u8 opcode[0x10]; 7531 u8 uid[0x10]; 7532 7533 u8 reserved_at_20[0x10]; 7534 u8 op_mod[0x10]; 7535 7536 u8 reserved_at_40[0x40]; 7537 7538 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7539 7540 u8 reserved_at_280[0x60]; 7541 7542 u8 xrc_srq_umem_valid[0x1]; 7543 u8 reserved_at_2e1[0x1f]; 7544 7545 u8 reserved_at_300[0x580]; 7546 7547 u8 pas[][0x40]; 7548 }; 7549 7550 struct mlx5_ifc_create_tis_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x8]; 7557 u8 tisn[0x18]; 7558 7559 u8 reserved_at_60[0x20]; 7560 }; 7561 7562 struct mlx5_ifc_create_tis_in_bits { 7563 u8 opcode[0x10]; 7564 u8 uid[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0xc0]; 7570 7571 struct mlx5_ifc_tisc_bits ctx; 7572 }; 7573 7574 struct mlx5_ifc_create_tir_out_bits { 7575 u8 status[0x8]; 7576 u8 icm_address_63_40[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 icm_address_39_32[0x8]; 7581 u8 tirn[0x18]; 7582 7583 u8 icm_address_31_0[0x20]; 7584 }; 7585 7586 struct mlx5_ifc_create_tir_in_bits { 7587 u8 opcode[0x10]; 7588 u8 uid[0x10]; 7589 7590 u8 reserved_at_20[0x10]; 7591 u8 op_mod[0x10]; 7592 7593 u8 reserved_at_40[0xc0]; 7594 7595 struct mlx5_ifc_tirc_bits ctx; 7596 }; 7597 7598 struct mlx5_ifc_create_srq_out_bits { 7599 u8 status[0x8]; 7600 u8 reserved_at_8[0x18]; 7601 7602 u8 syndrome[0x20]; 7603 7604 u8 reserved_at_40[0x8]; 7605 u8 srqn[0x18]; 7606 7607 u8 reserved_at_60[0x20]; 7608 }; 7609 7610 struct mlx5_ifc_create_srq_in_bits { 7611 u8 opcode[0x10]; 7612 u8 uid[0x10]; 7613 7614 u8 reserved_at_20[0x10]; 7615 u8 op_mod[0x10]; 7616 7617 u8 reserved_at_40[0x40]; 7618 7619 struct mlx5_ifc_srqc_bits srq_context_entry; 7620 7621 u8 reserved_at_280[0x600]; 7622 7623 u8 pas[][0x40]; 7624 }; 7625 7626 struct mlx5_ifc_create_sq_out_bits { 7627 u8 status[0x8]; 7628 u8 reserved_at_8[0x18]; 7629 7630 u8 syndrome[0x20]; 7631 7632 u8 reserved_at_40[0x8]; 7633 u8 sqn[0x18]; 7634 7635 u8 reserved_at_60[0x20]; 7636 }; 7637 7638 struct mlx5_ifc_create_sq_in_bits { 7639 u8 opcode[0x10]; 7640 u8 uid[0x10]; 7641 7642 u8 reserved_at_20[0x10]; 7643 u8 op_mod[0x10]; 7644 7645 u8 reserved_at_40[0xc0]; 7646 7647 struct mlx5_ifc_sqc_bits ctx; 7648 }; 7649 7650 struct mlx5_ifc_create_scheduling_element_out_bits { 7651 u8 status[0x8]; 7652 u8 reserved_at_8[0x18]; 7653 7654 u8 syndrome[0x20]; 7655 7656 u8 reserved_at_40[0x40]; 7657 7658 u8 scheduling_element_id[0x20]; 7659 7660 u8 reserved_at_a0[0x160]; 7661 }; 7662 7663 struct mlx5_ifc_create_scheduling_element_in_bits { 7664 u8 opcode[0x10]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 scheduling_hierarchy[0x8]; 7671 u8 reserved_at_48[0x18]; 7672 7673 u8 reserved_at_60[0xa0]; 7674 7675 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7676 7677 u8 reserved_at_300[0x100]; 7678 }; 7679 7680 struct mlx5_ifc_create_rqt_out_bits { 7681 u8 status[0x8]; 7682 u8 reserved_at_8[0x18]; 7683 7684 u8 syndrome[0x20]; 7685 7686 u8 reserved_at_40[0x8]; 7687 u8 rqtn[0x18]; 7688 7689 u8 reserved_at_60[0x20]; 7690 }; 7691 7692 struct mlx5_ifc_create_rqt_in_bits { 7693 u8 opcode[0x10]; 7694 u8 uid[0x10]; 7695 7696 u8 reserved_at_20[0x10]; 7697 u8 op_mod[0x10]; 7698 7699 u8 reserved_at_40[0xc0]; 7700 7701 struct mlx5_ifc_rqtc_bits rqt_context; 7702 }; 7703 7704 struct mlx5_ifc_create_rq_out_bits { 7705 u8 status[0x8]; 7706 u8 reserved_at_8[0x18]; 7707 7708 u8 syndrome[0x20]; 7709 7710 u8 reserved_at_40[0x8]; 7711 u8 rqn[0x18]; 7712 7713 u8 reserved_at_60[0x20]; 7714 }; 7715 7716 struct mlx5_ifc_create_rq_in_bits { 7717 u8 opcode[0x10]; 7718 u8 uid[0x10]; 7719 7720 u8 reserved_at_20[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 u8 reserved_at_40[0xc0]; 7724 7725 struct mlx5_ifc_rqc_bits ctx; 7726 }; 7727 7728 struct mlx5_ifc_create_rmp_out_bits { 7729 u8 status[0x8]; 7730 u8 reserved_at_8[0x18]; 7731 7732 u8 syndrome[0x20]; 7733 7734 u8 reserved_at_40[0x8]; 7735 u8 rmpn[0x18]; 7736 7737 u8 reserved_at_60[0x20]; 7738 }; 7739 7740 struct mlx5_ifc_create_rmp_in_bits { 7741 u8 opcode[0x10]; 7742 u8 uid[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 reserved_at_40[0xc0]; 7748 7749 struct mlx5_ifc_rmpc_bits ctx; 7750 }; 7751 7752 struct mlx5_ifc_create_qp_out_bits { 7753 u8 status[0x8]; 7754 u8 reserved_at_8[0x18]; 7755 7756 u8 syndrome[0x20]; 7757 7758 u8 reserved_at_40[0x8]; 7759 u8 qpn[0x18]; 7760 7761 u8 ece[0x20]; 7762 }; 7763 7764 struct mlx5_ifc_create_qp_in_bits { 7765 u8 opcode[0x10]; 7766 u8 uid[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 reserved_at_40[0x8]; 7772 u8 input_qpn[0x18]; 7773 7774 u8 reserved_at_60[0x20]; 7775 u8 opt_param_mask[0x20]; 7776 7777 u8 ece[0x20]; 7778 7779 struct mlx5_ifc_qpc_bits qpc; 7780 7781 u8 reserved_at_800[0x60]; 7782 7783 u8 wq_umem_valid[0x1]; 7784 u8 reserved_at_861[0x1f]; 7785 7786 u8 pas[][0x40]; 7787 }; 7788 7789 struct mlx5_ifc_create_psv_out_bits { 7790 u8 status[0x8]; 7791 u8 reserved_at_8[0x18]; 7792 7793 u8 syndrome[0x20]; 7794 7795 u8 reserved_at_40[0x40]; 7796 7797 u8 reserved_at_80[0x8]; 7798 u8 psv0_index[0x18]; 7799 7800 u8 reserved_at_a0[0x8]; 7801 u8 psv1_index[0x18]; 7802 7803 u8 reserved_at_c0[0x8]; 7804 u8 psv2_index[0x18]; 7805 7806 u8 reserved_at_e0[0x8]; 7807 u8 psv3_index[0x18]; 7808 }; 7809 7810 struct mlx5_ifc_create_psv_in_bits { 7811 u8 opcode[0x10]; 7812 u8 reserved_at_10[0x10]; 7813 7814 u8 reserved_at_20[0x10]; 7815 u8 op_mod[0x10]; 7816 7817 u8 num_psv[0x4]; 7818 u8 reserved_at_44[0x4]; 7819 u8 pd[0x18]; 7820 7821 u8 reserved_at_60[0x20]; 7822 }; 7823 7824 struct mlx5_ifc_create_mkey_out_bits { 7825 u8 status[0x8]; 7826 u8 reserved_at_8[0x18]; 7827 7828 u8 syndrome[0x20]; 7829 7830 u8 reserved_at_40[0x8]; 7831 u8 mkey_index[0x18]; 7832 7833 u8 reserved_at_60[0x20]; 7834 }; 7835 7836 struct mlx5_ifc_create_mkey_in_bits { 7837 u8 opcode[0x10]; 7838 u8 uid[0x10]; 7839 7840 u8 reserved_at_20[0x10]; 7841 u8 op_mod[0x10]; 7842 7843 u8 reserved_at_40[0x20]; 7844 7845 u8 pg_access[0x1]; 7846 u8 mkey_umem_valid[0x1]; 7847 u8 reserved_at_62[0x1e]; 7848 7849 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7850 7851 u8 reserved_at_280[0x80]; 7852 7853 u8 translations_octword_actual_size[0x20]; 7854 7855 u8 reserved_at_320[0x560]; 7856 7857 u8 klm_pas_mtt[][0x20]; 7858 }; 7859 7860 enum { 7861 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7862 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7863 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7864 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7865 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7866 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7867 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7868 }; 7869 7870 struct mlx5_ifc_create_flow_table_out_bits { 7871 u8 status[0x8]; 7872 u8 icm_address_63_40[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 icm_address_39_32[0x8]; 7877 u8 table_id[0x18]; 7878 7879 u8 icm_address_31_0[0x20]; 7880 }; 7881 7882 struct mlx5_ifc_create_flow_table_in_bits { 7883 u8 opcode[0x10]; 7884 u8 reserved_at_10[0x10]; 7885 7886 u8 reserved_at_20[0x10]; 7887 u8 op_mod[0x10]; 7888 7889 u8 other_vport[0x1]; 7890 u8 reserved_at_41[0xf]; 7891 u8 vport_number[0x10]; 7892 7893 u8 reserved_at_60[0x20]; 7894 7895 u8 table_type[0x8]; 7896 u8 reserved_at_88[0x18]; 7897 7898 u8 reserved_at_a0[0x20]; 7899 7900 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7901 }; 7902 7903 struct mlx5_ifc_create_flow_group_out_bits { 7904 u8 status[0x8]; 7905 u8 reserved_at_8[0x18]; 7906 7907 u8 syndrome[0x20]; 7908 7909 u8 reserved_at_40[0x8]; 7910 u8 group_id[0x18]; 7911 7912 u8 reserved_at_60[0x20]; 7913 }; 7914 7915 enum { 7916 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7917 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7918 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7919 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7920 }; 7921 7922 struct mlx5_ifc_create_flow_group_in_bits { 7923 u8 opcode[0x10]; 7924 u8 reserved_at_10[0x10]; 7925 7926 u8 reserved_at_20[0x10]; 7927 u8 op_mod[0x10]; 7928 7929 u8 other_vport[0x1]; 7930 u8 reserved_at_41[0xf]; 7931 u8 vport_number[0x10]; 7932 7933 u8 reserved_at_60[0x20]; 7934 7935 u8 table_type[0x8]; 7936 u8 reserved_at_88[0x18]; 7937 7938 u8 reserved_at_a0[0x8]; 7939 u8 table_id[0x18]; 7940 7941 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7942 7943 u8 reserved_at_c1[0x1f]; 7944 7945 u8 start_flow_index[0x20]; 7946 7947 u8 reserved_at_100[0x20]; 7948 7949 u8 end_flow_index[0x20]; 7950 7951 u8 reserved_at_140[0xa0]; 7952 7953 u8 reserved_at_1e0[0x18]; 7954 u8 match_criteria_enable[0x8]; 7955 7956 struct mlx5_ifc_fte_match_param_bits match_criteria; 7957 7958 u8 reserved_at_1200[0xe00]; 7959 }; 7960 7961 struct mlx5_ifc_create_eq_out_bits { 7962 u8 status[0x8]; 7963 u8 reserved_at_8[0x18]; 7964 7965 u8 syndrome[0x20]; 7966 7967 u8 reserved_at_40[0x18]; 7968 u8 eq_number[0x8]; 7969 7970 u8 reserved_at_60[0x20]; 7971 }; 7972 7973 struct mlx5_ifc_create_eq_in_bits { 7974 u8 opcode[0x10]; 7975 u8 uid[0x10]; 7976 7977 u8 reserved_at_20[0x10]; 7978 u8 op_mod[0x10]; 7979 7980 u8 reserved_at_40[0x40]; 7981 7982 struct mlx5_ifc_eqc_bits eq_context_entry; 7983 7984 u8 reserved_at_280[0x40]; 7985 7986 u8 event_bitmask[4][0x40]; 7987 7988 u8 reserved_at_3c0[0x4c0]; 7989 7990 u8 pas[][0x40]; 7991 }; 7992 7993 struct mlx5_ifc_create_dct_out_bits { 7994 u8 status[0x8]; 7995 u8 reserved_at_8[0x18]; 7996 7997 u8 syndrome[0x20]; 7998 7999 u8 reserved_at_40[0x8]; 8000 u8 dctn[0x18]; 8001 8002 u8 ece[0x20]; 8003 }; 8004 8005 struct mlx5_ifc_create_dct_in_bits { 8006 u8 opcode[0x10]; 8007 u8 uid[0x10]; 8008 8009 u8 reserved_at_20[0x10]; 8010 u8 op_mod[0x10]; 8011 8012 u8 reserved_at_40[0x40]; 8013 8014 struct mlx5_ifc_dctc_bits dct_context_entry; 8015 8016 u8 reserved_at_280[0x180]; 8017 }; 8018 8019 struct mlx5_ifc_create_cq_out_bits { 8020 u8 status[0x8]; 8021 u8 reserved_at_8[0x18]; 8022 8023 u8 syndrome[0x20]; 8024 8025 u8 reserved_at_40[0x8]; 8026 u8 cqn[0x18]; 8027 8028 u8 reserved_at_60[0x20]; 8029 }; 8030 8031 struct mlx5_ifc_create_cq_in_bits { 8032 u8 opcode[0x10]; 8033 u8 uid[0x10]; 8034 8035 u8 reserved_at_20[0x10]; 8036 u8 op_mod[0x10]; 8037 8038 u8 reserved_at_40[0x40]; 8039 8040 struct mlx5_ifc_cqc_bits cq_context; 8041 8042 u8 reserved_at_280[0x60]; 8043 8044 u8 cq_umem_valid[0x1]; 8045 u8 reserved_at_2e1[0x59f]; 8046 8047 u8 pas[][0x40]; 8048 }; 8049 8050 struct mlx5_ifc_config_int_moderation_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x4]; 8057 u8 min_delay[0xc]; 8058 u8 int_vector[0x10]; 8059 8060 u8 reserved_at_60[0x20]; 8061 }; 8062 8063 enum { 8064 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8065 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8066 }; 8067 8068 struct mlx5_ifc_config_int_moderation_in_bits { 8069 u8 opcode[0x10]; 8070 u8 reserved_at_10[0x10]; 8071 8072 u8 reserved_at_20[0x10]; 8073 u8 op_mod[0x10]; 8074 8075 u8 reserved_at_40[0x4]; 8076 u8 min_delay[0xc]; 8077 u8 int_vector[0x10]; 8078 8079 u8 reserved_at_60[0x20]; 8080 }; 8081 8082 struct mlx5_ifc_attach_to_mcg_out_bits { 8083 u8 status[0x8]; 8084 u8 reserved_at_8[0x18]; 8085 8086 u8 syndrome[0x20]; 8087 8088 u8 reserved_at_40[0x40]; 8089 }; 8090 8091 struct mlx5_ifc_attach_to_mcg_in_bits { 8092 u8 opcode[0x10]; 8093 u8 uid[0x10]; 8094 8095 u8 reserved_at_20[0x10]; 8096 u8 op_mod[0x10]; 8097 8098 u8 reserved_at_40[0x8]; 8099 u8 qpn[0x18]; 8100 8101 u8 reserved_at_60[0x20]; 8102 8103 u8 multicast_gid[16][0x8]; 8104 }; 8105 8106 struct mlx5_ifc_arm_xrq_out_bits { 8107 u8 status[0x8]; 8108 u8 reserved_at_8[0x18]; 8109 8110 u8 syndrome[0x20]; 8111 8112 u8 reserved_at_40[0x40]; 8113 }; 8114 8115 struct mlx5_ifc_arm_xrq_in_bits { 8116 u8 opcode[0x10]; 8117 u8 reserved_at_10[0x10]; 8118 8119 u8 reserved_at_20[0x10]; 8120 u8 op_mod[0x10]; 8121 8122 u8 reserved_at_40[0x8]; 8123 u8 xrqn[0x18]; 8124 8125 u8 reserved_at_60[0x10]; 8126 u8 lwm[0x10]; 8127 }; 8128 8129 struct mlx5_ifc_arm_xrc_srq_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x40]; 8136 }; 8137 8138 enum { 8139 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8140 }; 8141 8142 struct mlx5_ifc_arm_xrc_srq_in_bits { 8143 u8 opcode[0x10]; 8144 u8 uid[0x10]; 8145 8146 u8 reserved_at_20[0x10]; 8147 u8 op_mod[0x10]; 8148 8149 u8 reserved_at_40[0x8]; 8150 u8 xrc_srqn[0x18]; 8151 8152 u8 reserved_at_60[0x10]; 8153 u8 lwm[0x10]; 8154 }; 8155 8156 struct mlx5_ifc_arm_rq_out_bits { 8157 u8 status[0x8]; 8158 u8 reserved_at_8[0x18]; 8159 8160 u8 syndrome[0x20]; 8161 8162 u8 reserved_at_40[0x40]; 8163 }; 8164 8165 enum { 8166 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8167 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8168 }; 8169 8170 struct mlx5_ifc_arm_rq_in_bits { 8171 u8 opcode[0x10]; 8172 u8 uid[0x10]; 8173 8174 u8 reserved_at_20[0x10]; 8175 u8 op_mod[0x10]; 8176 8177 u8 reserved_at_40[0x8]; 8178 u8 srq_number[0x18]; 8179 8180 u8 reserved_at_60[0x10]; 8181 u8 lwm[0x10]; 8182 }; 8183 8184 struct mlx5_ifc_arm_dct_out_bits { 8185 u8 status[0x8]; 8186 u8 reserved_at_8[0x18]; 8187 8188 u8 syndrome[0x20]; 8189 8190 u8 reserved_at_40[0x40]; 8191 }; 8192 8193 struct mlx5_ifc_arm_dct_in_bits { 8194 u8 opcode[0x10]; 8195 u8 reserved_at_10[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x8]; 8201 u8 dct_number[0x18]; 8202 8203 u8 reserved_at_60[0x20]; 8204 }; 8205 8206 struct mlx5_ifc_alloc_xrcd_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x8]; 8213 u8 xrcd[0x18]; 8214 8215 u8 reserved_at_60[0x20]; 8216 }; 8217 8218 struct mlx5_ifc_alloc_xrcd_in_bits { 8219 u8 opcode[0x10]; 8220 u8 uid[0x10]; 8221 8222 u8 reserved_at_20[0x10]; 8223 u8 op_mod[0x10]; 8224 8225 u8 reserved_at_40[0x40]; 8226 }; 8227 8228 struct mlx5_ifc_alloc_uar_out_bits { 8229 u8 status[0x8]; 8230 u8 reserved_at_8[0x18]; 8231 8232 u8 syndrome[0x20]; 8233 8234 u8 reserved_at_40[0x8]; 8235 u8 uar[0x18]; 8236 8237 u8 reserved_at_60[0x20]; 8238 }; 8239 8240 struct mlx5_ifc_alloc_uar_in_bits { 8241 u8 opcode[0x10]; 8242 u8 reserved_at_10[0x10]; 8243 8244 u8 reserved_at_20[0x10]; 8245 u8 op_mod[0x10]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_alloc_transport_domain_out_bits { 8251 u8 status[0x8]; 8252 u8 reserved_at_8[0x18]; 8253 8254 u8 syndrome[0x20]; 8255 8256 u8 reserved_at_40[0x8]; 8257 u8 transport_domain[0x18]; 8258 8259 u8 reserved_at_60[0x20]; 8260 }; 8261 8262 struct mlx5_ifc_alloc_transport_domain_in_bits { 8263 u8 opcode[0x10]; 8264 u8 uid[0x10]; 8265 8266 u8 reserved_at_20[0x10]; 8267 u8 op_mod[0x10]; 8268 8269 u8 reserved_at_40[0x40]; 8270 }; 8271 8272 struct mlx5_ifc_alloc_q_counter_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x18]; 8279 u8 counter_set_id[0x8]; 8280 8281 u8 reserved_at_60[0x20]; 8282 }; 8283 8284 struct mlx5_ifc_alloc_q_counter_in_bits { 8285 u8 opcode[0x10]; 8286 u8 uid[0x10]; 8287 8288 u8 reserved_at_20[0x10]; 8289 u8 op_mod[0x10]; 8290 8291 u8 reserved_at_40[0x40]; 8292 }; 8293 8294 struct mlx5_ifc_alloc_pd_out_bits { 8295 u8 status[0x8]; 8296 u8 reserved_at_8[0x18]; 8297 8298 u8 syndrome[0x20]; 8299 8300 u8 reserved_at_40[0x8]; 8301 u8 pd[0x18]; 8302 8303 u8 reserved_at_60[0x20]; 8304 }; 8305 8306 struct mlx5_ifc_alloc_pd_in_bits { 8307 u8 opcode[0x10]; 8308 u8 uid[0x10]; 8309 8310 u8 reserved_at_20[0x10]; 8311 u8 op_mod[0x10]; 8312 8313 u8 reserved_at_40[0x40]; 8314 }; 8315 8316 struct mlx5_ifc_alloc_flow_counter_out_bits { 8317 u8 status[0x8]; 8318 u8 reserved_at_8[0x18]; 8319 8320 u8 syndrome[0x20]; 8321 8322 u8 flow_counter_id[0x20]; 8323 8324 u8 reserved_at_60[0x20]; 8325 }; 8326 8327 struct mlx5_ifc_alloc_flow_counter_in_bits { 8328 u8 opcode[0x10]; 8329 u8 reserved_at_10[0x10]; 8330 8331 u8 reserved_at_20[0x10]; 8332 u8 op_mod[0x10]; 8333 8334 u8 reserved_at_40[0x38]; 8335 u8 flow_counter_bulk[0x8]; 8336 }; 8337 8338 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 }; 8346 8347 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8348 u8 opcode[0x10]; 8349 u8 reserved_at_10[0x10]; 8350 8351 u8 reserved_at_20[0x10]; 8352 u8 op_mod[0x10]; 8353 8354 u8 reserved_at_40[0x20]; 8355 8356 u8 reserved_at_60[0x10]; 8357 u8 vxlan_udp_port[0x10]; 8358 }; 8359 8360 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8361 u8 status[0x8]; 8362 u8 reserved_at_8[0x18]; 8363 8364 u8 syndrome[0x20]; 8365 8366 u8 reserved_at_40[0x40]; 8367 }; 8368 8369 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8370 u8 rate_limit[0x20]; 8371 8372 u8 burst_upper_bound[0x20]; 8373 8374 u8 reserved_at_40[0x10]; 8375 u8 typical_packet_size[0x10]; 8376 8377 u8 reserved_at_60[0x120]; 8378 }; 8379 8380 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x10]; 8388 u8 rate_limit_index[0x10]; 8389 8390 u8 reserved_at_60[0x20]; 8391 8392 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8393 }; 8394 8395 struct mlx5_ifc_access_register_out_bits { 8396 u8 status[0x8]; 8397 u8 reserved_at_8[0x18]; 8398 8399 u8 syndrome[0x20]; 8400 8401 u8 reserved_at_40[0x40]; 8402 8403 u8 register_data[][0x20]; 8404 }; 8405 8406 enum { 8407 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8408 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8409 }; 8410 8411 struct mlx5_ifc_access_register_in_bits { 8412 u8 opcode[0x10]; 8413 u8 reserved_at_10[0x10]; 8414 8415 u8 reserved_at_20[0x10]; 8416 u8 op_mod[0x10]; 8417 8418 u8 reserved_at_40[0x10]; 8419 u8 register_id[0x10]; 8420 8421 u8 argument[0x20]; 8422 8423 u8 register_data[][0x20]; 8424 }; 8425 8426 struct mlx5_ifc_sltp_reg_bits { 8427 u8 status[0x4]; 8428 u8 version[0x4]; 8429 u8 local_port[0x8]; 8430 u8 pnat[0x2]; 8431 u8 reserved_at_12[0x2]; 8432 u8 lane[0x4]; 8433 u8 reserved_at_18[0x8]; 8434 8435 u8 reserved_at_20[0x20]; 8436 8437 u8 reserved_at_40[0x7]; 8438 u8 polarity[0x1]; 8439 u8 ob_tap0[0x8]; 8440 u8 ob_tap1[0x8]; 8441 u8 ob_tap2[0x8]; 8442 8443 u8 reserved_at_60[0xc]; 8444 u8 ob_preemp_mode[0x4]; 8445 u8 ob_reg[0x8]; 8446 u8 ob_bias[0x8]; 8447 8448 u8 reserved_at_80[0x20]; 8449 }; 8450 8451 struct mlx5_ifc_slrg_reg_bits { 8452 u8 status[0x4]; 8453 u8 version[0x4]; 8454 u8 local_port[0x8]; 8455 u8 pnat[0x2]; 8456 u8 reserved_at_12[0x2]; 8457 u8 lane[0x4]; 8458 u8 reserved_at_18[0x8]; 8459 8460 u8 time_to_link_up[0x10]; 8461 u8 reserved_at_30[0xc]; 8462 u8 grade_lane_speed[0x4]; 8463 8464 u8 grade_version[0x8]; 8465 u8 grade[0x18]; 8466 8467 u8 reserved_at_60[0x4]; 8468 u8 height_grade_type[0x4]; 8469 u8 height_grade[0x18]; 8470 8471 u8 height_dz[0x10]; 8472 u8 height_dv[0x10]; 8473 8474 u8 reserved_at_a0[0x10]; 8475 u8 height_sigma[0x10]; 8476 8477 u8 reserved_at_c0[0x20]; 8478 8479 u8 reserved_at_e0[0x4]; 8480 u8 phase_grade_type[0x4]; 8481 u8 phase_grade[0x18]; 8482 8483 u8 reserved_at_100[0x8]; 8484 u8 phase_eo_pos[0x8]; 8485 u8 reserved_at_110[0x8]; 8486 u8 phase_eo_neg[0x8]; 8487 8488 u8 ffe_set_tested[0x10]; 8489 u8 test_errors_per_lane[0x10]; 8490 }; 8491 8492 struct mlx5_ifc_pvlc_reg_bits { 8493 u8 reserved_at_0[0x8]; 8494 u8 local_port[0x8]; 8495 u8 reserved_at_10[0x10]; 8496 8497 u8 reserved_at_20[0x1c]; 8498 u8 vl_hw_cap[0x4]; 8499 8500 u8 reserved_at_40[0x1c]; 8501 u8 vl_admin[0x4]; 8502 8503 u8 reserved_at_60[0x1c]; 8504 u8 vl_operational[0x4]; 8505 }; 8506 8507 struct mlx5_ifc_pude_reg_bits { 8508 u8 swid[0x8]; 8509 u8 local_port[0x8]; 8510 u8 reserved_at_10[0x4]; 8511 u8 admin_status[0x4]; 8512 u8 reserved_at_18[0x4]; 8513 u8 oper_status[0x4]; 8514 8515 u8 reserved_at_20[0x60]; 8516 }; 8517 8518 struct mlx5_ifc_ptys_reg_bits { 8519 u8 reserved_at_0[0x1]; 8520 u8 an_disable_admin[0x1]; 8521 u8 an_disable_cap[0x1]; 8522 u8 reserved_at_3[0x5]; 8523 u8 local_port[0x8]; 8524 u8 reserved_at_10[0xd]; 8525 u8 proto_mask[0x3]; 8526 8527 u8 an_status[0x4]; 8528 u8 reserved_at_24[0xc]; 8529 u8 data_rate_oper[0x10]; 8530 8531 u8 ext_eth_proto_capability[0x20]; 8532 8533 u8 eth_proto_capability[0x20]; 8534 8535 u8 ib_link_width_capability[0x10]; 8536 u8 ib_proto_capability[0x10]; 8537 8538 u8 ext_eth_proto_admin[0x20]; 8539 8540 u8 eth_proto_admin[0x20]; 8541 8542 u8 ib_link_width_admin[0x10]; 8543 u8 ib_proto_admin[0x10]; 8544 8545 u8 ext_eth_proto_oper[0x20]; 8546 8547 u8 eth_proto_oper[0x20]; 8548 8549 u8 ib_link_width_oper[0x10]; 8550 u8 ib_proto_oper[0x10]; 8551 8552 u8 reserved_at_160[0x1c]; 8553 u8 connector_type[0x4]; 8554 8555 u8 eth_proto_lp_advertise[0x20]; 8556 8557 u8 reserved_at_1a0[0x60]; 8558 }; 8559 8560 struct mlx5_ifc_mlcr_reg_bits { 8561 u8 reserved_at_0[0x8]; 8562 u8 local_port[0x8]; 8563 u8 reserved_at_10[0x20]; 8564 8565 u8 beacon_duration[0x10]; 8566 u8 reserved_at_40[0x10]; 8567 8568 u8 beacon_remain[0x10]; 8569 }; 8570 8571 struct mlx5_ifc_ptas_reg_bits { 8572 u8 reserved_at_0[0x20]; 8573 8574 u8 algorithm_options[0x10]; 8575 u8 reserved_at_30[0x4]; 8576 u8 repetitions_mode[0x4]; 8577 u8 num_of_repetitions[0x8]; 8578 8579 u8 grade_version[0x8]; 8580 u8 height_grade_type[0x4]; 8581 u8 phase_grade_type[0x4]; 8582 u8 height_grade_weight[0x8]; 8583 u8 phase_grade_weight[0x8]; 8584 8585 u8 gisim_measure_bits[0x10]; 8586 u8 adaptive_tap_measure_bits[0x10]; 8587 8588 u8 ber_bath_high_error_threshold[0x10]; 8589 u8 ber_bath_mid_error_threshold[0x10]; 8590 8591 u8 ber_bath_low_error_threshold[0x10]; 8592 u8 one_ratio_high_threshold[0x10]; 8593 8594 u8 one_ratio_high_mid_threshold[0x10]; 8595 u8 one_ratio_low_mid_threshold[0x10]; 8596 8597 u8 one_ratio_low_threshold[0x10]; 8598 u8 ndeo_error_threshold[0x10]; 8599 8600 u8 mixer_offset_step_size[0x10]; 8601 u8 reserved_at_110[0x8]; 8602 u8 mix90_phase_for_voltage_bath[0x8]; 8603 8604 u8 mixer_offset_start[0x10]; 8605 u8 mixer_offset_end[0x10]; 8606 8607 u8 reserved_at_140[0x15]; 8608 u8 ber_test_time[0xb]; 8609 }; 8610 8611 struct mlx5_ifc_pspa_reg_bits { 8612 u8 swid[0x8]; 8613 u8 local_port[0x8]; 8614 u8 sub_port[0x8]; 8615 u8 reserved_at_18[0x8]; 8616 8617 u8 reserved_at_20[0x20]; 8618 }; 8619 8620 struct mlx5_ifc_pqdr_reg_bits { 8621 u8 reserved_at_0[0x8]; 8622 u8 local_port[0x8]; 8623 u8 reserved_at_10[0x5]; 8624 u8 prio[0x3]; 8625 u8 reserved_at_18[0x6]; 8626 u8 mode[0x2]; 8627 8628 u8 reserved_at_20[0x20]; 8629 8630 u8 reserved_at_40[0x10]; 8631 u8 min_threshold[0x10]; 8632 8633 u8 reserved_at_60[0x10]; 8634 u8 max_threshold[0x10]; 8635 8636 u8 reserved_at_80[0x10]; 8637 u8 mark_probability_denominator[0x10]; 8638 8639 u8 reserved_at_a0[0x60]; 8640 }; 8641 8642 struct mlx5_ifc_ppsc_reg_bits { 8643 u8 reserved_at_0[0x8]; 8644 u8 local_port[0x8]; 8645 u8 reserved_at_10[0x10]; 8646 8647 u8 reserved_at_20[0x60]; 8648 8649 u8 reserved_at_80[0x1c]; 8650 u8 wrps_admin[0x4]; 8651 8652 u8 reserved_at_a0[0x1c]; 8653 u8 wrps_status[0x4]; 8654 8655 u8 reserved_at_c0[0x8]; 8656 u8 up_threshold[0x8]; 8657 u8 reserved_at_d0[0x8]; 8658 u8 down_threshold[0x8]; 8659 8660 u8 reserved_at_e0[0x20]; 8661 8662 u8 reserved_at_100[0x1c]; 8663 u8 srps_admin[0x4]; 8664 8665 u8 reserved_at_120[0x1c]; 8666 u8 srps_status[0x4]; 8667 8668 u8 reserved_at_140[0x40]; 8669 }; 8670 8671 struct mlx5_ifc_pplr_reg_bits { 8672 u8 reserved_at_0[0x8]; 8673 u8 local_port[0x8]; 8674 u8 reserved_at_10[0x10]; 8675 8676 u8 reserved_at_20[0x8]; 8677 u8 lb_cap[0x8]; 8678 u8 reserved_at_30[0x8]; 8679 u8 lb_en[0x8]; 8680 }; 8681 8682 struct mlx5_ifc_pplm_reg_bits { 8683 u8 reserved_at_0[0x8]; 8684 u8 local_port[0x8]; 8685 u8 reserved_at_10[0x10]; 8686 8687 u8 reserved_at_20[0x20]; 8688 8689 u8 port_profile_mode[0x8]; 8690 u8 static_port_profile[0x8]; 8691 u8 active_port_profile[0x8]; 8692 u8 reserved_at_58[0x8]; 8693 8694 u8 retransmission_active[0x8]; 8695 u8 fec_mode_active[0x18]; 8696 8697 u8 rs_fec_correction_bypass_cap[0x4]; 8698 u8 reserved_at_84[0x8]; 8699 u8 fec_override_cap_56g[0x4]; 8700 u8 fec_override_cap_100g[0x4]; 8701 u8 fec_override_cap_50g[0x4]; 8702 u8 fec_override_cap_25g[0x4]; 8703 u8 fec_override_cap_10g_40g[0x4]; 8704 8705 u8 rs_fec_correction_bypass_admin[0x4]; 8706 u8 reserved_at_a4[0x8]; 8707 u8 fec_override_admin_56g[0x4]; 8708 u8 fec_override_admin_100g[0x4]; 8709 u8 fec_override_admin_50g[0x4]; 8710 u8 fec_override_admin_25g[0x4]; 8711 u8 fec_override_admin_10g_40g[0x4]; 8712 8713 u8 fec_override_cap_400g_8x[0x10]; 8714 u8 fec_override_cap_200g_4x[0x10]; 8715 8716 u8 fec_override_cap_100g_2x[0x10]; 8717 u8 fec_override_cap_50g_1x[0x10]; 8718 8719 u8 fec_override_admin_400g_8x[0x10]; 8720 u8 fec_override_admin_200g_4x[0x10]; 8721 8722 u8 fec_override_admin_100g_2x[0x10]; 8723 u8 fec_override_admin_50g_1x[0x10]; 8724 8725 u8 reserved_at_140[0x140]; 8726 }; 8727 8728 struct mlx5_ifc_ppcnt_reg_bits { 8729 u8 swid[0x8]; 8730 u8 local_port[0x8]; 8731 u8 pnat[0x2]; 8732 u8 reserved_at_12[0x8]; 8733 u8 grp[0x6]; 8734 8735 u8 clr[0x1]; 8736 u8 reserved_at_21[0x1c]; 8737 u8 prio_tc[0x3]; 8738 8739 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8740 }; 8741 8742 struct mlx5_ifc_mpein_reg_bits { 8743 u8 reserved_at_0[0x2]; 8744 u8 depth[0x6]; 8745 u8 pcie_index[0x8]; 8746 u8 node[0x8]; 8747 u8 reserved_at_18[0x8]; 8748 8749 u8 capability_mask[0x20]; 8750 8751 u8 reserved_at_40[0x8]; 8752 u8 link_width_enabled[0x8]; 8753 u8 link_speed_enabled[0x10]; 8754 8755 u8 lane0_physical_position[0x8]; 8756 u8 link_width_active[0x8]; 8757 u8 link_speed_active[0x10]; 8758 8759 u8 num_of_pfs[0x10]; 8760 u8 num_of_vfs[0x10]; 8761 8762 u8 bdf0[0x10]; 8763 u8 reserved_at_b0[0x10]; 8764 8765 u8 max_read_request_size[0x4]; 8766 u8 max_payload_size[0x4]; 8767 u8 reserved_at_c8[0x5]; 8768 u8 pwr_status[0x3]; 8769 u8 port_type[0x4]; 8770 u8 reserved_at_d4[0xb]; 8771 u8 lane_reversal[0x1]; 8772 8773 u8 reserved_at_e0[0x14]; 8774 u8 pci_power[0xc]; 8775 8776 u8 reserved_at_100[0x20]; 8777 8778 u8 device_status[0x10]; 8779 u8 port_state[0x8]; 8780 u8 reserved_at_138[0x8]; 8781 8782 u8 reserved_at_140[0x10]; 8783 u8 receiver_detect_result[0x10]; 8784 8785 u8 reserved_at_160[0x20]; 8786 }; 8787 8788 struct mlx5_ifc_mpcnt_reg_bits { 8789 u8 reserved_at_0[0x8]; 8790 u8 pcie_index[0x8]; 8791 u8 reserved_at_10[0xa]; 8792 u8 grp[0x6]; 8793 8794 u8 clr[0x1]; 8795 u8 reserved_at_21[0x1f]; 8796 8797 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8798 }; 8799 8800 struct mlx5_ifc_ppad_reg_bits { 8801 u8 reserved_at_0[0x3]; 8802 u8 single_mac[0x1]; 8803 u8 reserved_at_4[0x4]; 8804 u8 local_port[0x8]; 8805 u8 mac_47_32[0x10]; 8806 8807 u8 mac_31_0[0x20]; 8808 8809 u8 reserved_at_40[0x40]; 8810 }; 8811 8812 struct mlx5_ifc_pmtu_reg_bits { 8813 u8 reserved_at_0[0x8]; 8814 u8 local_port[0x8]; 8815 u8 reserved_at_10[0x10]; 8816 8817 u8 max_mtu[0x10]; 8818 u8 reserved_at_30[0x10]; 8819 8820 u8 admin_mtu[0x10]; 8821 u8 reserved_at_50[0x10]; 8822 8823 u8 oper_mtu[0x10]; 8824 u8 reserved_at_70[0x10]; 8825 }; 8826 8827 struct mlx5_ifc_pmpr_reg_bits { 8828 u8 reserved_at_0[0x8]; 8829 u8 module[0x8]; 8830 u8 reserved_at_10[0x10]; 8831 8832 u8 reserved_at_20[0x18]; 8833 u8 attenuation_5g[0x8]; 8834 8835 u8 reserved_at_40[0x18]; 8836 u8 attenuation_7g[0x8]; 8837 8838 u8 reserved_at_60[0x18]; 8839 u8 attenuation_12g[0x8]; 8840 }; 8841 8842 struct mlx5_ifc_pmpe_reg_bits { 8843 u8 reserved_at_0[0x8]; 8844 u8 module[0x8]; 8845 u8 reserved_at_10[0xc]; 8846 u8 module_status[0x4]; 8847 8848 u8 reserved_at_20[0x60]; 8849 }; 8850 8851 struct mlx5_ifc_pmpc_reg_bits { 8852 u8 module_state_updated[32][0x8]; 8853 }; 8854 8855 struct mlx5_ifc_pmlpn_reg_bits { 8856 u8 reserved_at_0[0x4]; 8857 u8 mlpn_status[0x4]; 8858 u8 local_port[0x8]; 8859 u8 reserved_at_10[0x10]; 8860 8861 u8 e[0x1]; 8862 u8 reserved_at_21[0x1f]; 8863 }; 8864 8865 struct mlx5_ifc_pmlp_reg_bits { 8866 u8 rxtx[0x1]; 8867 u8 reserved_at_1[0x7]; 8868 u8 local_port[0x8]; 8869 u8 reserved_at_10[0x8]; 8870 u8 width[0x8]; 8871 8872 u8 lane0_module_mapping[0x20]; 8873 8874 u8 lane1_module_mapping[0x20]; 8875 8876 u8 lane2_module_mapping[0x20]; 8877 8878 u8 lane3_module_mapping[0x20]; 8879 8880 u8 reserved_at_a0[0x160]; 8881 }; 8882 8883 struct mlx5_ifc_pmaos_reg_bits { 8884 u8 reserved_at_0[0x8]; 8885 u8 module[0x8]; 8886 u8 reserved_at_10[0x4]; 8887 u8 admin_status[0x4]; 8888 u8 reserved_at_18[0x4]; 8889 u8 oper_status[0x4]; 8890 8891 u8 ase[0x1]; 8892 u8 ee[0x1]; 8893 u8 reserved_at_22[0x1c]; 8894 u8 e[0x2]; 8895 8896 u8 reserved_at_40[0x40]; 8897 }; 8898 8899 struct mlx5_ifc_plpc_reg_bits { 8900 u8 reserved_at_0[0x4]; 8901 u8 profile_id[0xc]; 8902 u8 reserved_at_10[0x4]; 8903 u8 proto_mask[0x4]; 8904 u8 reserved_at_18[0x8]; 8905 8906 u8 reserved_at_20[0x10]; 8907 u8 lane_speed[0x10]; 8908 8909 u8 reserved_at_40[0x17]; 8910 u8 lpbf[0x1]; 8911 u8 fec_mode_policy[0x8]; 8912 8913 u8 retransmission_capability[0x8]; 8914 u8 fec_mode_capability[0x18]; 8915 8916 u8 retransmission_support_admin[0x8]; 8917 u8 fec_mode_support_admin[0x18]; 8918 8919 u8 retransmission_request_admin[0x8]; 8920 u8 fec_mode_request_admin[0x18]; 8921 8922 u8 reserved_at_c0[0x80]; 8923 }; 8924 8925 struct mlx5_ifc_plib_reg_bits { 8926 u8 reserved_at_0[0x8]; 8927 u8 local_port[0x8]; 8928 u8 reserved_at_10[0x8]; 8929 u8 ib_port[0x8]; 8930 8931 u8 reserved_at_20[0x60]; 8932 }; 8933 8934 struct mlx5_ifc_plbf_reg_bits { 8935 u8 reserved_at_0[0x8]; 8936 u8 local_port[0x8]; 8937 u8 reserved_at_10[0xd]; 8938 u8 lbf_mode[0x3]; 8939 8940 u8 reserved_at_20[0x20]; 8941 }; 8942 8943 struct mlx5_ifc_pipg_reg_bits { 8944 u8 reserved_at_0[0x8]; 8945 u8 local_port[0x8]; 8946 u8 reserved_at_10[0x10]; 8947 8948 u8 dic[0x1]; 8949 u8 reserved_at_21[0x19]; 8950 u8 ipg[0x4]; 8951 u8 reserved_at_3e[0x2]; 8952 }; 8953 8954 struct mlx5_ifc_pifr_reg_bits { 8955 u8 reserved_at_0[0x8]; 8956 u8 local_port[0x8]; 8957 u8 reserved_at_10[0x10]; 8958 8959 u8 reserved_at_20[0xe0]; 8960 8961 u8 port_filter[8][0x20]; 8962 8963 u8 port_filter_update_en[8][0x20]; 8964 }; 8965 8966 struct mlx5_ifc_pfcc_reg_bits { 8967 u8 reserved_at_0[0x8]; 8968 u8 local_port[0x8]; 8969 u8 reserved_at_10[0xb]; 8970 u8 ppan_mask_n[0x1]; 8971 u8 minor_stall_mask[0x1]; 8972 u8 critical_stall_mask[0x1]; 8973 u8 reserved_at_1e[0x2]; 8974 8975 u8 ppan[0x4]; 8976 u8 reserved_at_24[0x4]; 8977 u8 prio_mask_tx[0x8]; 8978 u8 reserved_at_30[0x8]; 8979 u8 prio_mask_rx[0x8]; 8980 8981 u8 pptx[0x1]; 8982 u8 aptx[0x1]; 8983 u8 pptx_mask_n[0x1]; 8984 u8 reserved_at_43[0x5]; 8985 u8 pfctx[0x8]; 8986 u8 reserved_at_50[0x10]; 8987 8988 u8 pprx[0x1]; 8989 u8 aprx[0x1]; 8990 u8 pprx_mask_n[0x1]; 8991 u8 reserved_at_63[0x5]; 8992 u8 pfcrx[0x8]; 8993 u8 reserved_at_70[0x10]; 8994 8995 u8 device_stall_minor_watermark[0x10]; 8996 u8 device_stall_critical_watermark[0x10]; 8997 8998 u8 reserved_at_a0[0x60]; 8999 }; 9000 9001 struct mlx5_ifc_pelc_reg_bits { 9002 u8 op[0x4]; 9003 u8 reserved_at_4[0x4]; 9004 u8 local_port[0x8]; 9005 u8 reserved_at_10[0x10]; 9006 9007 u8 op_admin[0x8]; 9008 u8 op_capability[0x8]; 9009 u8 op_request[0x8]; 9010 u8 op_active[0x8]; 9011 9012 u8 admin[0x40]; 9013 9014 u8 capability[0x40]; 9015 9016 u8 request[0x40]; 9017 9018 u8 active[0x40]; 9019 9020 u8 reserved_at_140[0x80]; 9021 }; 9022 9023 struct mlx5_ifc_peir_reg_bits { 9024 u8 reserved_at_0[0x8]; 9025 u8 local_port[0x8]; 9026 u8 reserved_at_10[0x10]; 9027 9028 u8 reserved_at_20[0xc]; 9029 u8 error_count[0x4]; 9030 u8 reserved_at_30[0x10]; 9031 9032 u8 reserved_at_40[0xc]; 9033 u8 lane[0x4]; 9034 u8 reserved_at_50[0x8]; 9035 u8 error_type[0x8]; 9036 }; 9037 9038 struct mlx5_ifc_mpegc_reg_bits { 9039 u8 reserved_at_0[0x30]; 9040 u8 field_select[0x10]; 9041 9042 u8 tx_overflow_sense[0x1]; 9043 u8 mark_cqe[0x1]; 9044 u8 mark_cnp[0x1]; 9045 u8 reserved_at_43[0x1b]; 9046 u8 tx_lossy_overflow_oper[0x2]; 9047 9048 u8 reserved_at_60[0x100]; 9049 }; 9050 9051 struct mlx5_ifc_pcam_enhanced_features_bits { 9052 u8 reserved_at_0[0x68]; 9053 u8 fec_50G_per_lane_in_pplm[0x1]; 9054 u8 reserved_at_69[0x4]; 9055 u8 rx_icrc_encapsulated_counter[0x1]; 9056 u8 reserved_at_6e[0x4]; 9057 u8 ptys_extended_ethernet[0x1]; 9058 u8 reserved_at_73[0x3]; 9059 u8 pfcc_mask[0x1]; 9060 u8 reserved_at_77[0x3]; 9061 u8 per_lane_error_counters[0x1]; 9062 u8 rx_buffer_fullness_counters[0x1]; 9063 u8 ptys_connector_type[0x1]; 9064 u8 reserved_at_7d[0x1]; 9065 u8 ppcnt_discard_group[0x1]; 9066 u8 ppcnt_statistical_group[0x1]; 9067 }; 9068 9069 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9070 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9071 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9072 9073 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9074 u8 pplm[0x1]; 9075 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9076 9077 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9078 u8 pbmc[0x1]; 9079 u8 pptb[0x1]; 9080 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9081 u8 ppcnt[0x1]; 9082 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9083 }; 9084 9085 struct mlx5_ifc_pcam_reg_bits { 9086 u8 reserved_at_0[0x8]; 9087 u8 feature_group[0x8]; 9088 u8 reserved_at_10[0x8]; 9089 u8 access_reg_group[0x8]; 9090 9091 u8 reserved_at_20[0x20]; 9092 9093 union { 9094 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9095 u8 reserved_at_0[0x80]; 9096 } port_access_reg_cap_mask; 9097 9098 u8 reserved_at_c0[0x80]; 9099 9100 union { 9101 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9102 u8 reserved_at_0[0x80]; 9103 } feature_cap_mask; 9104 9105 u8 reserved_at_1c0[0xc0]; 9106 }; 9107 9108 struct mlx5_ifc_mcam_enhanced_features_bits { 9109 u8 reserved_at_0[0x6e]; 9110 u8 pci_status_and_power[0x1]; 9111 u8 reserved_at_6f[0x5]; 9112 u8 mark_tx_action_cnp[0x1]; 9113 u8 mark_tx_action_cqe[0x1]; 9114 u8 dynamic_tx_overflow[0x1]; 9115 u8 reserved_at_77[0x4]; 9116 u8 pcie_outbound_stalled[0x1]; 9117 u8 tx_overflow_buffer_pkt[0x1]; 9118 u8 mtpps_enh_out_per_adj[0x1]; 9119 u8 mtpps_fs[0x1]; 9120 u8 pcie_performance_group[0x1]; 9121 }; 9122 9123 struct mlx5_ifc_mcam_access_reg_bits { 9124 u8 reserved_at_0[0x1c]; 9125 u8 mcda[0x1]; 9126 u8 mcc[0x1]; 9127 u8 mcqi[0x1]; 9128 u8 mcqs[0x1]; 9129 9130 u8 regs_95_to_87[0x9]; 9131 u8 mpegc[0x1]; 9132 u8 regs_85_to_68[0x12]; 9133 u8 tracer_registers[0x4]; 9134 9135 u8 regs_63_to_32[0x20]; 9136 u8 regs_31_to_0[0x20]; 9137 }; 9138 9139 struct mlx5_ifc_mcam_access_reg_bits1 { 9140 u8 regs_127_to_96[0x20]; 9141 9142 u8 regs_95_to_64[0x20]; 9143 9144 u8 regs_63_to_32[0x20]; 9145 9146 u8 regs_31_to_0[0x20]; 9147 }; 9148 9149 struct mlx5_ifc_mcam_access_reg_bits2 { 9150 u8 regs_127_to_99[0x1d]; 9151 u8 mirc[0x1]; 9152 u8 regs_97_to_96[0x2]; 9153 9154 u8 regs_95_to_64[0x20]; 9155 9156 u8 regs_63_to_32[0x20]; 9157 9158 u8 regs_31_to_0[0x20]; 9159 }; 9160 9161 struct mlx5_ifc_mcam_reg_bits { 9162 u8 reserved_at_0[0x8]; 9163 u8 feature_group[0x8]; 9164 u8 reserved_at_10[0x8]; 9165 u8 access_reg_group[0x8]; 9166 9167 u8 reserved_at_20[0x20]; 9168 9169 union { 9170 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9171 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9172 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9173 u8 reserved_at_0[0x80]; 9174 } mng_access_reg_cap_mask; 9175 9176 u8 reserved_at_c0[0x80]; 9177 9178 union { 9179 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9180 u8 reserved_at_0[0x80]; 9181 } mng_feature_cap_mask; 9182 9183 u8 reserved_at_1c0[0x80]; 9184 }; 9185 9186 struct mlx5_ifc_qcam_access_reg_cap_mask { 9187 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9188 u8 qpdpm[0x1]; 9189 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9190 u8 qdpm[0x1]; 9191 u8 qpts[0x1]; 9192 u8 qcap[0x1]; 9193 u8 qcam_access_reg_cap_mask_0[0x1]; 9194 }; 9195 9196 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9197 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9198 u8 qpts_trust_both[0x1]; 9199 }; 9200 9201 struct mlx5_ifc_qcam_reg_bits { 9202 u8 reserved_at_0[0x8]; 9203 u8 feature_group[0x8]; 9204 u8 reserved_at_10[0x8]; 9205 u8 access_reg_group[0x8]; 9206 u8 reserved_at_20[0x20]; 9207 9208 union { 9209 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9210 u8 reserved_at_0[0x80]; 9211 } qos_access_reg_cap_mask; 9212 9213 u8 reserved_at_c0[0x80]; 9214 9215 union { 9216 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9217 u8 reserved_at_0[0x80]; 9218 } qos_feature_cap_mask; 9219 9220 u8 reserved_at_1c0[0x80]; 9221 }; 9222 9223 struct mlx5_ifc_core_dump_reg_bits { 9224 u8 reserved_at_0[0x18]; 9225 u8 core_dump_type[0x8]; 9226 9227 u8 reserved_at_20[0x30]; 9228 u8 vhca_id[0x10]; 9229 9230 u8 reserved_at_60[0x8]; 9231 u8 qpn[0x18]; 9232 u8 reserved_at_80[0x180]; 9233 }; 9234 9235 struct mlx5_ifc_pcap_reg_bits { 9236 u8 reserved_at_0[0x8]; 9237 u8 local_port[0x8]; 9238 u8 reserved_at_10[0x10]; 9239 9240 u8 port_capability_mask[4][0x20]; 9241 }; 9242 9243 struct mlx5_ifc_paos_reg_bits { 9244 u8 swid[0x8]; 9245 u8 local_port[0x8]; 9246 u8 reserved_at_10[0x4]; 9247 u8 admin_status[0x4]; 9248 u8 reserved_at_18[0x4]; 9249 u8 oper_status[0x4]; 9250 9251 u8 ase[0x1]; 9252 u8 ee[0x1]; 9253 u8 reserved_at_22[0x1c]; 9254 u8 e[0x2]; 9255 9256 u8 reserved_at_40[0x40]; 9257 }; 9258 9259 struct mlx5_ifc_pamp_reg_bits { 9260 u8 reserved_at_0[0x8]; 9261 u8 opamp_group[0x8]; 9262 u8 reserved_at_10[0xc]; 9263 u8 opamp_group_type[0x4]; 9264 9265 u8 start_index[0x10]; 9266 u8 reserved_at_30[0x4]; 9267 u8 num_of_indices[0xc]; 9268 9269 u8 index_data[18][0x10]; 9270 }; 9271 9272 struct mlx5_ifc_pcmr_reg_bits { 9273 u8 reserved_at_0[0x8]; 9274 u8 local_port[0x8]; 9275 u8 reserved_at_10[0x10]; 9276 9277 u8 entropy_force_cap[0x1]; 9278 u8 entropy_calc_cap[0x1]; 9279 u8 entropy_gre_calc_cap[0x1]; 9280 u8 reserved_at_23[0xf]; 9281 u8 rx_ts_over_crc_cap[0x1]; 9282 u8 reserved_at_33[0xb]; 9283 u8 fcs_cap[0x1]; 9284 u8 reserved_at_3f[0x1]; 9285 9286 u8 entropy_force[0x1]; 9287 u8 entropy_calc[0x1]; 9288 u8 entropy_gre_calc[0x1]; 9289 u8 reserved_at_43[0xf]; 9290 u8 rx_ts_over_crc[0x1]; 9291 u8 reserved_at_53[0xb]; 9292 u8 fcs_chk[0x1]; 9293 u8 reserved_at_5f[0x1]; 9294 }; 9295 9296 struct mlx5_ifc_lane_2_module_mapping_bits { 9297 u8 reserved_at_0[0x6]; 9298 u8 rx_lane[0x2]; 9299 u8 reserved_at_8[0x6]; 9300 u8 tx_lane[0x2]; 9301 u8 reserved_at_10[0x8]; 9302 u8 module[0x8]; 9303 }; 9304 9305 struct mlx5_ifc_bufferx_reg_bits { 9306 u8 reserved_at_0[0x6]; 9307 u8 lossy[0x1]; 9308 u8 epsb[0x1]; 9309 u8 reserved_at_8[0x8]; 9310 u8 size[0x10]; 9311 9312 u8 xoff_threshold[0x10]; 9313 u8 xon_threshold[0x10]; 9314 }; 9315 9316 struct mlx5_ifc_set_node_in_bits { 9317 u8 node_description[64][0x8]; 9318 }; 9319 9320 struct mlx5_ifc_register_power_settings_bits { 9321 u8 reserved_at_0[0x18]; 9322 u8 power_settings_level[0x8]; 9323 9324 u8 reserved_at_20[0x60]; 9325 }; 9326 9327 struct mlx5_ifc_register_host_endianness_bits { 9328 u8 he[0x1]; 9329 u8 reserved_at_1[0x1f]; 9330 9331 u8 reserved_at_20[0x60]; 9332 }; 9333 9334 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9335 u8 reserved_at_0[0x20]; 9336 9337 u8 mkey[0x20]; 9338 9339 u8 addressh_63_32[0x20]; 9340 9341 u8 addressl_31_0[0x20]; 9342 }; 9343 9344 struct mlx5_ifc_ud_adrs_vector_bits { 9345 u8 dc_key[0x40]; 9346 9347 u8 ext[0x1]; 9348 u8 reserved_at_41[0x7]; 9349 u8 destination_qp_dct[0x18]; 9350 9351 u8 static_rate[0x4]; 9352 u8 sl_eth_prio[0x4]; 9353 u8 fl[0x1]; 9354 u8 mlid[0x7]; 9355 u8 rlid_udp_sport[0x10]; 9356 9357 u8 reserved_at_80[0x20]; 9358 9359 u8 rmac_47_16[0x20]; 9360 9361 u8 rmac_15_0[0x10]; 9362 u8 tclass[0x8]; 9363 u8 hop_limit[0x8]; 9364 9365 u8 reserved_at_e0[0x1]; 9366 u8 grh[0x1]; 9367 u8 reserved_at_e2[0x2]; 9368 u8 src_addr_index[0x8]; 9369 u8 flow_label[0x14]; 9370 9371 u8 rgid_rip[16][0x8]; 9372 }; 9373 9374 struct mlx5_ifc_pages_req_event_bits { 9375 u8 reserved_at_0[0x10]; 9376 u8 function_id[0x10]; 9377 9378 u8 num_pages[0x20]; 9379 9380 u8 reserved_at_40[0xa0]; 9381 }; 9382 9383 struct mlx5_ifc_eqe_bits { 9384 u8 reserved_at_0[0x8]; 9385 u8 event_type[0x8]; 9386 u8 reserved_at_10[0x8]; 9387 u8 event_sub_type[0x8]; 9388 9389 u8 reserved_at_20[0xe0]; 9390 9391 union mlx5_ifc_event_auto_bits event_data; 9392 9393 u8 reserved_at_1e0[0x10]; 9394 u8 signature[0x8]; 9395 u8 reserved_at_1f8[0x7]; 9396 u8 owner[0x1]; 9397 }; 9398 9399 enum { 9400 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9401 }; 9402 9403 struct mlx5_ifc_cmd_queue_entry_bits { 9404 u8 type[0x8]; 9405 u8 reserved_at_8[0x18]; 9406 9407 u8 input_length[0x20]; 9408 9409 u8 input_mailbox_pointer_63_32[0x20]; 9410 9411 u8 input_mailbox_pointer_31_9[0x17]; 9412 u8 reserved_at_77[0x9]; 9413 9414 u8 command_input_inline_data[16][0x8]; 9415 9416 u8 command_output_inline_data[16][0x8]; 9417 9418 u8 output_mailbox_pointer_63_32[0x20]; 9419 9420 u8 output_mailbox_pointer_31_9[0x17]; 9421 u8 reserved_at_1b7[0x9]; 9422 9423 u8 output_length[0x20]; 9424 9425 u8 token[0x8]; 9426 u8 signature[0x8]; 9427 u8 reserved_at_1f0[0x8]; 9428 u8 status[0x7]; 9429 u8 ownership[0x1]; 9430 }; 9431 9432 struct mlx5_ifc_cmd_out_bits { 9433 u8 status[0x8]; 9434 u8 reserved_at_8[0x18]; 9435 9436 u8 syndrome[0x20]; 9437 9438 u8 command_output[0x20]; 9439 }; 9440 9441 struct mlx5_ifc_cmd_in_bits { 9442 u8 opcode[0x10]; 9443 u8 reserved_at_10[0x10]; 9444 9445 u8 reserved_at_20[0x10]; 9446 u8 op_mod[0x10]; 9447 9448 u8 command[][0x20]; 9449 }; 9450 9451 struct mlx5_ifc_cmd_if_box_bits { 9452 u8 mailbox_data[512][0x8]; 9453 9454 u8 reserved_at_1000[0x180]; 9455 9456 u8 next_pointer_63_32[0x20]; 9457 9458 u8 next_pointer_31_10[0x16]; 9459 u8 reserved_at_11b6[0xa]; 9460 9461 u8 block_number[0x20]; 9462 9463 u8 reserved_at_11e0[0x8]; 9464 u8 token[0x8]; 9465 u8 ctrl_signature[0x8]; 9466 u8 signature[0x8]; 9467 }; 9468 9469 struct mlx5_ifc_mtt_bits { 9470 u8 ptag_63_32[0x20]; 9471 9472 u8 ptag_31_8[0x18]; 9473 u8 reserved_at_38[0x6]; 9474 u8 wr_en[0x1]; 9475 u8 rd_en[0x1]; 9476 }; 9477 9478 struct mlx5_ifc_query_wol_rol_out_bits { 9479 u8 status[0x8]; 9480 u8 reserved_at_8[0x18]; 9481 9482 u8 syndrome[0x20]; 9483 9484 u8 reserved_at_40[0x10]; 9485 u8 rol_mode[0x8]; 9486 u8 wol_mode[0x8]; 9487 9488 u8 reserved_at_60[0x20]; 9489 }; 9490 9491 struct mlx5_ifc_query_wol_rol_in_bits { 9492 u8 opcode[0x10]; 9493 u8 reserved_at_10[0x10]; 9494 9495 u8 reserved_at_20[0x10]; 9496 u8 op_mod[0x10]; 9497 9498 u8 reserved_at_40[0x40]; 9499 }; 9500 9501 struct mlx5_ifc_set_wol_rol_out_bits { 9502 u8 status[0x8]; 9503 u8 reserved_at_8[0x18]; 9504 9505 u8 syndrome[0x20]; 9506 9507 u8 reserved_at_40[0x40]; 9508 }; 9509 9510 struct mlx5_ifc_set_wol_rol_in_bits { 9511 u8 opcode[0x10]; 9512 u8 reserved_at_10[0x10]; 9513 9514 u8 reserved_at_20[0x10]; 9515 u8 op_mod[0x10]; 9516 9517 u8 rol_mode_valid[0x1]; 9518 u8 wol_mode_valid[0x1]; 9519 u8 reserved_at_42[0xe]; 9520 u8 rol_mode[0x8]; 9521 u8 wol_mode[0x8]; 9522 9523 u8 reserved_at_60[0x20]; 9524 }; 9525 9526 enum { 9527 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9528 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9529 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9530 }; 9531 9532 enum { 9533 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9534 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9535 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9536 }; 9537 9538 enum { 9539 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9540 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9541 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9542 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9543 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9544 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9545 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9546 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9547 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9548 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9549 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9550 }; 9551 9552 struct mlx5_ifc_initial_seg_bits { 9553 u8 fw_rev_minor[0x10]; 9554 u8 fw_rev_major[0x10]; 9555 9556 u8 cmd_interface_rev[0x10]; 9557 u8 fw_rev_subminor[0x10]; 9558 9559 u8 reserved_at_40[0x40]; 9560 9561 u8 cmdq_phy_addr_63_32[0x20]; 9562 9563 u8 cmdq_phy_addr_31_12[0x14]; 9564 u8 reserved_at_b4[0x2]; 9565 u8 nic_interface[0x2]; 9566 u8 log_cmdq_size[0x4]; 9567 u8 log_cmdq_stride[0x4]; 9568 9569 u8 command_doorbell_vector[0x20]; 9570 9571 u8 reserved_at_e0[0xf00]; 9572 9573 u8 initializing[0x1]; 9574 u8 reserved_at_fe1[0x4]; 9575 u8 nic_interface_supported[0x3]; 9576 u8 embedded_cpu[0x1]; 9577 u8 reserved_at_fe9[0x17]; 9578 9579 struct mlx5_ifc_health_buffer_bits health_buffer; 9580 9581 u8 no_dram_nic_offset[0x20]; 9582 9583 u8 reserved_at_1220[0x6e40]; 9584 9585 u8 reserved_at_8060[0x1f]; 9586 u8 clear_int[0x1]; 9587 9588 u8 health_syndrome[0x8]; 9589 u8 health_counter[0x18]; 9590 9591 u8 reserved_at_80a0[0x17fc0]; 9592 }; 9593 9594 struct mlx5_ifc_mtpps_reg_bits { 9595 u8 reserved_at_0[0xc]; 9596 u8 cap_number_of_pps_pins[0x4]; 9597 u8 reserved_at_10[0x4]; 9598 u8 cap_max_num_of_pps_in_pins[0x4]; 9599 u8 reserved_at_18[0x4]; 9600 u8 cap_max_num_of_pps_out_pins[0x4]; 9601 9602 u8 reserved_at_20[0x24]; 9603 u8 cap_pin_3_mode[0x4]; 9604 u8 reserved_at_48[0x4]; 9605 u8 cap_pin_2_mode[0x4]; 9606 u8 reserved_at_50[0x4]; 9607 u8 cap_pin_1_mode[0x4]; 9608 u8 reserved_at_58[0x4]; 9609 u8 cap_pin_0_mode[0x4]; 9610 9611 u8 reserved_at_60[0x4]; 9612 u8 cap_pin_7_mode[0x4]; 9613 u8 reserved_at_68[0x4]; 9614 u8 cap_pin_6_mode[0x4]; 9615 u8 reserved_at_70[0x4]; 9616 u8 cap_pin_5_mode[0x4]; 9617 u8 reserved_at_78[0x4]; 9618 u8 cap_pin_4_mode[0x4]; 9619 9620 u8 field_select[0x20]; 9621 u8 reserved_at_a0[0x60]; 9622 9623 u8 enable[0x1]; 9624 u8 reserved_at_101[0xb]; 9625 u8 pattern[0x4]; 9626 u8 reserved_at_110[0x4]; 9627 u8 pin_mode[0x4]; 9628 u8 pin[0x8]; 9629 9630 u8 reserved_at_120[0x20]; 9631 9632 u8 time_stamp[0x40]; 9633 9634 u8 out_pulse_duration[0x10]; 9635 u8 out_periodic_adjustment[0x10]; 9636 u8 enhanced_out_periodic_adjustment[0x20]; 9637 9638 u8 reserved_at_1c0[0x20]; 9639 }; 9640 9641 struct mlx5_ifc_mtppse_reg_bits { 9642 u8 reserved_at_0[0x18]; 9643 u8 pin[0x8]; 9644 u8 event_arm[0x1]; 9645 u8 reserved_at_21[0x1b]; 9646 u8 event_generation_mode[0x4]; 9647 u8 reserved_at_40[0x40]; 9648 }; 9649 9650 struct mlx5_ifc_mcqs_reg_bits { 9651 u8 last_index_flag[0x1]; 9652 u8 reserved_at_1[0x7]; 9653 u8 fw_device[0x8]; 9654 u8 component_index[0x10]; 9655 9656 u8 reserved_at_20[0x10]; 9657 u8 identifier[0x10]; 9658 9659 u8 reserved_at_40[0x17]; 9660 u8 component_status[0x5]; 9661 u8 component_update_state[0x4]; 9662 9663 u8 last_update_state_changer_type[0x4]; 9664 u8 last_update_state_changer_host_id[0x4]; 9665 u8 reserved_at_68[0x18]; 9666 }; 9667 9668 struct mlx5_ifc_mcqi_cap_bits { 9669 u8 supported_info_bitmask[0x20]; 9670 9671 u8 component_size[0x20]; 9672 9673 u8 max_component_size[0x20]; 9674 9675 u8 log_mcda_word_size[0x4]; 9676 u8 reserved_at_64[0xc]; 9677 u8 mcda_max_write_size[0x10]; 9678 9679 u8 rd_en[0x1]; 9680 u8 reserved_at_81[0x1]; 9681 u8 match_chip_id[0x1]; 9682 u8 match_psid[0x1]; 9683 u8 check_user_timestamp[0x1]; 9684 u8 match_base_guid_mac[0x1]; 9685 u8 reserved_at_86[0x1a]; 9686 }; 9687 9688 struct mlx5_ifc_mcqi_version_bits { 9689 u8 reserved_at_0[0x2]; 9690 u8 build_time_valid[0x1]; 9691 u8 user_defined_time_valid[0x1]; 9692 u8 reserved_at_4[0x14]; 9693 u8 version_string_length[0x8]; 9694 9695 u8 version[0x20]; 9696 9697 u8 build_time[0x40]; 9698 9699 u8 user_defined_time[0x40]; 9700 9701 u8 build_tool_version[0x20]; 9702 9703 u8 reserved_at_e0[0x20]; 9704 9705 u8 version_string[92][0x8]; 9706 }; 9707 9708 struct mlx5_ifc_mcqi_activation_method_bits { 9709 u8 pending_server_ac_power_cycle[0x1]; 9710 u8 pending_server_dc_power_cycle[0x1]; 9711 u8 pending_server_reboot[0x1]; 9712 u8 pending_fw_reset[0x1]; 9713 u8 auto_activate[0x1]; 9714 u8 all_hosts_sync[0x1]; 9715 u8 device_hw_reset[0x1]; 9716 u8 reserved_at_7[0x19]; 9717 }; 9718 9719 union mlx5_ifc_mcqi_reg_data_bits { 9720 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9721 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9722 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9723 }; 9724 9725 struct mlx5_ifc_mcqi_reg_bits { 9726 u8 read_pending_component[0x1]; 9727 u8 reserved_at_1[0xf]; 9728 u8 component_index[0x10]; 9729 9730 u8 reserved_at_20[0x20]; 9731 9732 u8 reserved_at_40[0x1b]; 9733 u8 info_type[0x5]; 9734 9735 u8 info_size[0x20]; 9736 9737 u8 offset[0x20]; 9738 9739 u8 reserved_at_a0[0x10]; 9740 u8 data_size[0x10]; 9741 9742 union mlx5_ifc_mcqi_reg_data_bits data[]; 9743 }; 9744 9745 struct mlx5_ifc_mcc_reg_bits { 9746 u8 reserved_at_0[0x4]; 9747 u8 time_elapsed_since_last_cmd[0xc]; 9748 u8 reserved_at_10[0x8]; 9749 u8 instruction[0x8]; 9750 9751 u8 reserved_at_20[0x10]; 9752 u8 component_index[0x10]; 9753 9754 u8 reserved_at_40[0x8]; 9755 u8 update_handle[0x18]; 9756 9757 u8 handle_owner_type[0x4]; 9758 u8 handle_owner_host_id[0x4]; 9759 u8 reserved_at_68[0x1]; 9760 u8 control_progress[0x7]; 9761 u8 error_code[0x8]; 9762 u8 reserved_at_78[0x4]; 9763 u8 control_state[0x4]; 9764 9765 u8 component_size[0x20]; 9766 9767 u8 reserved_at_a0[0x60]; 9768 }; 9769 9770 struct mlx5_ifc_mcda_reg_bits { 9771 u8 reserved_at_0[0x8]; 9772 u8 update_handle[0x18]; 9773 9774 u8 offset[0x20]; 9775 9776 u8 reserved_at_40[0x10]; 9777 u8 size[0x10]; 9778 9779 u8 reserved_at_60[0x20]; 9780 9781 u8 data[][0x20]; 9782 }; 9783 9784 enum { 9785 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9786 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9787 }; 9788 9789 enum { 9790 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9791 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9792 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9793 }; 9794 9795 struct mlx5_ifc_mfrl_reg_bits { 9796 u8 reserved_at_0[0x20]; 9797 9798 u8 reserved_at_20[0x2]; 9799 u8 pci_sync_for_fw_update_start[0x1]; 9800 u8 pci_sync_for_fw_update_resp[0x2]; 9801 u8 rst_type_sel[0x3]; 9802 u8 reserved_at_28[0x8]; 9803 u8 reset_type[0x8]; 9804 u8 reset_level[0x8]; 9805 }; 9806 9807 struct mlx5_ifc_mirc_reg_bits { 9808 u8 reserved_at_0[0x18]; 9809 u8 status_code[0x8]; 9810 9811 u8 reserved_at_20[0x20]; 9812 }; 9813 9814 union mlx5_ifc_ports_control_registers_document_bits { 9815 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9816 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9817 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9818 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9819 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9820 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9821 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9822 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9823 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9824 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9825 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9826 struct mlx5_ifc_paos_reg_bits paos_reg; 9827 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9828 struct mlx5_ifc_peir_reg_bits peir_reg; 9829 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9830 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9831 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9832 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9833 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9834 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9835 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9836 struct mlx5_ifc_plib_reg_bits plib_reg; 9837 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9838 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9839 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9840 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9841 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9842 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9843 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9844 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9845 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9846 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9847 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9848 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9849 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9850 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9851 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9852 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9853 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9854 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9855 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9856 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9857 struct mlx5_ifc_pude_reg_bits pude_reg; 9858 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9859 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9860 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9861 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9862 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9863 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9864 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9865 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9866 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9867 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9868 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9869 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9870 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9871 u8 reserved_at_0[0x60e0]; 9872 }; 9873 9874 union mlx5_ifc_debug_enhancements_document_bits { 9875 struct mlx5_ifc_health_buffer_bits health_buffer; 9876 u8 reserved_at_0[0x200]; 9877 }; 9878 9879 union mlx5_ifc_uplink_pci_interface_document_bits { 9880 struct mlx5_ifc_initial_seg_bits initial_seg; 9881 u8 reserved_at_0[0x20060]; 9882 }; 9883 9884 struct mlx5_ifc_set_flow_table_root_out_bits { 9885 u8 status[0x8]; 9886 u8 reserved_at_8[0x18]; 9887 9888 u8 syndrome[0x20]; 9889 9890 u8 reserved_at_40[0x40]; 9891 }; 9892 9893 struct mlx5_ifc_set_flow_table_root_in_bits { 9894 u8 opcode[0x10]; 9895 u8 reserved_at_10[0x10]; 9896 9897 u8 reserved_at_20[0x10]; 9898 u8 op_mod[0x10]; 9899 9900 u8 other_vport[0x1]; 9901 u8 reserved_at_41[0xf]; 9902 u8 vport_number[0x10]; 9903 9904 u8 reserved_at_60[0x20]; 9905 9906 u8 table_type[0x8]; 9907 u8 reserved_at_88[0x18]; 9908 9909 u8 reserved_at_a0[0x8]; 9910 u8 table_id[0x18]; 9911 9912 u8 reserved_at_c0[0x8]; 9913 u8 underlay_qpn[0x18]; 9914 u8 reserved_at_e0[0x120]; 9915 }; 9916 9917 enum { 9918 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9919 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9920 }; 9921 9922 struct mlx5_ifc_modify_flow_table_out_bits { 9923 u8 status[0x8]; 9924 u8 reserved_at_8[0x18]; 9925 9926 u8 syndrome[0x20]; 9927 9928 u8 reserved_at_40[0x40]; 9929 }; 9930 9931 struct mlx5_ifc_modify_flow_table_in_bits { 9932 u8 opcode[0x10]; 9933 u8 reserved_at_10[0x10]; 9934 9935 u8 reserved_at_20[0x10]; 9936 u8 op_mod[0x10]; 9937 9938 u8 other_vport[0x1]; 9939 u8 reserved_at_41[0xf]; 9940 u8 vport_number[0x10]; 9941 9942 u8 reserved_at_60[0x10]; 9943 u8 modify_field_select[0x10]; 9944 9945 u8 table_type[0x8]; 9946 u8 reserved_at_88[0x18]; 9947 9948 u8 reserved_at_a0[0x8]; 9949 u8 table_id[0x18]; 9950 9951 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9952 }; 9953 9954 struct mlx5_ifc_ets_tcn_config_reg_bits { 9955 u8 g[0x1]; 9956 u8 b[0x1]; 9957 u8 r[0x1]; 9958 u8 reserved_at_3[0x9]; 9959 u8 group[0x4]; 9960 u8 reserved_at_10[0x9]; 9961 u8 bw_allocation[0x7]; 9962 9963 u8 reserved_at_20[0xc]; 9964 u8 max_bw_units[0x4]; 9965 u8 reserved_at_30[0x8]; 9966 u8 max_bw_value[0x8]; 9967 }; 9968 9969 struct mlx5_ifc_ets_global_config_reg_bits { 9970 u8 reserved_at_0[0x2]; 9971 u8 r[0x1]; 9972 u8 reserved_at_3[0x1d]; 9973 9974 u8 reserved_at_20[0xc]; 9975 u8 max_bw_units[0x4]; 9976 u8 reserved_at_30[0x8]; 9977 u8 max_bw_value[0x8]; 9978 }; 9979 9980 struct mlx5_ifc_qetc_reg_bits { 9981 u8 reserved_at_0[0x8]; 9982 u8 port_number[0x8]; 9983 u8 reserved_at_10[0x30]; 9984 9985 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9986 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9987 }; 9988 9989 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9990 u8 e[0x1]; 9991 u8 reserved_at_01[0x0b]; 9992 u8 prio[0x04]; 9993 }; 9994 9995 struct mlx5_ifc_qpdpm_reg_bits { 9996 u8 reserved_at_0[0x8]; 9997 u8 local_port[0x8]; 9998 u8 reserved_at_10[0x10]; 9999 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10000 }; 10001 10002 struct mlx5_ifc_qpts_reg_bits { 10003 u8 reserved_at_0[0x8]; 10004 u8 local_port[0x8]; 10005 u8 reserved_at_10[0x2d]; 10006 u8 trust_state[0x3]; 10007 }; 10008 10009 struct mlx5_ifc_pptb_reg_bits { 10010 u8 reserved_at_0[0x2]; 10011 u8 mm[0x2]; 10012 u8 reserved_at_4[0x4]; 10013 u8 local_port[0x8]; 10014 u8 reserved_at_10[0x6]; 10015 u8 cm[0x1]; 10016 u8 um[0x1]; 10017 u8 pm[0x8]; 10018 10019 u8 prio_x_buff[0x20]; 10020 10021 u8 pm_msb[0x8]; 10022 u8 reserved_at_48[0x10]; 10023 u8 ctrl_buff[0x4]; 10024 u8 untagged_buff[0x4]; 10025 }; 10026 10027 struct mlx5_ifc_sbcam_reg_bits { 10028 u8 reserved_at_0[0x8]; 10029 u8 feature_group[0x8]; 10030 u8 reserved_at_10[0x8]; 10031 u8 access_reg_group[0x8]; 10032 10033 u8 reserved_at_20[0x20]; 10034 10035 u8 sb_access_reg_cap_mask[4][0x20]; 10036 10037 u8 reserved_at_c0[0x80]; 10038 10039 u8 sb_feature_cap_mask[4][0x20]; 10040 10041 u8 reserved_at_1c0[0x40]; 10042 10043 u8 cap_total_buffer_size[0x20]; 10044 10045 u8 cap_cell_size[0x10]; 10046 u8 cap_max_pg_buffers[0x8]; 10047 u8 cap_num_pool_supported[0x8]; 10048 10049 u8 reserved_at_240[0x8]; 10050 u8 cap_sbsr_stat_size[0x8]; 10051 u8 cap_max_tclass_data[0x8]; 10052 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10053 }; 10054 10055 struct mlx5_ifc_pbmc_reg_bits { 10056 u8 reserved_at_0[0x8]; 10057 u8 local_port[0x8]; 10058 u8 reserved_at_10[0x10]; 10059 10060 u8 xoff_timer_value[0x10]; 10061 u8 xoff_refresh[0x10]; 10062 10063 u8 reserved_at_40[0x9]; 10064 u8 fullness_threshold[0x7]; 10065 u8 port_buffer_size[0x10]; 10066 10067 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10068 10069 u8 reserved_at_2e0[0x80]; 10070 }; 10071 10072 struct mlx5_ifc_qtct_reg_bits { 10073 u8 reserved_at_0[0x8]; 10074 u8 port_number[0x8]; 10075 u8 reserved_at_10[0xd]; 10076 u8 prio[0x3]; 10077 10078 u8 reserved_at_20[0x1d]; 10079 u8 tclass[0x3]; 10080 }; 10081 10082 struct mlx5_ifc_mcia_reg_bits { 10083 u8 l[0x1]; 10084 u8 reserved_at_1[0x7]; 10085 u8 module[0x8]; 10086 u8 reserved_at_10[0x8]; 10087 u8 status[0x8]; 10088 10089 u8 i2c_device_address[0x8]; 10090 u8 page_number[0x8]; 10091 u8 device_address[0x10]; 10092 10093 u8 reserved_at_40[0x10]; 10094 u8 size[0x10]; 10095 10096 u8 reserved_at_60[0x20]; 10097 10098 u8 dword_0[0x20]; 10099 u8 dword_1[0x20]; 10100 u8 dword_2[0x20]; 10101 u8 dword_3[0x20]; 10102 u8 dword_4[0x20]; 10103 u8 dword_5[0x20]; 10104 u8 dword_6[0x20]; 10105 u8 dword_7[0x20]; 10106 u8 dword_8[0x20]; 10107 u8 dword_9[0x20]; 10108 u8 dword_10[0x20]; 10109 u8 dword_11[0x20]; 10110 }; 10111 10112 struct mlx5_ifc_dcbx_param_bits { 10113 u8 dcbx_cee_cap[0x1]; 10114 u8 dcbx_ieee_cap[0x1]; 10115 u8 dcbx_standby_cap[0x1]; 10116 u8 reserved_at_3[0x5]; 10117 u8 port_number[0x8]; 10118 u8 reserved_at_10[0xa]; 10119 u8 max_application_table_size[6]; 10120 u8 reserved_at_20[0x15]; 10121 u8 version_oper[0x3]; 10122 u8 reserved_at_38[5]; 10123 u8 version_admin[0x3]; 10124 u8 willing_admin[0x1]; 10125 u8 reserved_at_41[0x3]; 10126 u8 pfc_cap_oper[0x4]; 10127 u8 reserved_at_48[0x4]; 10128 u8 pfc_cap_admin[0x4]; 10129 u8 reserved_at_50[0x4]; 10130 u8 num_of_tc_oper[0x4]; 10131 u8 reserved_at_58[0x4]; 10132 u8 num_of_tc_admin[0x4]; 10133 u8 remote_willing[0x1]; 10134 u8 reserved_at_61[3]; 10135 u8 remote_pfc_cap[4]; 10136 u8 reserved_at_68[0x14]; 10137 u8 remote_num_of_tc[0x4]; 10138 u8 reserved_at_80[0x18]; 10139 u8 error[0x8]; 10140 u8 reserved_at_a0[0x160]; 10141 }; 10142 10143 struct mlx5_ifc_lagc_bits { 10144 u8 reserved_at_0[0x1d]; 10145 u8 lag_state[0x3]; 10146 10147 u8 reserved_at_20[0x14]; 10148 u8 tx_remap_affinity_2[0x4]; 10149 u8 reserved_at_38[0x4]; 10150 u8 tx_remap_affinity_1[0x4]; 10151 }; 10152 10153 struct mlx5_ifc_create_lag_out_bits { 10154 u8 status[0x8]; 10155 u8 reserved_at_8[0x18]; 10156 10157 u8 syndrome[0x20]; 10158 10159 u8 reserved_at_40[0x40]; 10160 }; 10161 10162 struct mlx5_ifc_create_lag_in_bits { 10163 u8 opcode[0x10]; 10164 u8 reserved_at_10[0x10]; 10165 10166 u8 reserved_at_20[0x10]; 10167 u8 op_mod[0x10]; 10168 10169 struct mlx5_ifc_lagc_bits ctx; 10170 }; 10171 10172 struct mlx5_ifc_modify_lag_out_bits { 10173 u8 status[0x8]; 10174 u8 reserved_at_8[0x18]; 10175 10176 u8 syndrome[0x20]; 10177 10178 u8 reserved_at_40[0x40]; 10179 }; 10180 10181 struct mlx5_ifc_modify_lag_in_bits { 10182 u8 opcode[0x10]; 10183 u8 reserved_at_10[0x10]; 10184 10185 u8 reserved_at_20[0x10]; 10186 u8 op_mod[0x10]; 10187 10188 u8 reserved_at_40[0x20]; 10189 u8 field_select[0x20]; 10190 10191 struct mlx5_ifc_lagc_bits ctx; 10192 }; 10193 10194 struct mlx5_ifc_query_lag_out_bits { 10195 u8 status[0x8]; 10196 u8 reserved_at_8[0x18]; 10197 10198 u8 syndrome[0x20]; 10199 10200 struct mlx5_ifc_lagc_bits ctx; 10201 }; 10202 10203 struct mlx5_ifc_query_lag_in_bits { 10204 u8 opcode[0x10]; 10205 u8 reserved_at_10[0x10]; 10206 10207 u8 reserved_at_20[0x10]; 10208 u8 op_mod[0x10]; 10209 10210 u8 reserved_at_40[0x40]; 10211 }; 10212 10213 struct mlx5_ifc_destroy_lag_out_bits { 10214 u8 status[0x8]; 10215 u8 reserved_at_8[0x18]; 10216 10217 u8 syndrome[0x20]; 10218 10219 u8 reserved_at_40[0x40]; 10220 }; 10221 10222 struct mlx5_ifc_destroy_lag_in_bits { 10223 u8 opcode[0x10]; 10224 u8 reserved_at_10[0x10]; 10225 10226 u8 reserved_at_20[0x10]; 10227 u8 op_mod[0x10]; 10228 10229 u8 reserved_at_40[0x40]; 10230 }; 10231 10232 struct mlx5_ifc_create_vport_lag_out_bits { 10233 u8 status[0x8]; 10234 u8 reserved_at_8[0x18]; 10235 10236 u8 syndrome[0x20]; 10237 10238 u8 reserved_at_40[0x40]; 10239 }; 10240 10241 struct mlx5_ifc_create_vport_lag_in_bits { 10242 u8 opcode[0x10]; 10243 u8 reserved_at_10[0x10]; 10244 10245 u8 reserved_at_20[0x10]; 10246 u8 op_mod[0x10]; 10247 10248 u8 reserved_at_40[0x40]; 10249 }; 10250 10251 struct mlx5_ifc_destroy_vport_lag_out_bits { 10252 u8 status[0x8]; 10253 u8 reserved_at_8[0x18]; 10254 10255 u8 syndrome[0x20]; 10256 10257 u8 reserved_at_40[0x40]; 10258 }; 10259 10260 struct mlx5_ifc_destroy_vport_lag_in_bits { 10261 u8 opcode[0x10]; 10262 u8 reserved_at_10[0x10]; 10263 10264 u8 reserved_at_20[0x10]; 10265 u8 op_mod[0x10]; 10266 10267 u8 reserved_at_40[0x40]; 10268 }; 10269 10270 struct mlx5_ifc_alloc_memic_in_bits { 10271 u8 opcode[0x10]; 10272 u8 reserved_at_10[0x10]; 10273 10274 u8 reserved_at_20[0x10]; 10275 u8 op_mod[0x10]; 10276 10277 u8 reserved_at_30[0x20]; 10278 10279 u8 reserved_at_40[0x18]; 10280 u8 log_memic_addr_alignment[0x8]; 10281 10282 u8 range_start_addr[0x40]; 10283 10284 u8 range_size[0x20]; 10285 10286 u8 memic_size[0x20]; 10287 }; 10288 10289 struct mlx5_ifc_alloc_memic_out_bits { 10290 u8 status[0x8]; 10291 u8 reserved_at_8[0x18]; 10292 10293 u8 syndrome[0x20]; 10294 10295 u8 memic_start_addr[0x40]; 10296 }; 10297 10298 struct mlx5_ifc_dealloc_memic_in_bits { 10299 u8 opcode[0x10]; 10300 u8 reserved_at_10[0x10]; 10301 10302 u8 reserved_at_20[0x10]; 10303 u8 op_mod[0x10]; 10304 10305 u8 reserved_at_40[0x40]; 10306 10307 u8 memic_start_addr[0x40]; 10308 10309 u8 memic_size[0x20]; 10310 10311 u8 reserved_at_e0[0x20]; 10312 }; 10313 10314 struct mlx5_ifc_dealloc_memic_out_bits { 10315 u8 status[0x8]; 10316 u8 reserved_at_8[0x18]; 10317 10318 u8 syndrome[0x20]; 10319 10320 u8 reserved_at_40[0x40]; 10321 }; 10322 10323 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10324 u8 opcode[0x10]; 10325 u8 uid[0x10]; 10326 10327 u8 vhca_tunnel_id[0x10]; 10328 u8 obj_type[0x10]; 10329 10330 u8 obj_id[0x20]; 10331 10332 u8 reserved_at_60[0x20]; 10333 }; 10334 10335 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10336 u8 status[0x8]; 10337 u8 reserved_at_8[0x18]; 10338 10339 u8 syndrome[0x20]; 10340 10341 u8 obj_id[0x20]; 10342 10343 u8 reserved_at_60[0x20]; 10344 }; 10345 10346 struct mlx5_ifc_umem_bits { 10347 u8 reserved_at_0[0x80]; 10348 10349 u8 reserved_at_80[0x1b]; 10350 u8 log_page_size[0x5]; 10351 10352 u8 page_offset[0x20]; 10353 10354 u8 num_of_mtt[0x40]; 10355 10356 struct mlx5_ifc_mtt_bits mtt[]; 10357 }; 10358 10359 struct mlx5_ifc_uctx_bits { 10360 u8 cap[0x20]; 10361 10362 u8 reserved_at_20[0x160]; 10363 }; 10364 10365 struct mlx5_ifc_sw_icm_bits { 10366 u8 modify_field_select[0x40]; 10367 10368 u8 reserved_at_40[0x18]; 10369 u8 log_sw_icm_size[0x8]; 10370 10371 u8 reserved_at_60[0x20]; 10372 10373 u8 sw_icm_start_addr[0x40]; 10374 10375 u8 reserved_at_c0[0x140]; 10376 }; 10377 10378 struct mlx5_ifc_geneve_tlv_option_bits { 10379 u8 modify_field_select[0x40]; 10380 10381 u8 reserved_at_40[0x18]; 10382 u8 geneve_option_fte_index[0x8]; 10383 10384 u8 option_class[0x10]; 10385 u8 option_type[0x8]; 10386 u8 reserved_at_78[0x3]; 10387 u8 option_data_length[0x5]; 10388 10389 u8 reserved_at_80[0x180]; 10390 }; 10391 10392 struct mlx5_ifc_create_umem_in_bits { 10393 u8 opcode[0x10]; 10394 u8 uid[0x10]; 10395 10396 u8 reserved_at_20[0x10]; 10397 u8 op_mod[0x10]; 10398 10399 u8 reserved_at_40[0x40]; 10400 10401 struct mlx5_ifc_umem_bits umem; 10402 }; 10403 10404 struct mlx5_ifc_create_umem_out_bits { 10405 u8 status[0x8]; 10406 u8 reserved_at_8[0x18]; 10407 10408 u8 syndrome[0x20]; 10409 10410 u8 reserved_at_40[0x8]; 10411 u8 umem_id[0x18]; 10412 10413 u8 reserved_at_60[0x20]; 10414 }; 10415 10416 struct mlx5_ifc_destroy_umem_in_bits { 10417 u8 opcode[0x10]; 10418 u8 uid[0x10]; 10419 10420 u8 reserved_at_20[0x10]; 10421 u8 op_mod[0x10]; 10422 10423 u8 reserved_at_40[0x8]; 10424 u8 umem_id[0x18]; 10425 10426 u8 reserved_at_60[0x20]; 10427 }; 10428 10429 struct mlx5_ifc_destroy_umem_out_bits { 10430 u8 status[0x8]; 10431 u8 reserved_at_8[0x18]; 10432 10433 u8 syndrome[0x20]; 10434 10435 u8 reserved_at_40[0x40]; 10436 }; 10437 10438 struct mlx5_ifc_create_uctx_in_bits { 10439 u8 opcode[0x10]; 10440 u8 reserved_at_10[0x10]; 10441 10442 u8 reserved_at_20[0x10]; 10443 u8 op_mod[0x10]; 10444 10445 u8 reserved_at_40[0x40]; 10446 10447 struct mlx5_ifc_uctx_bits uctx; 10448 }; 10449 10450 struct mlx5_ifc_create_uctx_out_bits { 10451 u8 status[0x8]; 10452 u8 reserved_at_8[0x18]; 10453 10454 u8 syndrome[0x20]; 10455 10456 u8 reserved_at_40[0x10]; 10457 u8 uid[0x10]; 10458 10459 u8 reserved_at_60[0x20]; 10460 }; 10461 10462 struct mlx5_ifc_destroy_uctx_in_bits { 10463 u8 opcode[0x10]; 10464 u8 reserved_at_10[0x10]; 10465 10466 u8 reserved_at_20[0x10]; 10467 u8 op_mod[0x10]; 10468 10469 u8 reserved_at_40[0x10]; 10470 u8 uid[0x10]; 10471 10472 u8 reserved_at_60[0x20]; 10473 }; 10474 10475 struct mlx5_ifc_destroy_uctx_out_bits { 10476 u8 status[0x8]; 10477 u8 reserved_at_8[0x18]; 10478 10479 u8 syndrome[0x20]; 10480 10481 u8 reserved_at_40[0x40]; 10482 }; 10483 10484 struct mlx5_ifc_create_sw_icm_in_bits { 10485 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10486 struct mlx5_ifc_sw_icm_bits sw_icm; 10487 }; 10488 10489 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10490 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10491 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10492 }; 10493 10494 struct mlx5_ifc_mtrc_string_db_param_bits { 10495 u8 string_db_base_address[0x20]; 10496 10497 u8 reserved_at_20[0x8]; 10498 u8 string_db_size[0x18]; 10499 }; 10500 10501 struct mlx5_ifc_mtrc_cap_bits { 10502 u8 trace_owner[0x1]; 10503 u8 trace_to_memory[0x1]; 10504 u8 reserved_at_2[0x4]; 10505 u8 trc_ver[0x2]; 10506 u8 reserved_at_8[0x14]; 10507 u8 num_string_db[0x4]; 10508 10509 u8 first_string_trace[0x8]; 10510 u8 num_string_trace[0x8]; 10511 u8 reserved_at_30[0x28]; 10512 10513 u8 log_max_trace_buffer_size[0x8]; 10514 10515 u8 reserved_at_60[0x20]; 10516 10517 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10518 10519 u8 reserved_at_280[0x180]; 10520 }; 10521 10522 struct mlx5_ifc_mtrc_conf_bits { 10523 u8 reserved_at_0[0x1c]; 10524 u8 trace_mode[0x4]; 10525 u8 reserved_at_20[0x18]; 10526 u8 log_trace_buffer_size[0x8]; 10527 u8 trace_mkey[0x20]; 10528 u8 reserved_at_60[0x3a0]; 10529 }; 10530 10531 struct mlx5_ifc_mtrc_stdb_bits { 10532 u8 string_db_index[0x4]; 10533 u8 reserved_at_4[0x4]; 10534 u8 read_size[0x18]; 10535 u8 start_offset[0x20]; 10536 u8 string_db_data[]; 10537 }; 10538 10539 struct mlx5_ifc_mtrc_ctrl_bits { 10540 u8 trace_status[0x2]; 10541 u8 reserved_at_2[0x2]; 10542 u8 arm_event[0x1]; 10543 u8 reserved_at_5[0xb]; 10544 u8 modify_field_select[0x10]; 10545 u8 reserved_at_20[0x2b]; 10546 u8 current_timestamp52_32[0x15]; 10547 u8 current_timestamp31_0[0x20]; 10548 u8 reserved_at_80[0x180]; 10549 }; 10550 10551 struct mlx5_ifc_host_params_context_bits { 10552 u8 host_number[0x8]; 10553 u8 reserved_at_8[0x7]; 10554 u8 host_pf_disabled[0x1]; 10555 u8 host_num_of_vfs[0x10]; 10556 10557 u8 host_total_vfs[0x10]; 10558 u8 host_pci_bus[0x10]; 10559 10560 u8 reserved_at_40[0x10]; 10561 u8 host_pci_device[0x10]; 10562 10563 u8 reserved_at_60[0x10]; 10564 u8 host_pci_function[0x10]; 10565 10566 u8 reserved_at_80[0x180]; 10567 }; 10568 10569 struct mlx5_ifc_query_esw_functions_in_bits { 10570 u8 opcode[0x10]; 10571 u8 reserved_at_10[0x10]; 10572 10573 u8 reserved_at_20[0x10]; 10574 u8 op_mod[0x10]; 10575 10576 u8 reserved_at_40[0x40]; 10577 }; 10578 10579 struct mlx5_ifc_query_esw_functions_out_bits { 10580 u8 status[0x8]; 10581 u8 reserved_at_8[0x18]; 10582 10583 u8 syndrome[0x20]; 10584 10585 u8 reserved_at_40[0x40]; 10586 10587 struct mlx5_ifc_host_params_context_bits host_params_context; 10588 10589 u8 reserved_at_280[0x180]; 10590 u8 host_sf_enable[][0x40]; 10591 }; 10592 10593 struct mlx5_ifc_sf_partition_bits { 10594 u8 reserved_at_0[0x10]; 10595 u8 log_num_sf[0x8]; 10596 u8 log_sf_bar_size[0x8]; 10597 }; 10598 10599 struct mlx5_ifc_query_sf_partitions_out_bits { 10600 u8 status[0x8]; 10601 u8 reserved_at_8[0x18]; 10602 10603 u8 syndrome[0x20]; 10604 10605 u8 reserved_at_40[0x18]; 10606 u8 num_sf_partitions[0x8]; 10607 10608 u8 reserved_at_60[0x20]; 10609 10610 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10611 }; 10612 10613 struct mlx5_ifc_query_sf_partitions_in_bits { 10614 u8 opcode[0x10]; 10615 u8 reserved_at_10[0x10]; 10616 10617 u8 reserved_at_20[0x10]; 10618 u8 op_mod[0x10]; 10619 10620 u8 reserved_at_40[0x40]; 10621 }; 10622 10623 struct mlx5_ifc_dealloc_sf_out_bits { 10624 u8 status[0x8]; 10625 u8 reserved_at_8[0x18]; 10626 10627 u8 syndrome[0x20]; 10628 10629 u8 reserved_at_40[0x40]; 10630 }; 10631 10632 struct mlx5_ifc_dealloc_sf_in_bits { 10633 u8 opcode[0x10]; 10634 u8 reserved_at_10[0x10]; 10635 10636 u8 reserved_at_20[0x10]; 10637 u8 op_mod[0x10]; 10638 10639 u8 reserved_at_40[0x10]; 10640 u8 function_id[0x10]; 10641 10642 u8 reserved_at_60[0x20]; 10643 }; 10644 10645 struct mlx5_ifc_alloc_sf_out_bits { 10646 u8 status[0x8]; 10647 u8 reserved_at_8[0x18]; 10648 10649 u8 syndrome[0x20]; 10650 10651 u8 reserved_at_40[0x40]; 10652 }; 10653 10654 struct mlx5_ifc_alloc_sf_in_bits { 10655 u8 opcode[0x10]; 10656 u8 reserved_at_10[0x10]; 10657 10658 u8 reserved_at_20[0x10]; 10659 u8 op_mod[0x10]; 10660 10661 u8 reserved_at_40[0x10]; 10662 u8 function_id[0x10]; 10663 10664 u8 reserved_at_60[0x20]; 10665 }; 10666 10667 struct mlx5_ifc_affiliated_event_header_bits { 10668 u8 reserved_at_0[0x10]; 10669 u8 obj_type[0x10]; 10670 10671 u8 obj_id[0x20]; 10672 }; 10673 10674 enum { 10675 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10676 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10677 }; 10678 10679 enum { 10680 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10681 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10682 }; 10683 10684 enum { 10685 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10686 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10687 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10688 }; 10689 10690 struct mlx5_ifc_ipsec_obj_bits { 10691 u8 modify_field_select[0x40]; 10692 u8 full_offload[0x1]; 10693 u8 reserved_at_41[0x1]; 10694 u8 esn_en[0x1]; 10695 u8 esn_overlap[0x1]; 10696 u8 reserved_at_44[0x2]; 10697 u8 icv_length[0x2]; 10698 u8 reserved_at_48[0x4]; 10699 u8 aso_return_reg[0x4]; 10700 u8 reserved_at_50[0x10]; 10701 10702 u8 esn_msb[0x20]; 10703 10704 u8 reserved_at_80[0x8]; 10705 u8 dekn[0x18]; 10706 10707 u8 salt[0x20]; 10708 10709 u8 implicit_iv[0x40]; 10710 10711 u8 reserved_at_100[0x700]; 10712 }; 10713 10714 struct mlx5_ifc_create_ipsec_obj_in_bits { 10715 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10716 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10717 }; 10718 10719 enum { 10720 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10721 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10722 }; 10723 10724 struct mlx5_ifc_query_ipsec_obj_out_bits { 10725 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10726 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10727 }; 10728 10729 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10730 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10731 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10732 }; 10733 10734 struct mlx5_ifc_encryption_key_obj_bits { 10735 u8 modify_field_select[0x40]; 10736 10737 u8 reserved_at_40[0x14]; 10738 u8 key_size[0x4]; 10739 u8 reserved_at_58[0x4]; 10740 u8 key_type[0x4]; 10741 10742 u8 reserved_at_60[0x8]; 10743 u8 pd[0x18]; 10744 10745 u8 reserved_at_80[0x180]; 10746 u8 key[8][0x20]; 10747 10748 u8 reserved_at_300[0x500]; 10749 }; 10750 10751 struct mlx5_ifc_create_encryption_key_in_bits { 10752 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10753 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10754 }; 10755 10756 enum { 10757 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10758 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10759 }; 10760 10761 enum { 10762 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10763 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10764 }; 10765 10766 struct mlx5_ifc_tls_static_params_bits { 10767 u8 const_2[0x2]; 10768 u8 tls_version[0x4]; 10769 u8 const_1[0x2]; 10770 u8 reserved_at_8[0x14]; 10771 u8 encryption_standard[0x4]; 10772 10773 u8 reserved_at_20[0x20]; 10774 10775 u8 initial_record_number[0x40]; 10776 10777 u8 resync_tcp_sn[0x20]; 10778 10779 u8 gcm_iv[0x20]; 10780 10781 u8 implicit_iv[0x40]; 10782 10783 u8 reserved_at_100[0x8]; 10784 u8 dek_index[0x18]; 10785 10786 u8 reserved_at_120[0xe0]; 10787 }; 10788 10789 struct mlx5_ifc_tls_progress_params_bits { 10790 u8 next_record_tcp_sn[0x20]; 10791 10792 u8 hw_resync_tcp_sn[0x20]; 10793 10794 u8 record_tracker_state[0x2]; 10795 u8 auth_state[0x2]; 10796 u8 reserved_at_44[0x4]; 10797 u8 hw_offset_record_number[0x18]; 10798 }; 10799 10800 enum { 10801 MLX5_MTT_PERM_READ = 1 << 0, 10802 MLX5_MTT_PERM_WRITE = 1 << 1, 10803 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10804 }; 10805 10806 #endif /* MLX5_IFC_H */ 10807