| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pllv2.c | 17 #define MXC_PLL_DP_CTL 0x00
18 #define MXC_PLL_DP_CONFIG 0x04
19 #define MXC_PLL_DP_OP 0x08
20 #define MXC_PLL_DP_MFD 0x0C
21 #define MXC_PLL_DP_MFN 0x10
22 #define MXC_PLL_DP_MFNMINUS 0x14
23 #define MXC_PLL_DP_MFNPLUS 0x18
24 #define MXC_PLL_DP_HFS_OP 0x1C
25 #define MXC_PLL_DP_HFS_MFD 0x20
26 #define MXC_PLL_DP_HFS_MFN 0x24
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | dart.h | 11 #define DART_CNTL 0
14 #define DART_EXCP_U3 0x10
16 #define DART_TAGS_U3 0x1000
19 #define DART_BASE_U4 0x10
20 #define DART_SIZE_U4 0x20
21 #define DART_EXCP_U4 0x30
22 #define DART_TAGS_U4 0x1000
27 #define DART_CNTL_U3_BASE_MASK 0xfffff
29 #define DART_CNTL_U3_FLUSHTLB 0x400
30 #define DART_CNTL_U3_ENABLE 0x200
[all …]
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| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | sh7785lcr.h | 11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | snps,dw-wdt.yaml | 52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | mv64x60_edac.h | 15 #define MV64x60_REVISION " Ver: 2.0.0"
25 #define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
26 #define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
27 #define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
28 #define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
29 #define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
30 #define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
31 #define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
33 #define MV64x60_CPU_CAUSE_MASK 0x07ffffff
36 #define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
[all …]
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| /kernel/linux/linux-5.10/drivers/scsi/ |
| D | gvp11.c | 43 static int gvp11_xfer_mask = 0;
59 static int scsi_alloc_out_of_range = 0; in dma_setup()
63 wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; in dma_setup()
78 wh->dma_bounce_len = 0; in dma_setup()
102 wh->dma_bounce_len = 0; in dma_setup()
135 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
143 return 0; in dma_setup()
170 wh->dma_bounce_len = 0; in dma_stop()
215 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
226 if (*scmd_3393 != q) /* and so should the image at 0x1f */ in check_wd33c93()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | dbell.h | 19 #define PPC_DBELL_MSG_BRDCAST (0x04000000)
20 #define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
21 #define PPC_DBELL_TYPE_MASK PPC_DBELL_TYPE(0xf)
23 #define PPC_DBELL_PIR_MASK 0x3fff
25 PPC_DBELL = 0, /* doorbell */
39 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGSND(%1), PPC_MSGSNDP(%1), %0) in _ppc_msgsnd()
53 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGSYNC " ; lwsync", "", %0) in ppc_msgsync()
59 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGCLR(%1), PPC_MSGCLRP(%1), %0) in _ppc_msgclr()
76 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); in _ppc_msgsnd()
97 (tag & 0x07ffffff); in ppc_msgsnd()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | si.c | 59 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
60 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
61 mmDB_DEBUG, 0xffffffff, 0x00000000,
62 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
63 mmDB_DEBUG3, 0x0002021c, 0x00020200,
64 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
65 0x340c, 0x000000c0, 0x00800040,
66 0x360c, 0x000000c0, 0x00800040,
67 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
68 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
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| D | cik.c | 129 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
140 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
169 0xc200, 0xe0ffffff, 0xe0000000
174 0x31dc, 0xffffffff, 0x00000800,
175 0x31dd, 0xffffffff, 0x00000800,
176 0x31e6, 0xffffffff, 0x00007fbf,
177 0x31e7, 0xffffffff, 0x00007faf
182 0xcd5, 0x00000333, 0x00000333,
183 0xcd4, 0x000c0fc0, 0x00040200,
184 0x2684, 0x00010000, 0x00058208,
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/ |
| D | sc.h | 13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | carminefb_regs.h | 5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
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| /kernel/linux/linux-5.10/drivers/char/xilinx_hwicap/ |
| D | xilinx_hwicap.h | 43 u32 write_buffer_in_use; /* Always in [0,3] */
45 u32 read_buffer_in_use; /* Always in [0,3] */
65 * Return 0 if successful.
70 * Return 0 if successful.
75 * D8 - 0 = configuration error
78 * D5 - 0 = abort in progress
101 #define XHI_PAD_FRAMES 0x1
104 #define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
105 #define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
106 #define XHI_TYPE_MASK 0x7
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/musb/ |
| D | tusb6010.h | 12 /* VLYNQ control register. 32-bit at offset 0x000 */
13 #define TUSB_VLYNQ_CTRL 0x004
15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
16 #define TUSB_BASE_OFFSET 0x400
18 /* FIFO registers 32-bit at offset 0x600 */
19 #define TUSB_FIFO_BASE 0x600
21 /* Device System & Control registers. 32-bit at offset 0x800 */
22 #define TUSB_SYS_REG_BASE 0x800
24 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
28 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
[all …]
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | perf_images.h | 27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| D | vmmnv44.c | 30 u32 pteo = (ptei << 2) & ~0x0000000f; in nv44_vmm_pgt_fill()
33 tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0); in nv44_vmm_pgt_fill()
34 tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4); in nv44_vmm_pgt_fill()
35 tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8); in nv44_vmm_pgt_fill()
36 tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc); in nv44_vmm_pgt_fill()
40 switch (ptei++ & 0x3) { in nv44_vmm_pgt_fill()
41 case 0: in nv44_vmm_pgt_fill()
42 tmp[0] &= ~0x07ffffff; in nv44_vmm_pgt_fill()
43 tmp[0] |= addr; in nv44_vmm_pgt_fill()
46 tmp[0] &= ~0xf8000000; in nv44_vmm_pgt_fill()
[all …]
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| /kernel/linux/linux-5.10/drivers/message/fusion/lsi/ |
| D | mpi_lan.h | 58 SGE_MPI_UNION SG_List[1]; /* 0Ch */
73 U16 Reserved3; /* 0Ch */
74 U16 IOCStatus; /* 0Eh */
92 U32 BucketCount; /* 0Ch */
108 U16 Reserved3; /* 0Ch */
109 U16 IOCStatus; /* 0Eh */
143 U16 Reserved3; /* 0Ch */
144 U16 IOCStatus; /* 0Eh */
154 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF)
155 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0)
[all …]
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| /kernel/linux/linux-5.10/arch/parisc/math-emu/ |
| D | decode_exc.c | 41 #define Fpustatus_register Fpu_register[0]
45 #define NOTRAP 0
58 #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
81 if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
86 aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
87 Fpu_register[0] |= bflags; \
104 * need to restore Fpu_register[0] in decode_fpu()
107 bflags=(Fpu_register[0] & 0xf8000000); in decode_fpu()
108 Fpu_register[0] &= 0x07ffffff; in decode_fpu()
139 * codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds in decode_fpu()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-au1x00/ |
| D | au1xxx_dbdma.h | 50 #define DDMA_CONFIG_AL (1 << 0)
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
75 #define DDMA_CFG_EN (1 << 0) /* Channel enable */
82 #define DDMA_IRQ_IN (1 << 0)
86 #define DDMA_STAT_H (1 << 0) /* Channel Halted */
112 #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
[all …]
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| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | core_mcpcia.h | 58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x058
[all …]
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| D | core_cia.h | 48 * 00 00 Byte 1110 0x000
49 * 01 00 Byte 1101 0x020
50 * 10 00 Byte 1011 0x040
51 * 11 00 Byte 0111 0x060
53 * 00 01 Word 1100 0x008
54 * 01 01 Word 1001 0x028 <= Not supported in this code.
55 * 10 01 Word 0011 0x048
57 * 00 10 Tribyte 1000 0x010
58 * 01 10 Tribyte 0001 0x030
60 * 10 11 Longword 0000 0x058
[all …]
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| D | core_t2.h | 25 #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */
29 #define _GAMMA_BIAS 0x8000000000UL
36 #define GAMMA_BIAS 0
42 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
43 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
44 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
45 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
47 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
48 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
49 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | ni.c | 69 0x98fc,
70 0x98f0,
71 0x9834,
72 0x9838,
73 0x9870,
74 0x9874,
75 0x8a14,
76 0x8b24,
77 0x8bcc,
78 0x8b10,
[all …]
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| D | si.c | 166 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
167 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
168 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
172 (0x8000 << 16) | (0x98f4 >> 2),
173 0x00000000,
174 (0x8040 << 16) | (0x98f4 >> 2),
175 0x00000000,
176 (0x8000 << 16) | (0xe80 >> 2),
177 0x00000000,
178 (0x8040 << 16) | (0xe80 >> 2),
[all …]
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