Home
last modified time | relevance | path

Searched +full:0 +full:x140 (Results 1 – 25 of 443) sorted by relevance

12345678910>>...18

/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mn-var-som-symphony.dts18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
53 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
66 pinctrl-0 = <&pinctrl_i2c2>;
71 reg = <0x20>;
74 pinctrl-0 = <&pinctrl_pca9534>;
105 reg = <0x3d>;
109 pinctrl-0 = <&pinctrl_ptn5150>;
118 reg = <0x38>;
120 pinctrl-0 = <&pinctrl_captouch>;
132 reg = <0x68>;
[all …]
Dimx8mm-var-som-symphony.dts17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
76 pinctrl-0 = <&pinctrl_i2c2>;
81 reg = <0x20>;
84 pinctrl-0 = <&pinctrl_pca9534>;
115 reg = <0x3d>;
119 pinctrl-0 = <&pinctrl_ptn5150>;
128 reg = <0x38>;
130 pinctrl-0 = <&pinctrl_captouch>;
[all …]
Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
53 pinctrl-0 = <&pinctrl_ecspi1>;
55 <&gpio1 0 GPIO_ACTIVE_LOW>;
61 touchscreen@0 {
62 reg = <0>;
65 pinctrl-0 = <&pinctrl_restouch>;
89 pinctrl-0 = <&pinctrl_fec1>;
99 #size-cells = <0>;
113 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mm-var-som.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
25 pinctrl-0 = <&pinctrl_reg_eth_phy>;
72 pinctrl-0 = <&pinctrl_ecspi1>;
74 <&gpio1 0 GPIO_ACTIVE_LOW>;
80 touchscreen@0 {
81 reg = <0>;
84 pinctrl-0 = <&pinctrl_restouch>;
108 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
132 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx8mp-evk.dts21 pinctrl-0 = <&pinctrl_gpio_led>;
32 reg = <0x0 0x40000000 0 0xc0000000>,
33 <0x1 0x00000000 0 0xc0000000>;
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
50 pinctrl-0 = <&pinctrl_fec>;
58 #size-cells = <0>;
74 pinctrl-0 = <&pinctrl_i2c3>;
79 reg = <0x20>;
92 pinctrl-0 = <&pinctrl_uart2>;
100 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
[all …]
Dimx8mm-beacon-som.dtsi10 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
19 reg = <0x0 0x40000000 0 0x80000000>;
49 pinctrl-0 = <&pinctrl_fec1>;
57 #size-cells = <0>;
59 ethphy0: ethernet-phy@0 {
61 reg = <0>;
69 pinctrl-0 = <&pinctrl_i2c1>;
74 reg = <0x4b>;
76 pinctrl-0 = <&pinctrl_pmic>;
184 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
Dimx8mm-beacon-baseboard.dtsi30 pinctrl-0 = <&pinctrl_led3>;
72 pinctrl-0 = <&pinctrl_espi2>;
76 eeprom@0 {
78 reg = <0>;
91 pinctrl-0 = <&pinctrl_i2c2>;
98 pinctrl-0 = <&pinctrl_i2c4>;
103 reg = <0x1a>;
115 0x0000 /* 0:Default */
116 0x0000 /* 1:Default */
117 0x0000 /* 2:FN_DMICCLK */
[all …]
Dimx8mn-evk.dtsi17 pinctrl-0 = <&pinctrl_gpio_led>;
28 reg = <0x0 0x40000000 0 0x80000000>;
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
45 pinctrl-0 = <&pinctrl_fec1>;
53 #size-cells = <0>;
55 ethphy0: ethernet-phy@0 {
57 reg = <0>;
65 pinctrl-0 = <&pinctrl_i2c1>;
72 pinctrl-0 = <&pinctrl_i2c2>;
78 pinctrl-0 = <&pinctrl_typec1>;
[all …]
/kernel/linux/linux-5.10/drivers/media/usb/go7007/
Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/amlogic/
Damlogic,meson-gx-ao-secure.yaml52 reg = <0x140 0x140>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mm-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
Dfsl,imx8mn-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/kernel/linux/linux-5.10/arch/mips/pci/
Dpci-vr41xx.h12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-of-sparx5.c22 #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
27 #define CPU_REGS_PROC_CTRL (0x2C * 4)
33 #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
34 #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
35 #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
37 #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value); in sparx5_set_cacheable()
109 pr_debug("%s: Set EMMC_CTRL: 0x%08x\n", in sdhci_sparx5_set_emmc()
152 .quirks = 0,
198 (value > 0 && value <= MSHC_DLY_CC_MAX)) in sdhci_sparx5_probe()
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/kernel/linux/linux-5.10/drivers/soc/rockchip/
Dgrf.c28 #define RK3036_GRF_SOC_CON0 0x140
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
43 #define RK3128_GRF_SOC_CON0 0x140
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
54 #define RK3228_GRF_SOC_CON6 0x418
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
65 #define RK3288_GRF_SOC_CON0 0x244
66 #define RK3288_GRF_SOC_CON2 0x24c
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
[all …]
/kernel/linux/linux-5.10/drivers/soc/renesas/
Dr8a77995-sysc.c15 { "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
18 { "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
Dr8a7779-sysc.c15 { "always-on", 0, 0, R8A7779_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "arm1", 0x40, 1, R8A7779_PD_ARM1, R8A7779_PD_ALWAYS_ON,
18 { "arm2", 0x40, 2, R8A7779_PD_ARM2, R8A7779_PD_ALWAYS_ON,
20 { "arm3", 0x40, 3, R8A7779_PD_ARM3, R8A7779_PD_ALWAYS_ON,
22 { "sgx", 0xc0, 0, R8A7779_PD_SGX, R8A7779_PD_ALWAYS_ON },
23 { "vdp", 0x100, 0, R8A7779_PD_VDP, R8A7779_PD_ALWAYS_ON },
24 { "imp", 0x140, 0, R8A7779_PD_IMP, R8A7779_PD_ALWAYS_ON },
Dr8a7792-sysc.c16 { "always-on", 0, 0, R8A7792_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
17 { "ca15-scu", 0x180, 0, R8A7792_PD_CA15_SCU, R8A7792_PD_ALWAYS_ON,
19 { "ca15-cpu0", 0x40, 0, R8A7792_PD_CA15_CPU0, R8A7792_PD_CA15_SCU,
21 { "ca15-cpu1", 0x40, 1, R8A7792_PD_CA15_CPU1, R8A7792_PD_CA15_SCU,
23 { "sgx", 0xc0, 0, R8A7792_PD_SGX, R8A7792_PD_ALWAYS_ON },
24 { "imp", 0x140, 0, R8A7792_PD_IMP, R8A7792_PD_ALWAYS_ON },
Dr8a77970-sysc.c16 { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
17 { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON,
19 { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
21 { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
23 { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
24 { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR },
25 { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR },
26 { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
27 { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
28 { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR },
[all …]
Dr8a7790-sysc.c15 { "always-on", 0, 0, R8A7790_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
16 { "ca15-scu", 0x180, 0, R8A7790_PD_CA15_SCU, R8A7790_PD_ALWAYS_ON,
18 { "ca15-cpu0", 0x40, 0, R8A7790_PD_CA15_CPU0, R8A7790_PD_CA15_SCU,
20 { "ca15-cpu1", 0x40, 1, R8A7790_PD_CA15_CPU1, R8A7790_PD_CA15_SCU,
22 { "ca15-cpu2", 0x40, 2, R8A7790_PD_CA15_CPU2, R8A7790_PD_CA15_SCU,
24 { "ca15-cpu3", 0x40, 3, R8A7790_PD_CA15_CPU3, R8A7790_PD_CA15_SCU,
26 { "ca7-scu", 0x100, 0, R8A7790_PD_CA7_SCU, R8A7790_PD_ALWAYS_ON,
28 { "ca7-cpu0", 0x1c0, 0, R8A7790_PD_CA7_CPU0, R8A7790_PD_CA7_SCU,
30 { "ca7-cpu1", 0x1c0, 1, R8A7790_PD_CA7_CPU1, R8A7790_PD_CA7_SCU,
32 { "ca7-cpu2", 0x1c0, 2, R8A7790_PD_CA7_CPU2, R8A7790_PD_CA7_SCU,
[all …]
/kernel/linux/linux-5.10/arch/sparc/lib/
Dbzero.S14 and %o1, 0xff, %o3
30 prefetch [%o0 + 0x000], #n_writes
31 andcc %o0, 0x3, %g0
33 1: stb %o2, [%o0 + 0x00]
35 andcc %o0, 0x3, %g0
38 2: andcc %o0, 0x7, %g0
40 stw %o2, [%o0 + 0x00]
43 3: and %o1, 0x38, %g1
44 cmp %o1, 0x40
45 andn %o1, 0x3f, %o4
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Dphy_ac.h7 #define B43_PHY_AC_BBCFG 0x001
8 #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
9 #define B43_PHY_AC_BANDCTL 0x003 /* Band control */
10 #define B43_PHY_AC_BANDCTL_5GHZ 0x0001
11 #define B43_PHY_AC_TABLE_ID 0x00d
12 #define B43_PHY_AC_TABLE_OFFSET 0x00e
13 #define B43_PHY_AC_TABLE_DATA1 0x00f
14 #define B43_PHY_AC_TABLE_DATA2 0x010
15 #define B43_PHY_AC_TABLE_DATA3 0x011
16 #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
[all …]
Dradio_2059.h9 #define R2059_C1 0x000
10 #define R2059_C2 0x400
11 #define R2059_C3 0x800
12 #define R2059_ALL 0xC00
14 #define R2059_RCAL_CONFIG 0x004
15 #define R2059_RFPLL_MASTER 0x011
16 #define R2059_RFPLL_MISC_EN 0x02b
17 #define R2059_RFPLL_MISC_CAL_RESETN 0x02e
18 #define R2059_XTAL_CONFIG2 0x0c0
19 #define R2059_RCCAL_START_R1_Q1_P1 0x13c
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]

12345678910>>...18