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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dmpc512x-dma.txt24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
/kernel/linux/linux-5.10/arch/arm/mach-mmp/
Dregs-timers.h11 #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
12 #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
14 #define TMR_CCR (0x0000)
15 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
16 #define TMR_CR(n) (0x0028 + ((n) << 2))
17 #define TMR_SR(n) (0x0034 + ((n) << 2))
18 #define TMR_IER(n) (0x0040 + ((n) << 2))
19 #define TMR_PLVR(n) (0x004c + ((n) << 2))
20 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
21 #define TMR_WMER (0x0064)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8916.yaml54 reg = <0x00400000 0x62000>;
63 reg = <0x00500000 0x11000>;
72 reg = <0x00580000 0x14000>;
Dinterconnect.txt30 reg = <0x580000 0x14000>;
83 cpu@0 {
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/marvell/
Darmada-37xx.txt34 reg = <0x14000 0x60>;
49 reg = <0x11500 0x40>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/
Dti,j721e-ufs.yaml49 "^ufs@[0-9a-f]+$":
69 reg = <0x0 0x4e80000 0x0 0x100>;
75 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
81 reg = <0x0 0x4000 0x0 0x10000>;
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/kernel/linux/linux-5.10/drivers/remoteproc/
Dmtk_common.h15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
Dgef_ppc9a.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
[all …]
Dgef_sbc610.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
[all …]
Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/kernel/linux/linux-5.10/sound/soc/intel/atom/sst/
Dsst_acpi.c38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
/kernel/linux/linux-5.10/sound/soc/amd/
Dacp.h8 #define ACP_PAGE_SIZE_4K_ENABLE 0x02
11 #define ACP_CAPTURE_PTE_OFFSET 0
14 #define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
15 #define ACP_ST_CAPTURE_PTE_OFFSET 0x00
16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08
17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c
19 #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
20 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
22 #define ACP_PHYSICAL_BASE 0x14000
32 #define ACP_SRAM_BANK_1_ADDRESS 0x4002000
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/tegra/
Dpinctrl-tegra194.c89 .mux_bit = 0, \
101 .parked_bitmask = 0
104 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
106 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
127 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
129 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
/kernel/linux/linux-5.10/arch/arm/mach-davinci/include/mach/
Dda8xx.h52 #define DA8XX_CP_INTC_BASE 0xfffee000
56 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
58 #define DA8XX_JTAG_ID_REG 0x18
59 #define DA8XX_HOST1CFG_REG 0x44
60 #define DA8XX_CHIPSIG_REG 0x174
61 #define DA8XX_CFGCHIP0_REG 0x17c
62 #define DA8XX_CFGCHIP1_REG 0x180
63 #define DA8XX_CFGCHIP2_REG 0x184
64 #define DA8XX_CFGCHIP3_REG 0x188
65 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_d.h26 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
27 #define ixPB0_DFT_JIT_INJ_REG0 0x13000
28 #define ixPB0_DFT_JIT_INJ_REG1 0x13004
29 #define ixPB0_DFT_JIT_INJ_REG2 0x13008
30 #define ixPB0_GLB_CTRL_REG0 0x10004
31 #define ixPB0_GLB_CTRL_REG1 0x10008
32 #define ixPB0_GLB_CTRL_REG2 0x1000C
33 #define ixPB0_GLB_CTRL_REG3 0x10010
34 #define ixPB0_GLB_CTRL_REG4 0x10014
35 #define ixPB0_GLB_CTRL_REG5 0x10018
[all …]
/kernel/linux/linux-5.10/sound/pci/au88x0/
Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]

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