/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
D | hisilicon-histb-pcie.txt | 38 - phys: List of phandle and phy mode specifier, should be 0. 44 reg = <0xf9860000 0x1000>, 45 <0xf0000000 0x2000>, 46 <0xf2000000 0x01000000>; 51 bus-range = <0 15>; 53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000 54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>; 58 interrupt-map-mask = <0 0 0 0>; 59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
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/kernel/linux/linux-5.10/drivers/media/platform/coda/ |
D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000 15 #define CODA_REG_RUN_ENABLE (1 << 0) 16 #define CODA_REG_BIT_CODE_DOWN 0x004 17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16) 18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff) 19 #define CODA_REG_BIT_HOST_IN_REQ 0x008 20 #define CODA_REG_BIT_INT_CLEAR 0x00c 21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1 22 #define CODA_REG_BIT_INT_STATUS 0x010 23 #define CODA_REG_BIT_CODE_RESET 0x014 [all …]
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/kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
D | crg-hi3798cv200.c | 45 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, 46 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, 47 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, 48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, 49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, 50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, 51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, 52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, 53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, 54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_doorbell.h | 85 AMDGPU_DOORBELL_KIQ = 0x000, 86 AMDGPU_DOORBELL_HIQ = 0x001, 87 AMDGPU_DOORBELL_DIQ = 0x002, 88 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 89 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 90 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 91 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 92 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 93 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 94 AMDGPU_DOORBELL_MEC_RING6 = 0x016, [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
D | hdmi4_core.h | 15 #define HDMI_CORE_SYS_VND_IDL 0x0 16 #define HDMI_CORE_SYS_DEV_IDL 0x8 17 #define HDMI_CORE_SYS_DEV_IDH 0xC 18 #define HDMI_CORE_SYS_DEV_REV 0x10 19 #define HDMI_CORE_SYS_SRST 0x14 20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20 21 #define HDMI_CORE_SYS_SYS_STAT 0x24 22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28 23 #define HDMI_CORE_SYS_DCTL 0x34 24 #define HDMI_CORE_SYS_DE_DLY 0xC8 [all …]
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/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
D | hdmi4_core.h | 15 #define HDMI_CORE_SYS_VND_IDL 0x0 16 #define HDMI_CORE_SYS_DEV_IDL 0x8 17 #define HDMI_CORE_SYS_DEV_IDH 0xC 18 #define HDMI_CORE_SYS_DEV_REV 0x10 19 #define HDMI_CORE_SYS_SRST 0x14 20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20 21 #define HDMI_CORE_SYS_SYS_STAT 0x24 22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28 23 #define HDMI_CORE_SYS_DCTL 0x34 24 #define HDMI_CORE_SYS_DE_DLY 0xC8 [all …]
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
D | ccu-sun50i-a100-r.c | 24 { .index = 3, .shift = 0, .width = 5 }, 39 .reg = 0x000, 44 0), 48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0); 51 .div = _SUNXI_CCU_DIV(0, 2), 54 .reg = 0x00c, 58 0), 74 .reg = 0x010, 79 0), 92 0x11c, BIT(0), 0); [all …]
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D | ccu-sun50i-h6-r.c | 28 { .index = 3, .shift = 0, .width = 5 }, 43 .reg = 0x000, 48 0), 52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0); 54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0); 68 .reg = 0x010, 73 0), 85 0x11c, BIT(0), 0); 87 0x12c, BIT(0), 0); 89 0x13c, BIT(0), 0); [all …]
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/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
D | phy-qcom-qmp.h | 10 #define QSERDES_COM_BG_TIMER 0x00c 11 #define QSERDES_COM_SSC_EN_CENTER 0x010 12 #define QSERDES_COM_SSC_ADJ_PER1 0x014 13 #define QSERDES_COM_SSC_ADJ_PER2 0x018 14 #define QSERDES_COM_SSC_PER1 0x01c 15 #define QSERDES_COM_SSC_PER2 0x020 16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19 #define QSERDES_COM_CLK_ENABLE1 0x038 [all …]
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/kernel/linux/linux-5.10/sound/soc/meson/ |
D | aiu.h | 18 PCLK = 0, 63 #define AIU_IEC958_BPF 0x000 64 #define AIU_958_MISC 0x010 65 #define AIU_IEC958_DCU_FF_CTRL 0x01c 66 #define AIU_958_CHSTAT_L0 0x020 67 #define AIU_958_CHSTAT_L1 0x024 68 #define AIU_958_CTRL 0x028 69 #define AIU_I2S_SOURCE_DESC 0x034 70 #define AIU_I2S_DAC_CFG 0x040 71 #define AIU_I2S_SYNC 0x044 [all …]
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/kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
D | mxregs.h | 20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p 21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p 22 * 0180 0...0m..m Clear enable specified by mask (m) 23 * 0184 0...0m..m Set enable specified by mask (m) 24 * 0190 0...0x..x 8-bit IPI partition register 30 * 0200 0...0m..m RunStall core 'n' 34 #define MIROUT(irq) (0x000 + (irq)) 35 #define MIPICAUSE(cpu) (0x100 + (cpu)) 36 #define MIPISET(cause) (0x140 + (cause)) 37 #define MIENG 0x180 [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
D | ti,iodelay.txt | 24 reg = <0x4844a000 0x0d1c>; 26 #size-cells = <0>; 35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ [all …]
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
D | tsi108.h | 18 #define TSI108_REG_SIZE (0x10000) 21 #define TSI108_HLP_SIZE 0x1000 22 #define TSI108_PCI_SIZE 0x1000 23 #define TSI108_CLK_SIZE 0x1000 24 #define TSI108_PB_SIZE 0x1000 25 #define TSI108_SD_SIZE 0x1000 26 #define TSI108_DMA_SIZE 0x1000 27 #define TSI108_ETH_SIZE 0x1000 28 #define TSI108_I2C_SIZE 0x400 29 #define TSI108_MPIC_SIZE 0x400 [all …]
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/kernel/linux/linux-5.10/drivers/pinctrl/ |
D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/kernel/linux/linux-5.10/tools/perf/arch/powerpc/util/ |
D | book3s_hcalls.h | 9 {0x4, "H_REMOVE"}, \ 10 {0x8, "H_ENTER"}, \ 11 {0xc, "H_READ"}, \ 12 {0x10, "H_CLEAR_MOD"}, \ 13 {0x14, "H_CLEAR_REF"}, \ 14 {0x18, "H_PROTECT"}, \ 15 {0x1c, "H_GET_TCE"}, \ 16 {0x20, "H_PUT_TCE"}, \ 17 {0x24, "H_SET_SPRG0"}, \ 18 {0x28, "H_SET_DABR"}, \ [all …]
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/kernel/linux/linux-5.10/include/linux/ |
D | tifm.h | 19 FM_SET_INTERRUPT_ENABLE = 0x008, 20 FM_CLEAR_INTERRUPT_ENABLE = 0x00c, 21 FM_INTERRUPT_STATUS = 0x014 26 SOCK_CONTROL = 0x004, 27 SOCK_PRESENT_STATE = 0x008, 28 SOCK_DMA_ADDRESS = 0x00c, 29 SOCK_DMA_CONTROL = 0x010, 30 SOCK_DMA_FIFO_INT_ENABLE_SET = 0x014, 31 SOCK_DMA_FIFO_INT_ENABLE_CLEAR = 0x018, 32 SOCK_DMA_FIFO_STATUS = 0x020, [all …]
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/kernel/linux/linux-5.10/arch/c6x/include/asm/ |
D | clock.h | 22 #define PLLCTL 0x100 23 #define PLLM 0x110 24 #define PLLPRE 0x114 25 #define PLLDIV1 0x118 26 #define PLLDIV2 0x11c 27 #define PLLDIV3 0x120 28 #define PLLPOST 0x128 29 #define PLLCMD 0x138 30 #define PLLSTAT 0x13c 31 #define PLLALNCTL 0x140 [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
D | hi3798cv200.dtsi | 27 #size-cells = <0>; 29 cpu@0 { 32 reg = <0x0 0x0>; 39 reg = <0x0 0x1>; 46 reg = <0x0 0x2>; 53 reg = <0x0 0x3>; 60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ 61 <0x0 0xf1002000 0x0 0x100>; /* GICC */ 62 #address-cells = <0>; 83 ranges = <0x0 0x0 0xf0000000 0x10000000>; [all …]
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/kernel/linux/linux-5.10/drivers/firewire/ |
D | ohci.h | 7 #define OHCI1394_Version 0x000 8 #define OHCI1394_GUID_ROM 0x004 9 #define OHCI1394_ATRetries 0x008 10 #define OHCI1394_CSRData 0x00C 11 #define OHCI1394_CSRCompareData 0x010 12 #define OHCI1394_CSRControl 0x014 13 #define OHCI1394_ConfigROMhdr 0x018 14 #define OHCI1394_BusID 0x01C 15 #define OHCI1394_BusOptions 0x020 16 #define OHCI1394_GUIDHi 0x024 [all …]
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